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39 lines
709 B
Systemverilog
39 lines
709 B
Systemverilog
// Simple RAM
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//
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// Copyright (c) 2025 David Hunter
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//
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// This program is GPL licensed. See COPYING for the full license.
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module ram
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#(parameter AW,
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parameter DW)
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(
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input CLK,
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input nCE,
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input nWE,
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input nOE,
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input [DW/8-1:0] nBE,
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input [AW-1:0] A,
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input [DW-1:0] DI,
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output [DW-1:0] DO
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);
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localparam SIZE = 1 << AW;
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bit [DW-1:0] mem [0:SIZE-1];
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bit [DW-1:0] dor;
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always @(posedge CLK) begin
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dor <= mem[A];
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end
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assign DO = ~(nCE | nOE) ? dor : {DW{1'bz}};
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always @(posedge CLK) begin
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for (int i = 0; i < DW/8; i++)
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if (~(nCE | nWE | nBE[i]))
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mem[A][i*8+:8] <= DI[i*8+:8];
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end
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endmodule
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