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https://github.com/MiSTer-devel/PCFX_MiSTer.git
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bd908cda3c
SDRAM burst reads/writes wrap column adds at the burst length. And pcfx_top was illegally doing a 32-bit write at an odd 16-bit boundary. Thus every other 16-bit word was being written to zero. This fixes both the SDRAM burst simulation and the odd address read/write.
68 lines
2.0 KiB
Systemverilog
68 lines
2.0 KiB
Systemverilog
// A FX-BMP with battery-backed SRAM, connected to the Memory Card Port
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//
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// Copyright (c) 2026 David Hunter
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//
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// This program is GPL licensed. See COPYING for the full license.
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module fx_bmp
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(
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// Emulation configuration
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input CFG_EN,
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input [2:0] CFG_SIZE, // 0=128KB, 1=256KB, 2=512KB, .. 6=8MB
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// Memory Card port interface
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input [26:1] MCP_A, // A24 is omitted
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input [7:0] MCP_DI,
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output [7:0] MCP_DO,
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input MCP_CSn, // aka /CartSel
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input MCP_RDn,
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input MCP_WRn,
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output MCP_READYn,
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// Memory interface
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output [22:0] RAM_A,
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output [7:0] RAM_DI,
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input [7:0] RAM_DO,
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output RAM_CEn,
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output RAM_WEn,
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input RAM_READYn
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);
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// Control size by masking (zeroing) RAM address bits above 128KB.
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logic [22:0] ram_a_mask;
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always @* begin
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ram_a_mask[16:0] = '1;
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case (CFG_SIZE)
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3'd0: ram_a_mask[22:17] = 'b000_000; // 128KB
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3'd1: ram_a_mask[22:17] = 'b000_001; // 256KB
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3'd2: ram_a_mask[22:17] = 'b000_011; // 512KB
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3'd3: ram_a_mask[22:17] = 'b000_111; // 1MB
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3'd4: ram_a_mask[22:17] = 'b001_111; // 2MB
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3'd5: ram_a_mask[22:17] = 'b011_111; // 4MB
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default:ram_a_mask[22:17] = 'b111_111; // 8MB
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endcase
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end
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// BMP address range is E800_0000 .. EBFF_FFFF -- half the port's addressable range.
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wire bmp_sel = ~(~CFG_EN | MCP_CSn | MCP_A[26]);
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// BMP memory is split down the middle:
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// E800_0000 + (0000_0000 .. 01FF_FFFE) is SRAM
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// E800_0000 + (0200_0000 .. 03FF_FFFE) is battery status
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wire sram_sel = bmp_sel & ~MCP_A[25];
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wire bat_sel = bmp_sel & MCP_A[25];
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// The battery is always "good".
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wire bat_good = '1;
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assign RAM_A = MCP_A[23:1] & ram_a_mask;
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assign RAM_DI = MCP_DI;
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assign RAM_CEn = ~sram_sel;
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assign RAM_WEn = RAM_CEn | MCP_WRn;
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assign MCP_DO = {8{~bmp_sel}} | (bat_sel ? {7'h7F, bat_good} : RAM_DO);
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assign MCP_READYn = MCP_CSn | (sram_sel & RAM_READYn);
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endmodule
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