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Three bugs: - Sense data was missing additional sense length and code - HuC6272 must not drive SCSI data out when IO line is asserted (bus contention) - SCSI data into HuC6272 was delayed one clock, causing a full byte shift
73 lines
1.8 KiB
Systemverilog
73 lines
1.8 KiB
Systemverilog
// Fake an empty CD drive on the SCSI-CD bridge
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//
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// Copyright (c) 2025 David Hunter
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//
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// This program is GPL licensed. See COPYING for the full license.
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module fake_cd
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(
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input CLK,
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input RESn,
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output reg STAT_GET,
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input [95:0] COMMAND,
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input COMM_SEND,
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output reg [7:0] STATUS,
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output reg [7:0] CD_DATA,
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output reg CD_WR
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);
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logic req_sense;
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logic [4:0] req_st;
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always @(posedge CLK) begin
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if (~RESn) begin
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STAT_GET <= '0;
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STATUS <= '0;
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CD_DATA <= 8'h00;
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CD_WR <= '0;
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req_sense <= '0;
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req_st <= '0;
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end
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else begin
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if (COMM_SEND) begin
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case (COMMAND[7:0] )
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/*8'h00,*/ // TEST UNIT READY
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default: begin
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STAT_GET <= '1;
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STATUS <= 8'h02; // CHECK CONDITION
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end
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8'h03: req_sense <= '1; // REQUEST SENSE
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endcase
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end
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if (req_sense) begin
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case (req_st)
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'd0: CD_DATA <= 8'h70;
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'd2: CD_DATA <= 8'h02; // Sense key: NOT READY
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'd7: CD_DATA <= 8'h0A; // Additional sense length
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'd12:CD_DATA <= 8'h0B; // Additional sense code: ABORTED COMMAND
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default: CD_DATA <= 8'h00;
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endcase
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if (req_st == 'd18) begin
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STAT_GET <= '1;
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STATUS <= 8'h00; // GOOD
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CD_WR <= '0;
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req_sense <= '0;
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req_st <= '0;
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end
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else begin
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CD_WR <= ~CD_WR;
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if (CD_WR)
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req_st <= req_st + 1'd1;
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end
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end
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if (STAT_GET) begin
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STAT_GET <= '0;
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end
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end
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end
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endmodule
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