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85 lines
2.2 KiB
Systemverilog
85 lines
2.2 KiB
Systemverilog
// True dual-port RAM
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//
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// Translated from TurboGrafx16_MiSTer/rtl/dpram.vhd
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//
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// Copyright (c) 2025 David Hunter
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//
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// This program is GPL licensed. See COPYING for the full license.
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module dpram
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#(parameter int addr_width = 8,
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parameter int data_width = 8,
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parameter string mem_init_file = " ",
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parameter reg disable_value = 1'b1
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)
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(
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input clock,
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input [addr_width-1:0] address_a,
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input [data_width-1:0] data_a,
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input enable_a,
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input wren_a,
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output reg [data_width-1:0] q_a,
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input cs_a,
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input [addr_width-1:0] address_b,
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input [data_width-1:0] data_b,
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input enable_b,
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input wren_b,
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output reg [data_width-1:0] q_b,
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input cs_b
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);
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reg [data_width-1:0] q0, q1;
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always @* begin
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q_a = cs_a ? q0 : {data_width{disable_value}};
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q_b = cs_b ? q1 : {data_width{disable_value}};
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end
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altsyncram
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#(
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.address_reg_b("CLOCK1"),
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.clock_enable_input_a("NORMAL"),
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.clock_enable_input_b("NORMAL"),
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.clock_enable_output_a("BYPASS"),
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.clock_enable_output_b("BYPASS"),
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.indata_reg_b("CLOCK1"),
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.intended_device_family("Cyclone V"),
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.lpm_type("altsyncram"),
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.numwords_a((1 << addr_width)),
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.numwords_b((1 << addr_width)),
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.operation_mode("BIDIR_DUAL_PORT"),
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.outdata_aclr_a("NONE"),
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.outdata_aclr_b("NONE"),
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.outdata_reg_a("UNREGISTERED"),
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.outdata_reg_b("UNREGISTERED"),
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.power_up_uninitialized("FALSE"),
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.read_during_write_mode_port_a("NEW_DATA_NO_NBE_READ"),
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.read_during_write_mode_port_b("NEW_DATA_NO_NBE_READ"),
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.init_file(mem_init_file),
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.widthad_a(addr_width),
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.widthad_b(addr_width),
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.width_a(data_width),
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.width_b(data_width),
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.width_byteena_a(1),
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.width_byteena_b(1),
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.wrcontrol_wraddress_reg_b("CLOCK1")
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)
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altsyncram_component
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(
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.address_a(address_a),
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.address_b(address_b),
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.clock0(clock),
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.clock1(clock),
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.clocken0(enable_a),
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.clocken1(enable_b),
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.data_a(data_a),
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.data_b(data_b),
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.wren_a(wren_a & cs_a),
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.wren_b(wren_b & cs_b),
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.q_a(q0),
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.q_b(q1)
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);
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endmodule
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