//============================================================================ // NEC PC-FX // // Copyright (c) 2025-2026 David Hunter // // This program is free software; you can redistribute it and/or modify it // under the terms of the GNU General Public License as published by the Free // Software Foundation; either version 2 of the License, or (at your option) // any later version. // // This program is distributed in the hope that it will be useful, but WITHOUT // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for // more details. // // You should have received a copy of the GNU General Public License along // with this program; if not, write to the Free Software Foundation, Inc., // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. // //============================================================================ module emu ( //Master input clock input CLK_50M, //Async reset from top-level module. //Can be used as initial reset. input RESET, //Must be passed to hps_io module inout [48:0] HPS_BUS, //Base video clock. Usually equals to CLK_SYS. output CLK_VIDEO, //Multiple resolutions are supported using different CE_PIXEL rates. //Must be based on CLK_VIDEO output CE_PIXEL, //Video aspect ratio for HDMI. Most retro systems have ratio 4:3. //if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio. output [12:0] VIDEO_ARX, output [12:0] VIDEO_ARY, output [7:0] VGA_R, output [7:0] VGA_G, output [7:0] VGA_B, output VGA_HS, output VGA_VS, output VGA_DE, // = ~(VBlank | HBlank) output VGA_F1, output [1:0] VGA_SL, output VGA_SCALER, // Force VGA scaler output VGA_DISABLE, // analog out is off input [11:0] HDMI_WIDTH, input [11:0] HDMI_HEIGHT, output HDMI_FREEZE, output HDMI_BLACKOUT, output HDMI_BOB_DEINT, `ifdef MISTER_FB // Use framebuffer in DDRAM // FB_FORMAT: // [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp // [3] : 0=16bits 565 1=16bits 1555 // [4] : 0=RGB 1=BGR (for 16/24/32 modes) // // FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes) output FB_EN, output [4:0] FB_FORMAT, output [11:0] FB_WIDTH, output [11:0] FB_HEIGHT, output [31:0] FB_BASE, output [13:0] FB_STRIDE, input FB_VBL, input FB_LL, output FB_FORCE_BLANK, `ifdef MISTER_FB_PALETTE // Palette control for 8bit modes. // Ignored for other video modes. output FB_PAL_CLK, output [7:0] FB_PAL_ADDR, output [23:0] FB_PAL_DOUT, input [23:0] FB_PAL_DIN, output FB_PAL_WR, `endif `endif output LED_USER, // 1 - ON, 0 - OFF. // b[1]: 0 - LED status is system status OR'd with b[0] // 1 - LED status is controled solely by b[0] // hint: supply 2'b00 to let the system control the LED. output [1:0] LED_POWER, output [1:0] LED_DISK, // I/O board button press simulation (active high) // b[1]: user button // b[0]: osd button output [1:0] BUTTONS, input CLK_AUDIO, // 24.576 MHz output [15:0] AUDIO_L, output [15:0] AUDIO_R, output AUDIO_S, // 1 - signed audio samples, 0 - unsigned output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono) //ADC inout [3:0] ADC_BUS, //SD-SPI output SD_SCK, output SD_MOSI, input SD_MISO, output SD_CS, input SD_CD, //High latency DDR3 RAM interface //Use for non-critical time purposes output DDRAM_CLK, input DDRAM_BUSY, output [7:0] DDRAM_BURSTCNT, output [28:0] DDRAM_ADDR, input [63:0] DDRAM_DOUT, input DDRAM_DOUT_READY, output DDRAM_RD, output [63:0] DDRAM_DIN, output [7:0] DDRAM_BE, output DDRAM_WE, //SDRAM interface with lower latency output SDRAM_CLK, output SDRAM_CKE, output [12:0] SDRAM_A, output [1:0] SDRAM_BA, inout [15:0] SDRAM_DQ, output SDRAM_DQML, output SDRAM_DQMH, output SDRAM_nCS, output SDRAM_nCAS, output SDRAM_nRAS, output SDRAM_nWE, `ifdef MISTER_DUAL_SDRAM //Secondary SDRAM //Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0 input SDRAM2_EN, output SDRAM2_CLK, output [12:0] SDRAM2_A, output [1:0] SDRAM2_BA, inout [15:0] SDRAM2_DQ, output SDRAM2_nCS, output SDRAM2_nCAS, output SDRAM2_nRAS, output SDRAM2_nWE, `endif input UART_CTS, output UART_RTS, input UART_RXD, output UART_TXD, output UART_DTR, input UART_DSR, // Open-drain User port. // 0 - D+/RX // 1 - D-/TX // 2..6 - USR2..USR6 // Set USER_OUT to 1 to read from USER_IN. input [6:0] USER_IN, output [6:0] USER_OUT, input OSD_STATUS ); ///////// Default values for ports not used in this core ///////// assign ADC_BUS = 'Z; assign USER_OUT = '1; assign {UART_RTS, UART_TXD, UART_DTR} = 0; assign {SD_SCK, SD_MOSI, SD_CS} = 'Z; assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0; assign VGA_SL = 0; assign VGA_F1 = 0; assign VGA_SCALER = 0; assign VGA_DISABLE = 0; assign HDMI_FREEZE = 0; assign HDMI_BLACKOUT = 0; assign HDMI_BOB_DEINT = 0; assign AUDIO_S = 0; assign AUDIO_L = 0; assign AUDIO_R = 0; assign AUDIO_MIX = 0; assign LED_DISK = 0; assign LED_POWER = 0; assign BUTTONS = 0; ////////////////////////////////////////////////////////////////// wire [1:0] ar = status[22:21]; assign VIDEO_ARX = (!ar) ? 12'd4 : (ar - 1'd1); assign VIDEO_ARY = (!ar) ? 12'd3 : 12'd0; // Status Bit Map: // 0 1 2 3 4 5 6 // 01234567890123456789012345678901 23456789012345678901234567890123 // 0123456789ABCDEFGHIJKLMNOPQRSTUV 0123456789ABCDEFGHIJKLMNOPQRSTUV // X XXX XX `include "build_id.v" localparam CONF_STR = { "PCFX;;", "-;", "O[22:21],Aspect ratio,Original,Full Screen,[ARC1],[ARC2];", "-;", "D0S0,SAVBIN,Mount int. backup RAM;", "D1S1,FXBBIN,Mount FX-BMP backup RAM;", "D2R7,Load backup RAM;", "D2R8,Save backup RAM;", "-;", "F1,ROMBIN,Load custom BIOS;", "F2,FXB,Load FX-BMP ROM;", "D3T9,Unload FX-BMP ROM;", "-;", "T[0],Reset;", "R[0],Reset and close OSD;", "J1,Button I,Button II,Select,Run,Button III,Button IV,Button V,Button VI;", "jn,A,B,Select,Start,X,Y,L,R;", "jp,A,B,Select,Start,L,R,Y,X;", "v,0;", "V,v",`BUILD_DATE }; wire forced_scandoubler; wire [1:0] buttons; wire [127:0] status; wire [31:0] joystick_0, joystick_1; wire [10:0] ps2_key; wire [1:0] img_mounted; wire img_readonly; wire [63:0] img_size; wire [31:0] sd_lba; wire [1:0] sd_rd; wire [1:0] sd_wr; wire [1:0] sd_ack; wire [7:0] sd_buff_addr; wire [15:0] sd_buff_dout; wire [15:0] sd_buff_din; wire sd_buff_wr; wire ioctl_download; wire [7:0] ioctl_index; wire ioctl_wr; wire [24:0] ioctl_addr; wire [15:0] ioctl_dout; wire ioctl_wait; wire bk_ena; wire [1:0] bk_ena_img_mount; wire bmp_rom_inserted; hps_io #(.CONF_STR(CONF_STR), .WIDE(1), .VDNUM(2)) hps_io ( .clk_sys(clk_sys), .HPS_BUS(HPS_BUS), .buttons(buttons), .forced_scandoubler(forced_scandoubler), .gamma_bus(), .status(status), .status_menumask({~bmp_rom_inserted, ~bk_ena, ~bk_ena_img_mount}), .joystick_0(joystick_0), .joystick_1(joystick_1), .ps2_key(ps2_key), .img_mounted(img_mounted), .img_readonly(img_readonly), .img_size(img_size), .sd_lba('{sd_lba, sd_lba}), .sd_rd(sd_rd), .sd_wr(sd_wr), .sd_ack(sd_ack), .sd_buff_addr(sd_buff_addr), .sd_buff_dout(sd_buff_dout), .sd_buff_din('{sd_buff_din, sd_buff_din}), .sd_buff_wr(sd_buff_wr), .ioctl_download(ioctl_download), .ioctl_index(ioctl_index), .ioctl_wr(ioctl_wr), .ioctl_addr(ioctl_addr), .ioctl_dout(ioctl_dout), .ioctl_wait(ioctl_wait), .EXT_BUS() ); /////////////////////// CLOCKS /////////////////////////////// wire clk_sys, clk_ram; wire pll_locked; pll pll ( .refclk(CLK_50M), .rst(0), .outclk_0(clk_sys), .outclk_1(clk_ram), .locked(pll_locked) ); wire reset = RESET | status[0] | buttons[1]; ////////////////////////////////////////////////////////////////////// // Connect input sources to HMI hmi_t hmi; task joy2hmi(input [31:0] joy, output joypad_t jp); {jp.u, jp.d, jp.l, jp.r} = joy[3:0]; {jp.b[6:3], jp.run, jp.select, jp.b[2:1]} = joy[11:4]; {jp.mode2, jp.mode1} = '0; endtask initial hmi = '0; always @joystick_0 joy2hmi(joystick_0, hmi.jp1); always @joystick_1 joy2hmi(joystick_1, hmi.jp2); ////////////////////////////////////////////////////////////////////// wire error; wire HBlank; wire HSync; wire VBlank; wire VSync; wire ce_pix; pcfx_top pcfx_top ( .clk_sys(clk_sys), .clk_ram(clk_ram), .reset(reset), .pll_locked(pll_locked), .img_mounted(img_mounted), .img_readonly(img_readonly), .img_size(img_size), .sd_lba(sd_lba), .sd_rd(sd_rd), .sd_wr(sd_wr), .sd_ack(sd_ack), .sd_buff_addr(sd_buff_addr), .sd_buff_dout(sd_buff_dout), .sd_buff_din(sd_buff_din), .sd_buff_wr(sd_buff_wr), .ioctl_download(ioctl_download), .ioctl_index(ioctl_index), .ioctl_wr(ioctl_wr), .ioctl_addr(ioctl_addr), .ioctl_dout(ioctl_dout), .ioctl_wait(ioctl_wait), .bk_ena_img_mount(bk_ena_img_mount), .bk_ena(bk_ena), .bk_load(status[7]), .bk_save(status[8]), .bmp_rom_inserted(bmp_rom_inserted), .bmp_eject_rom(status[9]), .HMI(hmi), .SDRAM_CLK(SDRAM_CLK), .SDRAM_CKE(SDRAM_CKE), .SDRAM_A(SDRAM_A), .SDRAM_BA(SDRAM_BA), .SDRAM_DQ(SDRAM_DQ), .SDRAM_DQML(SDRAM_DQML), .SDRAM_DQMH(SDRAM_DQMH), .SDRAM_nCS(SDRAM_nCS), .SDRAM_nCAS(SDRAM_nCAS), .SDRAM_nRAS(SDRAM_nRAS), .SDRAM_nWE(SDRAM_nWE), .ERROR(error), .ce_pix(ce_pix), .HBlank(HBlank), .HSync(HSync), .VBlank(VBlank), .VSync(VSync), .R(VGA_R), .G(VGA_G), .B(VGA_B) ); assign CLK_VIDEO = clk_sys; assign CE_PIXEL = ce_pix; assign VGA_DE = ~(HBlank | VBlank); assign VGA_HS = HSync; assign VGA_VS = VSync; assign LED_USER = error; endmodule