diff --git a/rtl/huc6261.sv b/rtl/huc6261.sv
index 69e4841..3dd9ba3 100644
--- a/rtl/huc6261.sv
+++ b/rtl/huc6261.sv
@@ -682,17 +682,23 @@ always @* begin
     ccdp_reg1_en = '0;
     ccdp_low_chroma = '0;
 
-    if (ccdp_phase < 2'd3) begin
-        prio_sel = ccdp_phase;
-        ccdp_reg1_en = mix.key;
-        ccdp_sel1_ccr = '0;
-        ccdp_sel2_cc = mix.cpe != CPE_OFF;
-    end
-    if (ccdp_phase == 2'd0 && !(ble.ed & ~ble.fb)) begin
-        // Special case for lowest priority layer
-        ccdp_low_chroma = '1;
+    if (cr.dc7) begin
+        prio_sel = 2'd2;
         ccdp_reg1_en = '1;
     end
+    else begin
+        if (ccdp_phase < 2'd3) begin
+            prio_sel = ccdp_phase;
+            ccdp_reg1_en = mix.key;
+            ccdp_sel1_ccr = '0;
+            ccdp_sel2_cc = mix.cpe != CPE_OFF;
+        end
+        if (ccdp_phase == 2'd0 && !(ble.ed & ~ble.fb)) begin
+            // Special case for lowest priority layer
+            ccdp_low_chroma = '1;
+            ccdp_reg1_en = '1;
+        end
+    end
 end
 
 assign vmux_low_chroma = ccdp_low_chroma;
diff --git a/rtl/tb/huc6261_video_render.gtkw b/rtl/tb/huc6261_video_render.gtkw
index c706577..48b73ce 100644
--- a/rtl/tb/huc6261_video_render.gtkw
+++ b/rtl/tb/huc6261_video_render.gtkw
@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v4.0.0-prealpha (8ba24ab+) (w)1999-2022 BSI
-[*] Tue May 12 04:46:18 2026
+[*] Fri May 15 04:44:32 2026
 [*]
 [dumpfile] "/Users/dhunter/src/mister/PCFX_MiSTer/rtl/tb/huc6261_video_render_tb.vcd"
-[dumpfile_mtime] "Tue May 12 04:45:50 2026"
-[dumpfile_size] 341812845
+[dumpfile_mtime] "Fri May 15 04:44:32 2026"
+[dumpfile_size] 125861888
 [savefile] "/Users/dhunter/src/mister/PCFX_MiSTer/rtl/tb/huc6261_video_render.gtkw"
-[timestart] 12969610
+[timestart] 13001708
 [size] 1333 600
 [pos] -1 -1
-*-7.824339 12970260 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+*-7.829422 13002540 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 [markername] AA
 [markername] BB
 [markername] CC
@@ -37,15 +37,14 @@
 [markername] YY
 [markername] ZZ
 [treeopen] huc6261_video_render_tb.
+[treeopen] huc6261_video_render_tb.vce.
 [sst_width] 255
 [signals_width] 229
 [sst_expanded] 1
 [sst_vpaned_height] 159
 @22
 huc6261_video_render_tb.vce.vmux[30:0]
-@23
 huc6261_video_render_tb.vce.mix_vd[23:0]
-@22
 huc6261_video_render_tb.vce.spbl[15:0]
 @28
 huc6261_video_render_tb.vdc0.DMAS_EXEC
@@ -59,13 +58,18 @@ huc6261_video_render_tb.vdc0.VDISP_END_POS[9:0]
 huc6261_video_render_tb.vdc0.HSYNC_F
 huc6261_video_render_tb.vdc0.VSYNC_F
 huc6261_video_render_tb.vce.VBL
+huc6261_video_render_tb.vce.HBL
 @22
 huc6261_video_render_tb.vce.v_cnt[8:0]
+huc6261_video_render_tb.vce.h_cnt[11:0]
 huc6261_video_render_tb.mmc.video.row[9:0]
 @28
 huc6261_video_render_tb.vce.prio_out[1:0]
 huc6261_video_render_tb.vce.CLK
 huc6261_video_render_tb.vce.ckenf
+@29
+huc6261_video_render_tb.vce.DCK70
+@28
 huc6261_video_render_tb.vce.ckenkr
 huc6261_video_render_tb.vce.prio_sel[1:0]
 huc6261_video_render_tb.vce.vmux_low_chroma
diff --git a/rtl/tb/huc6261_video_render_tb.sv b/rtl/tb/huc6261_video_render_tb.sv
index 3be57c1..8b65b00 100644
--- a/rtl/tb/huc6261_video_render_tb.sv
+++ b/rtl/tb/huc6261_video_render_tb.sv
@@ -16,6 +16,7 @@ initial begin
 end
 
 `include "mmc_kram_vce.svh"
+`include "video_filemgr.svh"
 
 //////////////////////////////////////////////////////////////////////
 
@@ -27,7 +28,7 @@ initial begin
     pice = 0;
 end
 always @(posedge clk) begin
-    if (dck) begin
+    if (dck70) begin
         if (vce_vde) begin
             $fwrite(fpic, "%x", vce_vd);
             pice = 1;
@@ -43,125 +44,8 @@ final
 
 //////////////////////////////////////////////////////////////////////
 
-task load_vce_reg();
-    io_sel = VCE;
-    reg_write(7'h00, 16'h0700); // CR
-    reg_write(7'h04, 16'h0800); // CPAO1
-    reg_write(7'h08, 16'h0567); // PR1
-    reg_write(7'h09, 16'h0004); // PR2
-    reg_write(7'h0d, 16'hFF88); // CCR
-    reg_write(7'h0e, 16'h0008); // BLE
-    reg_write(7'h0f, 16'h0100); // SPBL
-    reg_write(7'h10, 16'h0000); // BL1A
-    reg_write(7'h11, 16'h0888); // BL1B
-    reg_write(7'h12, 16'h0222); // BL2A
-    reg_write(7'h13, 16'h0666); // BL2B
-    reg_write(7'h14, 16'h0000); // BL3A
-    reg_write(7'h15, 16'h0000); // BL3B
-
-    // Palette
-    //reg_write(7'h01, 16'h0000); // addr = 0
-    //reg_write(7'h02, 16'h0000); // ent[0]
-endtask
-
-task load_vdc0_reg();
-    io_sel = VDC0;
-    reg_write(7'h05, 16'h00c8); // CR
-    reg_write(7'h06, 16'h0000); // RCR
-    reg_write(7'h07, 16'h0000); // BXR
-    reg_write(7'h08, 16'h0000); // BYR
-    reg_write(7'h09, 16'h0050); // MWR
-    reg_write(7'h0a, 16'h0202); // HSR
-    reg_write(7'h0b, 16'h041f); // HDR
-    reg_write(7'h0c, 16'h1102); // VPR
-    reg_write(7'h0d, 16'h00ef); // VDR
-    reg_write(7'h0e, 16'h0002); // VCR
-    reg_write(7'h13, 16'h7f00); // DVSSR
-endtask
-
-task load_vdc1_reg();
-    io_sel = VDC1;
-    reg_write(7'h05, 16'h00c0); // CR
-    reg_write(7'h06, 16'h0000); // RCR
-    reg_write(7'h07, 16'h0000); // BXR
-    reg_write(7'h08, 16'hfff8); // BYR
-    reg_write(7'h09, 16'h0050); // MWR
-    reg_write(7'h0a, 16'h0202); // HSR
-    reg_write(7'h0b, 16'h041f); // HDR
-    reg_write(7'h0c, 16'h1102); // VPR
-    reg_write(7'h0d, 16'h00ef); // VDR
-    reg_write(7'h0e, 16'h0002); // VCR
-    reg_write(7'h13, 16'h7f00); // DVSSR
-endtask
-
-task load_kreg();
-    // KING BG
-    io_sel = MMC;
-    reg_write(7'h10, 16'h0005); // Mode
-    reg_write(7'h12, 16'h0004); // Prio
-    reg_write(7'h16, 16'h0001); // ScrM
-    // KBG0
-    reg_write(7'h2c, 16'h8888); // Size
-    reg_write(7'h20, 16'h0000); // BAT
-    reg_write(7'h21, 16'h0080); // CG
-    reg_write(7'h22, 16'h0000); // SubBAT
-    reg_write(7'h23, 16'h0080); // SubCG
-    reg_write(7'h30, 16'h0000); // XScr
-    reg_write(7'h31, 16'h0000); // YScr
-    // KBG1
-    reg_write(7'h2d, 16'h0000); // Size
-    reg_write(7'h24, 16'h0000); // BAT
-    reg_write(7'h25, 16'h0000); // CG
-    reg_write(7'h32, 16'h0000); // XScr
-    reg_write(7'h33, 16'h0000); // YScr
-    // KBG2
-    reg_write(7'h2e, 16'h0000); // Size
-    reg_write(7'h28, 16'h0000); // BAT
-    reg_write(7'h29, 16'h0000); // CG
-    reg_write(7'h34, 16'h0000); // XScr
-    reg_write(7'h35, 16'h0000); // YScr
-    // KBG3
-    reg_write(7'h2f, 16'h0000); // Size
-    reg_write(7'h2a, 16'h0000); // BAT
-    reg_write(7'h2b, 16'h0000); // CG
-    reg_write(7'h34, 16'h0000); // XScr
-    reg_write(7'h35, 16'h0000); // YScr
-    // AFFIN
-    reg_write(7'h38, 16'h0000); // A
-    reg_write(7'h39, 16'h0000); // B
-    reg_write(7'h3a, 16'h0000); // C
-    reg_write(7'h3b, 16'h0000); // D
-    reg_write(7'h3c, 16'h0000); // X
-    reg_write(7'h3d, 16'h0000); // Y
-    // MPROG
-    reg_write(7'h13, 16'h0000); // uAddr=0
-    reg_write(7'h14, 16'h0100); // 0
-    reg_write(7'h14, 16'h0100); // 1
-    reg_write(7'h14, 16'h0100); // 2
-    reg_write(7'h14, 16'h0100); // 3
-    reg_write(7'h14, 16'h0100); // 4
-    reg_write(7'h14, 16'h0100); // 5
-    reg_write(7'h14, 16'h0100); // 6
-    reg_write(7'h14, 16'h0100); // 7
-    reg_write(7'h14, 16'h0000); // 8
-    reg_write(7'h14, 16'h0001); // 9
-    reg_write(7'h14, 16'h0002); // A
-    reg_write(7'h14, 16'h0003); // B
-    reg_write(7'h14, 16'h0004); // C
-    reg_write(7'h14, 16'h0005); // D
-    reg_write(7'h14, 16'h0006); // E
-    reg_write(7'h14, 16'h0007); // F
-    reg_write(7'h15, 16'h0001); // MPSW=1
-endtask
-
-//////////////////////////////////////////////////////////////////////
-
 initial #0 begin
-    $readmemh("vram0.hex", vram0.mem);
-    $readmemh("vram1.hex", vram1.mem);
-    $readmemh("vce_cp.hex", vce.cpram.mem);
-    vram_load_file("kram0.bin", 0);
-    vram_load_file("kram1.bin", 1);
+    load_vmem();
 
     #10 @(posedge clk) reset <= 0;
     #2 @(posedge clk) ;
@@ -190,5 +74,5 @@ endmodule
 
 
 // Local Variables:
-// compile-command: "iverilog -g2012 -grelative-include -s huc6261_video_render_tb -DHUC6272_DMC_ENABLE -DTB_VDC -o huc6261_video_render_tb.vvp ../huc6272.sv ../huc6261.sv ../huc6270.sv dpram.sv pd424260.sv huc6261_video_render_tb.sv && ./huc6261_video_render_tb.vvp && python3 yuv_render2png.py huc6261_video_render.hex huc6261_video_render.png 270 242"
+// compile-command: "iverilog -g2012 -grelative-include -s huc6261_video_render_tb -DHUC6272_DMC_ENABLE -DTB_VDC -o huc6261_video_render_tb.vvp ../huc6272.sv ../huc6261.sv ../huc6270.sv dpram.sv pd424260.sv huc6261_video_render_tb.sv && ./huc6261_video_render_tb.vvp && python3 yuv_render2png.py huc6261_video_render.hex huc6261_video_render.png 360 242"
 // End:
diff --git a/rtl/tb/video_filemgr.svh b/rtl/tb/video_filemgr.svh
new file mode 100644
index 0000000..98afe84
--- /dev/null
+++ b/rtl/tb/video_filemgr.svh
@@ -0,0 +1,120 @@
+// PC-FX File Manager
+
+task load_vce_reg();
+    io_sel = VCE;
+    reg_write(7'h00, 16'h0348); // CR
+    reg_write(7'h04, 16'h0000); // CPO1
+    reg_write(7'h05, 16'h2828); // CPO2
+    reg_write(7'h06, 16'h2828); // CPO3
+    reg_write(7'h07, 16'h0028); // CPO4
+    reg_write(7'h08, 16'h0576); // PR1
+    reg_write(7'h09, 16'h4321); // PR2
+    reg_write(7'h0d, 16'h0088); // CCR
+    reg_write(7'h0e, 16'h0000); // BLE
+    reg_write(7'h0f, 16'h0000); // SPBL
+    reg_write(7'h10, 16'h0444); // BL1A
+    reg_write(7'h11, 16'h0444); // BL1B
+    reg_write(7'h12, 16'h0444); // BL2A
+    reg_write(7'h13, 16'h0444); // BL2B
+    reg_write(7'h14, 16'h0444); // BL3A
+    reg_write(7'h15, 16'h0444); // BL3B
+endtask
+
+task load_vdc0_reg();
+    io_sel = VDC0;
+    reg_write(7'h05, 16'h00c8); // CR
+    reg_write(7'h06, 16'h0000); // RCR
+    reg_write(7'h07, 16'h0000); // BXR
+    reg_write(7'h08, 16'h0000); // BYR
+    reg_write(7'h09, 16'h0010); // MWR
+    reg_write(7'h0a, 16'h0503); // HSR
+    reg_write(7'h0b, 16'h0227); // HDR
+    reg_write(7'h0c, 16'h1002); // VPR
+    reg_write(7'h0d, 16'h00ff); // VDR
+    reg_write(7'h0e, 16'h001b); // VCR
+    reg_write(7'h0f, 16'h0010); // DCR
+    reg_write(7'h13, 16'h0800); // DVSSR
+endtask
+
+task load_vdc1_reg();
+    io_sel = VDC1;
+    reg_write(7'h05, 16'h0040); // CR
+    reg_write(7'h06, 16'h0000); // RCR
+    reg_write(7'h07, 16'h0000); // BXR
+    reg_write(7'h08, 16'h0000); // BYR
+    reg_write(7'h09, 16'h0010); // MWR
+    reg_write(7'h0a, 16'h0503); // HSR
+    reg_write(7'h0b, 16'h0227); // HDR
+    reg_write(7'h0c, 16'h1002); // VPR
+    reg_write(7'h0d, 16'h00ff); // VDR
+    reg_write(7'h0e, 16'h001b); // VCR
+    reg_write(7'h0f, 16'h0010); // DCR
+    reg_write(7'h13, 16'h0800); // DVSSR
+endtask
+
+task load_kreg();
+    // KING BG
+    io_sel = MMC;
+    reg_write(7'h10, 16'h000B); // Mode
+    reg_write(7'h12, 16'h1004); // Prio
+    reg_write(7'h16, 16'h0001); // ScrM
+    // KBG0
+    reg_write(7'h2c, 16'h9898); // Size
+    reg_write(7'h20, 16'h00C0); // BAT
+    reg_write(7'h21, 16'h0000); // CG
+    reg_write(7'h22, 16'h00C0); // SubBAT
+    reg_write(7'h23, 16'h0000); // SubCG
+    reg_write(7'h30, 16'h0000); // XScr
+    reg_write(7'h31, 16'h0000); // YScr
+    // KBG1
+    reg_write(7'h2d, 16'h0000); // Size
+    reg_write(7'h24, 16'h0000); // BAT
+    reg_write(7'h25, 16'h0000); // CG
+    reg_write(7'h32, 16'h0000); // XScr
+    reg_write(7'h33, 16'h0000); // YScr
+    // KBG2
+    reg_write(7'h2e, 16'h0000); // Size
+    reg_write(7'h28, 16'h0000); // BAT
+    reg_write(7'h29, 16'h0000); // CG
+    reg_write(7'h34, 16'h0000); // XScr
+    reg_write(7'h35, 16'h0000); // YScr
+    // KBG3
+    reg_write(7'h2f, 16'h0000); // Size
+    reg_write(7'h2a, 16'h0000); // BAT
+    reg_write(7'h2b, 16'h0000); // CG
+    reg_write(7'h34, 16'h0000); // XScr
+    reg_write(7'h35, 16'h0000); // YScr
+    // AFFIN
+    reg_write(7'h38, 16'h0100); // A
+    reg_write(7'h39, 16'h0000); // B
+    reg_write(7'h3a, 16'h0000); // C
+    reg_write(7'h3b, 16'h0100); // D
+    reg_write(7'h3c, 16'h0080); // X
+    reg_write(7'h3d, 16'h0080); // Y
+    // MPROG
+    reg_write(7'h13, 16'h0000); // uAddr=0
+    reg_write(7'h14, 16'h0000); // 0
+    reg_write(7'h14, 16'h0000); // 1
+    reg_write(7'h14, 16'h0000); // 2
+    reg_write(7'h14, 16'h0000); // 3
+    reg_write(7'h14, 16'h0000); // 4
+    reg_write(7'h14, 16'h0000); // 5
+    reg_write(7'h14, 16'h0000); // 6
+    reg_write(7'h14, 16'h0038); // 7
+    reg_write(7'h14, 16'h0038); // 8
+    reg_write(7'h14, 16'h0038); // 9
+    reg_write(7'h14, 16'h0038); // A
+    reg_write(7'h14, 16'h0038); // B
+    reg_write(7'h14, 16'h0038); // C
+    reg_write(7'h14, 16'h0038); // D
+    reg_write(7'h14, 16'h0038); // E
+    reg_write(7'h14, 16'h0038); // F
+    reg_write(7'h15, 16'h0001); // MPSW=1
+endtask
+
+task load_vmem();
+    $readmemh("vram0-filemgr.hex", vram0.mem);
+    $readmemh("vram1-filemgr.hex", vram1.mem);
+    $readmemh("vce_cp-filemgr.hex", vce.cpram.mem);
+endtask
+
diff --git a/rtl/tb/video_mainmenu.svh b/rtl/tb/video_mainmenu.svh
new file mode 100644
index 0000000..66f860c
--- /dev/null
+++ b/rtl/tb/video_mainmenu.svh
@@ -0,0 +1,121 @@
+// PC-FX main menu (CD ejected)
+
+task load_vce_reg();
+    io_sel = VCE;
+    reg_write(7'h00, 16'h0700); // CR
+    reg_write(7'h04, 16'h0800); // CPO1
+    reg_write(7'h08, 16'h0567); // PR1
+    reg_write(7'h09, 16'h0004); // PR2
+    reg_write(7'h0d, 16'hFF88); // CCR
+    reg_write(7'h0e, 16'h0008); // BLE
+    reg_write(7'h0f, 16'h0100); // SPBL
+    reg_write(7'h10, 16'h0000); // BL1A
+    reg_write(7'h11, 16'h0888); // BL1B
+    reg_write(7'h12, 16'h0222); // BL2A
+    reg_write(7'h13, 16'h0666); // BL2B
+    reg_write(7'h14, 16'h0000); // BL3A
+    reg_write(7'h15, 16'h0000); // BL3B
+
+    // Palette
+    //reg_write(7'h01, 16'h0000); // addr = 0
+    //reg_write(7'h02, 16'h0000); // ent[0]
+endtask
+
+task load_vdc0_reg();
+    io_sel = VDC0;
+    reg_write(7'h05, 16'h00c8); // CR
+    reg_write(7'h06, 16'h0000); // RCR
+    reg_write(7'h07, 16'h0000); // BXR
+    reg_write(7'h08, 16'h0000); // BYR
+    reg_write(7'h09, 16'h0050); // MWR
+    reg_write(7'h0a, 16'h0202); // HSR
+    reg_write(7'h0b, 16'h041f); // HDR
+    reg_write(7'h0c, 16'h1102); // VPR
+    reg_write(7'h0d, 16'h00ef); // VDR
+    reg_write(7'h0e, 16'h0002); // VCR
+    reg_write(7'h13, 16'h7f00); // DVSSR
+endtask
+
+task load_vdc1_reg();
+    io_sel = VDC1;
+    reg_write(7'h05, 16'h00c0); // CR
+    reg_write(7'h06, 16'h0000); // RCR
+    reg_write(7'h07, 16'h0000); // BXR
+    reg_write(7'h08, 16'hfff8); // BYR
+    reg_write(7'h09, 16'h0050); // MWR
+    reg_write(7'h0a, 16'h0202); // HSR
+    reg_write(7'h0b, 16'h041f); // HDR
+    reg_write(7'h0c, 16'h1102); // VPR
+    reg_write(7'h0d, 16'h00ef); // VDR
+    reg_write(7'h0e, 16'h0002); // VCR
+    reg_write(7'h13, 16'h7f00); // DVSSR
+endtask
+
+task load_kreg();
+    // KING BG
+    io_sel = MMC;
+    reg_write(7'h10, 16'h0005); // Mode
+    reg_write(7'h12, 16'h0004); // Prio
+    reg_write(7'h16, 16'h0001); // ScrM
+    // KBG0
+    reg_write(7'h2c, 16'h8888); // Size
+    reg_write(7'h20, 16'h0000); // BAT
+    reg_write(7'h21, 16'h0080); // CG
+    reg_write(7'h22, 16'h0000); // SubBAT
+    reg_write(7'h23, 16'h0080); // SubCG
+    reg_write(7'h30, 16'h0000); // XScr
+    reg_write(7'h31, 16'h0000); // YScr
+    // KBG1
+    reg_write(7'h2d, 16'h0000); // Size
+    reg_write(7'h24, 16'h0000); // BAT
+    reg_write(7'h25, 16'h0000); // CG
+    reg_write(7'h32, 16'h0000); // XScr
+    reg_write(7'h33, 16'h0000); // YScr
+    // KBG2
+    reg_write(7'h2e, 16'h0000); // Size
+    reg_write(7'h28, 16'h0000); // BAT
+    reg_write(7'h29, 16'h0000); // CG
+    reg_write(7'h34, 16'h0000); // XScr
+    reg_write(7'h35, 16'h0000); // YScr
+    // KBG3
+    reg_write(7'h2f, 16'h0000); // Size
+    reg_write(7'h2a, 16'h0000); // BAT
+    reg_write(7'h2b, 16'h0000); // CG
+    reg_write(7'h34, 16'h0000); // XScr
+    reg_write(7'h35, 16'h0000); // YScr
+    // AFFIN
+    reg_write(7'h38, 16'h0000); // A
+    reg_write(7'h39, 16'h0000); // B
+    reg_write(7'h3a, 16'h0000); // C
+    reg_write(7'h3b, 16'h0000); // D
+    reg_write(7'h3c, 16'h0000); // X
+    reg_write(7'h3d, 16'h0000); // Y
+    // MPROG
+    reg_write(7'h13, 16'h0000); // uAddr=0
+    reg_write(7'h14, 16'h0100); // 0
+    reg_write(7'h14, 16'h0100); // 1
+    reg_write(7'h14, 16'h0100); // 2
+    reg_write(7'h14, 16'h0100); // 3
+    reg_write(7'h14, 16'h0100); // 4
+    reg_write(7'h14, 16'h0100); // 5
+    reg_write(7'h14, 16'h0100); // 6
+    reg_write(7'h14, 16'h0100); // 7
+    reg_write(7'h14, 16'h0000); // 8
+    reg_write(7'h14, 16'h0001); // 9
+    reg_write(7'h14, 16'h0002); // A
+    reg_write(7'h14, 16'h0003); // B
+    reg_write(7'h14, 16'h0004); // C
+    reg_write(7'h14, 16'h0005); // D
+    reg_write(7'h14, 16'h0006); // E
+    reg_write(7'h14, 16'h0007); // F
+    reg_write(7'h15, 16'h0001); // MPSW=1
+endtask
+
+task load_vmem();
+    $readmemh("vram0-mainmenu.hex", vram0.mem);
+    $readmemh("vram1-mainmenu.hex", vram1.mem);
+    $readmemh("vce_cp-mainmenu.hex", vce.cpram.mem);
+    vram_load_file("kram0-mainmenu.bin", 0);
+    vram_load_file("kram1-mainmenu.bin", 1);
+endtask
+