mirror of
https://github.com/MiSTer-devel/PC88_MiSTer.git
synced 2026-04-19 03:04:48 +00:00
266 lines
7.9 KiB
VHDL
266 lines
7.9 KiB
VHDL
LIBRARY IEEE,WORK;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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USE WORK.addressmap_pkg.ALL;
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entity memorymaps is
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generic(
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extram :integer :=0;
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addrwidth :integer :=25
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);
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port(
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CPU_ADR :in std_logic_vector(15 downto 0);
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CPU_MREQn :in std_logic;
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CPU_IORQn :in std_logic;
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CPU_RDn :in std_logic;
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CPU_WRn :in std_logic;
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CPU_WDAT :in std_logic_vector(7 downto 0);
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CPU_RDAT :out std_logic_vector(7 downto 0);
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CPU_OE :out std_logic;
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KNJ1_ADR :in std_logic_vector(16 downto 0);
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KNJ1_RD :in std_logic;
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KNJ2_ADR :in std_logic_vector(16 downto 0);
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KNJ2_RD :in std_logic;
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RAM_ADR :out std_logic_vector(addrwidth-1 downto 0);
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RAM_CE :out std_logic;
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TRAM_ADR :out std_logic_vector(11 downto 0);
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TRAM_CE :out std_logic;
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TVRAM_ADR :out std_logic_vector(11 downto 0);
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TVRAM_CE :out std_logic;
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TXTWINEN :out std_logic;
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G_EXTMODE :out std_logic;
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G_RAMSEL :out integer range 0 to 3;
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ALUOE :out std_logic;
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ALUME :out std_logic;
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ALURE :out std_logic;
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GADR_MSEL :out std_logic;
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clk :in std_logic;
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rstn :in std_logic
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);
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end memorymaps;
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architecture MAIN of memorymaps is
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signal LOWSEL :std_logic_vector(1 downto 0);
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signal ROM4SEL :std_logic_vector(1 downto 0);
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signal VRAMSEL :std_logic_vector(1 downto 0);
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signal TXWADR :std_logic_vector(7 downto 0);
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signal RMODE :std_logic;
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signal MMODE :std_logic;
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signal IEROMn :std_logic;
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signal TMODE :std_logic;
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signal RAM_ADRF :std_logic_vector(27 downto 0);
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signal ADRSEL :integer range 0 to 4;
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constant ADR_ROM :integer :=0;
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constant ADR_RAM :integer :=1;
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constant ADR_VRAM :integer :=2;
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constant ADR_ERAM :integer :=3;
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constant ADR_TRAM :integer :=4;
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signal TXW_BASE :std_logic_vector(15 downto 0);
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signal TXW_OFFSET :std_logic_vector(15 downto 0);
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signal TXW_SUM :std_logic_vector(15 downto 0);
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signal TXW_SELV :std_logic;
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signal IO5c :std_logic_vector(7 downto 0);
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signal IO70 :std_logic_vector(7 downto 0);
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signal IO71 :std_logic_vector(7 downto 0);
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signal G_RAMSELb :integer range 0 to 3;
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signal GVAM :std_logic;
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signal GAM :std_logic;
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signal TRAMSEL :std_logic;
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signal TVRMODE :std_logic;
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signal IOWRn :std_logic;
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signal lWRn :std_logic;
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signal TXTWINENb :std_logic;
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signal extsel :std_logic_vector(3 downto 0);
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signal extwe :std_logic;
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signal extre :std_logic;
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begin
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IOWRn<=CPU_IORQn or CPU_WRn;
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process(clk,rstn)begin
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if(rstn='0')then
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RMODE<='0';
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MMODE<='0';
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IEROMn<='1';
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TMODE<='0';
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ROM4SEL<="00";
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TXWADR<=x"00";
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G_RAMSELb<=3;
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GVAM<='0';
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GAM<='0';
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extre<='0';
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extwe<='0';
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extsel<=(others=>'0');
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TVRMODE<='0';
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elsif(clk' event and clk='1')then
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if(IOWRn='0')then
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case CPU_ADR(7 downto 0) is
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when x"31" =>
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MMODE<=CPU_WDAT(1);
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RMODE<=CPU_WDAT(2);
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when x"32" =>
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ROM4SEL<=CPU_WDAT(1 downto 0);
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TMODE<=CPU_WDAT(4);
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GVAM<=CPU_WDAT(6);
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if(CPU_WDAT(6)='1')then
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G_RAMSELb<=3;
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end if;
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when x"35" =>
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GAM<=CPU_WDAT(7);
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when x"38"=>
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TVRMODE<=CPU_WDAT(0);
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when x"5c" =>
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G_RAMSELb<=0;
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when x"5d" =>
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G_RAMSELb<=1;
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when x"5e" =>
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G_RAMSELb<=2;
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when x"5f" =>
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G_RAMSELb<=3;
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when x"70" =>
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TXWADR<=CPU_WDAT;
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when x"71" =>
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IEROMn<=CPU_WDAT(0);
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when x"78" =>
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if(lWRn='1')then
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TXWADR<=TXWADR+1;
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end if;
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when x"e2" =>
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if(extram=0)then
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extre<='0';
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extwe<='0';
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else
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extre<=CPU_WDAT(0);
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extwe<=CPU_WDAT(4);
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end if;
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when x"e3" =>
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if(extram=0)then
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extsel<=(others=>'0');
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else
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extsel<=CPU_WDAT(3 downto 0);
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end if;
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when others=>
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end case;
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end if;
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lWRn<=IOWRn;
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end if;
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end process;
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G_EXTMODE<=GVAM;
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TXW_BASE<=TXWADR & x"00";
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TXW_OFFSET<=x"0" & "00" & CPU_ADR(9 downto 0);
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TXW_SUM<=TXW_BASE+TXW_OFFSET;
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TXW_SELV<='1' when TXW_SUM(15 downto 14)="11" else '0';
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IO70<=TXWADR;
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TXTWINENb<='1' when RMODE='0' and MMODE='0' and CPU_ADR(15 downto 10)="100000" else '0';
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TXTWINEN<=TXTWINENb;
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TRAMSEL<= '1' when GVAM='0' and G_RAMSELb=3 else
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'1' when GVAM='1' and GAM='0' else
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'0';
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RAM_ADRF<=
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ADDR_KANJI1(27 downto 17) & KNJ1_ADR when KNJ1_RD='1' else --Kanji1 ROM
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ADDR_KANJI2(27 downto 17) & KNJ2_ADR when KNJ2_RD='1' else --Kanji2 ROM
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ADDR_EXTRAM(27 downto 19) & extsel & CPU_ADR(14 downto 0) when extram/=0 and CPU_ADR(15)='0' and extre='1' and CPU_RDn='0' else --ext ram(read)
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ADDR_EXTRAM(27 downto 19) & extsel & CPU_ADR(14 downto 0) when extram/=0 and CPU_ADR(15)='0' and extwe='1' and CPU_WRn='0' else --ext ram(write)
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ADDR_BACKRAM(27 downto 15) & CPU_ADR(14 downto 0) when CPU_ADR(15)='0' and CPU_WRn='0' else --write ram when rom assigned
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ADDR_GVRAM(27 downto 15) & TXW_SUM(13 downto 0) & '0' when TXTWINENb='1' and TXW_SELV='1' else --text window(VRAM area)
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ADDR_MAINRAM(27 downto 16) & TXW_SUM when TXTWINENb='1' else --text window
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ADDR_N88_4_0(27 downto 15) & ROM4SEL & CPU_ADR(12 downto 0) when RMODE='0' and MMODE='0' and IEROMn='0' and CPU_ADR(15 downto 13)="011" else --4th ROM
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ADDR_N88(27 downto 16) & RMODE & CPU_ADR(14 downto 0) when CPU_ADR(15)='0' and MMODE='0' else --N88 or N80 BASIC
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ADDR_MAINRAM(27 downto 14) & CPU_ADR(13 downto 0) when CPU_ADR(15 downto 14)="10" else --MAIN RAM
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ADDR_GVRAM(27 downto 15) & CPU_ADR(13 downto 0) & '0' when CPU_ADR(15 downto 14)="11" else --VRAM
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ADDR_MAINRAM(27 downto 16) & CPU_ADR; --MAIN RAM
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ADRSEL<=
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ADR_TRAM when TRAMSEL='1' and TMODE='0' and CPU_ADR(15 downto 12)=x"F" else
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ADR_VRAM when CPU_ADR(15 downto 14)="11" else
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ADR_RAM when CPU_ADR(15)='0' and extre='1' and CPU_WRn='1' else
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ADR_ROM when MMODE='0' and CPU_ADR(15)='0' and CPU_WRn='1' else
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ADR_RAM;
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ALUOE<= '1' when CPU_MREQn='0' and CPU_RDn='0' and ADRSEL=ADR_VRAM and GVAM='1' and GAM='1' else '0';
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ALUME<= '1' when CPU_MREQn='0' and CPU_RDn='0' and ADRSEL=ADR_VRAM and GVAM='1' and GAM='0' else
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'1' when CPU_MREQn='0' and CPU_RDn='0' and ADRSEL=ADR_VRAM and GVAM='0' else --and G_RAMSELb=3 else
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'0';
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ALURE<= '1' when CPU_MREQn='0' and CPU_RDn='0' and ADRSEL=ADR_VRAM and GVAM='1' and GAM='1' else
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-- '1' when CPU_MREQn='0' and CPU_RDn='0' and ADRSEL=ADR_VRAM and GVAM='0' and G_RAMSELb/=3 else
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'0';
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GADR_MSEL<= '1' when CPU_MREQn='0' and ADRSEL=ADR_VRAM and GVAM='0' and G_RAMSELb=3 else
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'1' when CPU_MREQn='0' and ADRSEL=ADR_VRAM and GVAM='1' and GAM='0' else
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'0';
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RAM_CE <=not CPU_MREQn when ADRSEL=ADR_VRAM or ADRSEL=ADR_ROM or ADRSEL=ADR_RAM else '0';
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TRAM_CE <=not CPU_MREQn when ADRSEL=ADR_TRAM and TVRMODE='0' else '0';
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TVRAM_CE <=not CPU_MREQn when ADRSEL=ADR_TRAM and TVRMODE='1' else '0';
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RAM_ADR<=RAM_ADRF(addrwidth-1 downto 0);
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TRAM_ADR<=CPU_ADR(11 downto 0);
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TVRAM_ADR<=CPU_ADR(11 downto 0);
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G_RAMSEL<= 3 when (GVAM='1' and GAM='0') else
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3 when TXTWINENb='1' and TXW_SELV='1' else --TXTWINDOW
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G_RAMSELb;
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IO5c<= "00000001" when G_RAMSELb=0 else
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"00000010" when G_RAMSELb=1 else
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"00000100" when G_RAMSELb=2 else
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"00000000";
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IO71<= "1111111" & IEROMn;
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process(CPU_ADR,CPU_IORQn,CPU_RDn,IO5c,IO70,IO71,extwe,extre,extsel)begin
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if(CPU_IORQn='1' or CPU_RDn='1')then
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CPU_RDAT<=(others=>'1');
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CPU_OE<='0';
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else
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case CPU_ADR(7 downto 0) is
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when x"5c" =>
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CPU_RDAT<=IO5c;
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CPU_OE<='1';
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when x"70" =>
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CPU_RDAT<=IO70;
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CPU_OE<='1';
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when x"71" =>
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CPU_RDAT<=IO71;
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CPU_OE<='1';
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when x"e2" =>
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if(extram/=0)then
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CPU_RDAT<="111" & not extwe & "111" & not extre;
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CPU_OE<='1';
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else
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CPU_RDAT<=(others=>'1');
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end if;
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when x"e3" =>
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if(extram/=0)then
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CPU_RDAT<="0000" & extsel;
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CPU_OE<='1';
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else
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CPU_RDAT<=(others=>'1');
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end if;
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when others=>
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CPU_RDAT<=(others=>'1');
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CPU_OE<='0';
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end case;
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end if;
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end process;
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end MAIN;
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