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41 lines
937 B
VHDL
41 lines
937 B
VHDL
library ieee,work;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity susmult is
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generic(
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awidth :integer :=16;
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bwidth :integer :=16
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);
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port(
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ain :in std_logic_vector(awidth-1 downto 0);
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bin :in std_logic_vector(bwidth-1 downto 0);
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qout :out std_logic_vector(awidth+bwidth-1 downto 0);
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clk :in std_logic
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);
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end susmult;
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architecture rtl of susmult is
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signal bsig :std_logic_vector(bwidth downto 0);
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signal qsub :std_logic_vector(awidth+bwidth downto 0);
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component ssmult
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generic(
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awidth :integer :=16;
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bwidth :integer :=16
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);
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port(
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ain :in std_logic_vector(awidth-1 downto 0);
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bin :in std_logic_vector(bwidth-1 downto 0);
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qout :out std_logic_vector(awidth+bwidth-1 downto 0);
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clk :in std_logic
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);
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end component;
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begin
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bsig<='0' & bin;
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mul :ssmult generic map(awidth,bwidth+1)port map(ain,bsig,qsub,clk);
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qout<=qsub(awidth+bwidth-1 downto 0);
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end rtl;
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