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30 lines
588 B
VHDL
30 lines
588 B
VHDL
library ieee,work;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_signed.all;
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entity ssmult is
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generic(
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awidth :integer :=16;
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bwidth :integer :=16
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);
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port(
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ain :in std_logic_vector(awidth-1 downto 0);
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bin :in std_logic_vector(bwidth-1 downto 0);
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qout :out std_logic_vector(awidth+bwidth-1 downto 0);
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clk :in std_logic
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);
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end ssmult;
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architecture rtl of ssmult is
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signal qsub :std_logic_vector(awidth+bwidth-1 downto 0);
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begin
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qsub<=ain * bin;
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process(clk)begin
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if(clk' event and clk='1')then
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qout<=qsub;
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end if;
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end process;
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end rtl;
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