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116 lines
2.9 KiB
Verilog
116 lines
2.9 KiB
Verilog
// NeoGeo logic definition
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// Copyright (C) 2018 Sean Gonsalves
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// Rewrite to fully synchronous logic by (C) 2023 Gyorgy Szombathelyi
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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module linebuffer(
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//input TEST_MODE,
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//input [7:0] GBD,
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input CLK,
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input CK,
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input WE,
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input LOAD,
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input CLEARING,
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input [3:0] COLOR_INDEX,
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input PCK2_EN,
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input [7:0] SPR_PAL,
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input [7:0] ADDR_LOAD,
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output [11:0] DATA_OUT
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);
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// 192 pixels * 12 bits
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//reg [11:0] LB_RAM[0:255]; // TODO: Add a check, should never go over 191
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reg [7:0] PAL_REG;
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reg [7:0] ADDR_COUNTER;
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reg [7:0] ADDR_LATCH;
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wire [7:0] ADDR_MUX;
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wire [11:0] DATA_IN;
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wire [3:0] COLOR_GATED;
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// Switch between color index or backdrop clear
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// BL: NUDE NOSY...
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// BR: NEGA NACO...
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// TL: MOZA MAKO...
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// TR: NUDE NOSY...
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assign COLOR_GATED = COLOR_INDEX | {4{CLEARING}};
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// Select color index or test data (unused)
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// BL: NODO NUJA...
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// BR: NOFA NYKO...
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// TL: MAPE MUCA...
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// TR: LANO LODO...
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assign DATA_IN[3:0] = COLOR_GATED; // TEST_MODE ? GBD : COLOR_GATED;
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// Latch sprite palette from P bus
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// BL: MANA NAKA...
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// BR: MESY NEPA...
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// TL: JETU JUMA...
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// TR: GENA HARU...
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always @(posedge CLK)
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if (PCK2_EN) PAL_REG <= SPR_PAL;
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// Switch between sprite palette or backdrop clear
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// BL: MORA NOKU...
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// BR: MECY NUXA...
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// TL: JEZA JODE...
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// TR: GUSU HYKU...
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assign DATA_IN[11:4] = PAL_REG | {8{CLEARING}};
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// Switch between address inc or address reload
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// BL: RUFY QAZU...
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// BR: PECU QUNY...
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// TL: BAME CUNU...
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// TR: EGED DUGA...
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assign ADDR_MUX = LOAD ? (ADDR_COUNTER_REG + 1'b1) : ADDR_LOAD;
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// Address counter update
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// BL: REVA QEVU...
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// BR: PAJE QATA...
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// TL: BEWA CENA...
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// TR: EPAQ DAFU...
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reg CK_D;
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reg [7:0] ADDR_COUNTER_REG;
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always @(posedge CLK) begin
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CK_D <= CK;
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ADDR_COUNTER_REG <= ADDR_COUNTER;
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end
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always @(*) begin
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if (!CK_D & CK)
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ADDR_COUNTER = ADDR_MUX;
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else
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ADDR_COUNTER = ADDR_COUNTER_REG;
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end
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// always @(posedge CK)
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// ADDR_COUNTER <= ADDR_MUX;
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// Address counter latch
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// BL: NACY OKYS...
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// BR: PEXU QUVU...
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// TL: ERYV ENOG...
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// TR: EDYZ ASYX...
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reg [11:0] DATA_LATCH;
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always @(posedge CLK) if(WE) begin ADDR_LATCH <= ADDR_COUNTER; DATA_LATCH <= DATA_IN; end
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spram #(8,12) UR(
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.clock(CLK),
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.address(ADDR_LATCH),
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.data(DATA_LATCH),
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.wren(~WE),
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.q(DATA_OUT)
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);
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endmodule
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