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https://github.com/MiSTer-devel/NeoGeo_MiSTer.git
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90 lines
2.7 KiB
Verilog
90 lines
2.7 KiB
Verilog
// NeoGeo logic definition
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// Copyright (C) 2018 Sean Gonsalves
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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module syslatch(
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input [4:1] M68K_ADDR,
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input nBITW1,
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input nRESET,
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output SHADOW, nVEC, nCARDWEN, CARDWENB, nREGEN, nSYSTEM, nSRAMWEN, PALBNK,
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input CLK, CLK_EN_68K_P
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);
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reg [7:0] SLATCH;
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assign SHADOW = SLATCH[0];
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assign nVEC = SLATCH[1];
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assign nCARDWEN = SLATCH[2];
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assign CARDWENB = SLATCH[3];
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assign nREGEN = SLATCH[4];
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assign nSYSTEM = SLATCH[5];
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assign nSRAMWEN = ~SLATCH[6]; // See MVS schematics page 3
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assign PALBNK = SLATCH[7];
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// System latch
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/*always @(*) // M68K_ADDR[4:1] or nBITW1 or nRESET
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begin
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if (!nRESET)
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begin
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if (nBITW1)
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SLATCH <= 8'h00; // Clear
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else
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begin // Demux mode
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case (M68K_ADDR[3:1])
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0: SLATCH <= {7'b0000000, M68K_ADDR[4]};
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1: SLATCH <= {6'b000000, M68K_ADDR[4], 1'b0};
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2: SLATCH <= {5'b00000, M68K_ADDR[4], 2'b00};
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3: SLATCH <= {4'b0000, M68K_ADDR[4], 3'b000};
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4: SLATCH <= {3'b000, M68K_ADDR[4], 4'b0000};
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5: SLATCH <= {2'b00, M68K_ADDR[4], 5'b00000};
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6: SLATCH <= {1'b0, M68K_ADDR[4], 6'b000000};
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7: SLATCH <= {M68K_ADDR[4], 7'b0000000};
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endcase
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end
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end
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else if (!nBITW1)
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begin // Latch mode
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SLATCH[M68K_ADDR[3:1]] <= M68K_ADDR[4];
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end
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end*/
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always @(posedge CLK) // M68K_ADDR[4:1] or nBITW1 or nRESET
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if (CLK_EN_68K_P) begin
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if (!nRESET)
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begin
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if (nBITW1)
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SLATCH <= 8'h00; // Clear
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else
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begin // Demux mode
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case (M68K_ADDR[3:1])
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0: SLATCH <= {7'b0000000, M68K_ADDR[4]};
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1: SLATCH <= {6'b000000, M68K_ADDR[4], 1'b0};
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2: SLATCH <= {5'b00000, M68K_ADDR[4], 2'b00};
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3: SLATCH <= {4'b0000, M68K_ADDR[4], 3'b000};
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4: SLATCH <= {3'b000, M68K_ADDR[4], 4'b0000};
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5: SLATCH <= {2'b00, M68K_ADDR[4], 5'b00000};
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6: SLATCH <= {1'b0, M68K_ADDR[4], 6'b000000};
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7: SLATCH <= {M68K_ADDR[4], 7'b0000000};
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endcase
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end
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end
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else if (!nBITW1)
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begin // Latch mode
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SLATCH[M68K_ADDR[3:1]] <= M68K_ADDR[4];
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end
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end
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endmodule
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