paulb-nl ecf677a1d9 Reset fixes for DDRAM & T80pa (#253) ...

There were some issues exposed with the previous reset changes.

DDRAM: set cache invalid during reset to prevent wrong data at first
read

T80pa: IntCycleD_n was not set during reset which caused the first
read cycle to assert both MREQ and IORQ. This resulted in reading the
wrong data.

2026-05-16 06:25:17 +08:00

..

T80_ALU.vhd

Fix async clocks and latches (based on gyurco's changes).

2023-07-24 03:07:53 +08:00

T80_MCode.vhd

Fix async clocks and latches (based on gyurco's changes).

2023-07-24 03:07:53 +08:00

T80_Pack.vhd

Fix async clocks and latches (based on gyurco's changes).

2023-07-24 03:07:53 +08:00

T80_Reg.vhd

Update sys. Re-organize the sources.

2020-05-11 00:10:59 +08:00

T80.qip

Minor update in T80.

2020-08-20 17:48:49 +08:00

T80.vhd

Fix async clocks and latches (based on gyurco's changes).

2023-07-24 03:07:53 +08:00

T80pa.vhd

Reset fixes for DDRAM & T80pa (#253)

2026-05-16 06:25:17 +08:00

T80s.vhd

Minor update in T80.

2020-08-20 17:48:49 +08:00