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18 lines
562 B
Verilog
18 lines
562 B
Verilog
// Copyright (c) 2012-2013 Ludvig Strigeus
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// This program is GPL Licensed. See COPYING for the full license.
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module MUXCY(output O, input CI, input DI, input S);
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assign O = S ? CI : DI;
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endmodule
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module MUXCY_L(output LO, input CI, input DI, input S);
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assign LO = S ? CI : DI;
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endmodule
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module MUXCY_D(output LO, output O, input CI, input DI, input S);
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assign LO = S ? CI : DI;
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assign O = LO;
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endmodule
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module XORCY(output O, input CI, input LI);
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assign O = CI ^ LI;
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endmodule
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module XOR2(output O, input I0, input I1);
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assign O = I0 ^ I1;
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endmodule |