From f0ef237a82bf8bc2a2d431f4bc70955044dca20f Mon Sep 17 00:00:00 2001 From: sorgelig Date: Sun, 23 Dec 2018 19:24:21 +0800 Subject: [PATCH] Update sys. --- NES.qsf | 2 +- sys/lpf48k.sv | 4 ++-- sys/reset_source.v | 50 ++++++++++++++++++++++++++++++++++++++++++++++ sys/sys.qip | 3 ++- sys/sys_q13.qip | 3 ++- sys/sys_top.sdc | 12 +++++------ sys/sys_top.v | 10 +++++----- 7 files changed, 68 insertions(+), 16 deletions(-) create mode 100644 sys/reset_source.v diff --git a/NES.qsf b/NES.qsf index a7b8787..d8a3e6c 100644 --- a/NES.qsf +++ b/NES.qsf @@ -29,7 +29,7 @@ set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CSEBA6U23I7 set_global_assignment -name TOP_LEVEL_ENTITY sys_top set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 -set_global_assignment -name LAST_QUARTUS_VERSION "17.0.1 Standard Edition" +set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Standard Edition" set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 diff --git a/sys/lpf48k.sv b/sys/lpf48k.sv index 2a32981..e6bab53 100644 --- a/sys/lpf48k.sv +++ b/sys/lpf48k.sv @@ -76,7 +76,7 @@ always @(posedge RESET or posedge CLK) begin end end -assign W_DATA = LPF_TAP_DATA[FF_ADDR] * IDATA; +assign W_DATA = LPF_TAP_DATA[FF_ADDR] * $signed(IDATA); always @(posedge RESET or posedge CLK) begin if (RESET) FF_INTEG <= 0; @@ -84,7 +84,7 @@ always @(posedge RESET or posedge CLK) begin begin if (CE) begin if (W_ADDR_END) FF_INTEG <= 0; - else FF_INTEG <= FF_INTEG + W_DATA; + else FF_INTEG <= $signed(FF_INTEG) + $signed(W_DATA); end end end diff --git a/sys/reset_source.v b/sys/reset_source.v new file mode 100644 index 0000000..1b81394 --- /dev/null +++ b/sys/reset_source.v @@ -0,0 +1,50 @@ +// reset_source.v + +// This file was auto-generated as a prototype implementation of a module +// created in component editor. It ties off all outputs to ground and +// ignores all inputs. It needs to be edited to make it do something +// useful. +// +// This file will not be automatically regenerated. You should check it in +// to your version control system if you want to keep it. + +`timescale 1 ps / 1 ps +module reset_source +( + input wire clk, // clock.clk + input wire reset_hps, // reset_hps.reset + output wire reset_sys, // reset_sys.reset + output wire reset_cold, // reset_cold.reset + input wire cold_req, // reset_ctl.cold_req + output wire reset, // .reset + input wire reset_req, // .reset_req + input wire reset_vip, // .reset_vip + input wire warm_req, // .warm_req + output wire reset_warm // reset_warm.reset +); + +assign reset_cold = cold_req; +assign reset_warm = warm_req; + +wire reset_m = sys_reset | reset_hps | reset_req; +assign reset = reset_m; +assign reset_sys = reset_m | reset_vip; + +reg sys_reset = 1; +always @(posedge clk) begin + integer timeout = 0; + reg reset_lock = 0; + + reset_lock <= reset_lock | cold_req; + + if(timeout < 2000000) begin + sys_reset <= 1; + timeout <= timeout + 1; + reset_lock <= 0; + end + else begin + sys_reset <= reset_lock; + end +end + +endmodule diff --git a/sys/sys.qip b/sys/sys.qip index ecb75c1..3dd4831 100644 --- a/sys/sys.qip +++ b/sys/sys.qip @@ -18,7 +18,8 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) s set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) lpf48k.sv ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ip/reset_source.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) reset_source.v ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vip_config.sv ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ] +set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sysmem_HPS_fpga_interfaces -to peripheral_uart1 diff --git a/sys/sys_q13.qip b/sys/sys_q13.qip index 9303f21..c765279 100644 --- a/sys/sys_q13.qip +++ b/sys/sys_q13.qip @@ -22,7 +22,8 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) s set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) lpf48k.sv ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) ip/reset_source.v ] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) reset_source.v ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vip_config.sv ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ] +set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sysmem_HPS_fpga_interfaces -to peripheral_uart1 diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc index 8d7a795..3ff1e17 100644 --- a/sys/sys_top.sdc +++ b/sys/sys_top.sdc @@ -7,7 +7,7 @@ create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk] derive_pll_clocks # Specify PLL-generated clock(s) -#create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \ +create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -name SDRAM_CLK [get_ports {SDRAM_CLK}] create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \ @@ -21,15 +21,15 @@ derive_clock_uncertainty # Set acceptable delays for SDRAM chip (See correspondent chip datasheet) -#set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]] -#set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]] +set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]] +set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]] -#set_multicycle_path -from [get_clocks {SDRAM_CLK}] \ +set_multicycle_path -from [get_clocks {SDRAM_CLK}] \ -to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -setup 2 -#set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] -#set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] # Decouple different clock groups (to simplify routing) set_clock_groups -asynchronous \ diff --git a/sys/sys_top.v b/sys/sys_top.v index feef53c..be27d8d 100644 --- a/sys/sys_top.v +++ b/sys/sys_top.v @@ -529,8 +529,8 @@ ascal .i_r (r_out), .i_g (g_out), .i_b (b_out), - .i_hs (hs_emu), - .i_vs (vs_emu), + .i_hs (hs), + .i_vs (vs), .i_fl (f1), .i_de (de), .iauto (1), @@ -560,7 +560,7 @@ ascal .vmin (vmin), .vmax (vmax), - .mode ({1'b1,scaler_flt ? 3'd4 : 3'd0}), + .mode ({1'b1,scaler_flt ? 3'd6 : 3'd0}), .poly_clk (clk_sys), .poly_a (coef_addr), .poly_dw (coef_data), @@ -901,8 +901,8 @@ wire [1:0] led_power; wire [1:0] led_disk; wire vs_emu, hs_emu; -sync_fix sync_v(FPGA_CLK3_50, vs_emu, vs); -sync_fix sync_h(FPGA_CLK3_50, hs_emu, hs); +sync_fix sync_v(clk_vid, vs_emu, vs); +sync_fix sync_h(clk_vid, hs_emu, hs); wire uart_dtr; wire uart_dsr;