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https://github.com/MiSTer-devel/MultiComp_MiSTer.git
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1dae91a05e
- update README.md OSD and BASIC sections - fix horizontal offset too far left in VGA mode
653 lines
18 KiB
Systemverilog
653 lines
18 KiB
Systemverilog
//============================================================================
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// Grant’s multi computer
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//
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// Port to MiSTer.
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//
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// Based on Grant’s multi computer
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// http://searle.hostei.com/grant/
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// http://searle.hostei.com/grant/Multicomp/index.html
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// and WiSo's collector blog (MiST port)
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// https://ws0.org/building-your-own-custom-computer-with-the-mist-fpga-board-part-1/
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// https://ws0.org/building-your-own-custom-computer-with-the-mist-fpga-board-part-2/
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [45:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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output [7:0] VIDEO_ARX,
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output [7:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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/*
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// Use framebuffer from DDRAM (USE_FB=1 in qsf)
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// FB_FORMAT:
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// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
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// [3] : 0=16bits 565 1=16bits 1555
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// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
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//
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// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of 16 bytes.
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output FB_EN,
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output [4:0] FB_FORMAT,
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output [11:0] FB_WIDTH,
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output [11:0] FB_HEIGHT,
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output [31:0] FB_BASE,
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output [13:0] FB_STRIDE,
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input FB_VBL,
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input FB_LL,
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output FB_FORCE_BLANK,
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// Palette control for 8bit modes.
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// Ignored for other video modes.
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output FB_PAL_CLK,
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output [7:0] FB_PAL_ADDR,
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output [23:0] FB_PAL_DOUT,
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input [23:0] FB_PAL_DIN,
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output FB_PAL_WR,
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*/
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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// I/O board button press simulation (active high)
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// b[1]: user button
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// b[0]: osd button
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output [1:0] BUTTONS,
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input CLK_AUDIO, // 24.576 MHz
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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//ADC
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inout [3:0] ADC_BUS,
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//SD-SPI SECONDARY SDCARD
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - RTS,CTS,DTR,DSR,IO6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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);
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// User Port - extra USB 3.1A style connector on MiSTer
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//
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// USB P7 Name PIN Mister emu wire
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// 1 +5V +5V
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// 2 2 TX SDA AH9 USER_IO[1]
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// 3 1 RX SCL AG11 USER_IO[0]
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// 4 GND GND
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// 5 8 DSR IO10 AF15 USER_IO[5]
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// 6 7 DTR IO11 AG16 USER_IO[4]
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// 7 6 CTS IO12 AH11 USER_IO[3]
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// 8 5 RTS IO13 AH12 USER_IO[2]
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// 9 10 IO6 IO8 AF17 USER_IO[6]
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// FT232 USB to serial cable
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// sig usb io connector
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// Red 5V
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// Black GND GND
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// White RXD 2
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// Green TXD 3
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// Yellow RTS 7
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// Blue CTS 8
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// Define meaningful names for USER_IO signals
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// Input pins (USER_IN)
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wire user_rx = USER_IN[0]; // Serial RX from USER_IO port
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wire user_cts = USER_IN[3]; // CTS from USER_IO port
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// USER_IN[1] unused
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// USER_IN[2] unused
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// USER_IN[4:6] unused
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// Output pins (USER_OUT)
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// Active high enables for input pins
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wire user_rx_en = USER_OUT[0]; // Enable RX input
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wire user_tx = USER_OUT[1]; // Serial TX to USER_IO port
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wire user_rts = USER_OUT[2]; // RTS to USER_IO port
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wire user_cts_en = USER_OUT[3]; // Enable CTS input
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// USER_OUT[4:6] unused
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assign ADC_BUS = 'Z;
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//assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
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assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
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//assign UART_RTS = UART_CTS;
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assign UART_DTR = UART_DSR;
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assign LED_POWER = 0;
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assign BUTTONS = 0;
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assign VIDEO_ARX = 4;
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assign VIDEO_ARY = 3;
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assign VGA_SL = 0;
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assign VGA_F1 = 0;
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assign VGA_SCALER = 1;
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assign AUDIO_S = 0;
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assign AUDIO_L = 0;
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assign AUDIO_R = 0;
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assign AUDIO_MIX = 0;
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`include "build_id.v"
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localparam CONF_STR = {
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"MultiComp;;",
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"S,IMG;",
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"OF,Reset after Mount,No,Yes;",
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"-;",
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"O78,CPU-ROM,Z80-CP/M,Z80-BASIC,6502-Basic,6809-Basic;",
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"-;",
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"O9B,Baud Rate tty,115200,38400,19200,9600,4800,2400;",
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"OC,Serial Port,Console Port,User IO Port;",
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"OE,Flow Control,None,RTS/CTS;", // New flow control option
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"OD,Storage Controller,SD Controller,Image Controller;",
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"-;",
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"RE,Reset;",
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"V,v",`BUILD_DATE
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};
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////////////////// HPS I/O ///////////////////
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wire [1:0] buttons;
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wire [31:0] status;
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wire PS2_CLK;
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wire PS2_DAT;
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wire forced_scandoubler;
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wire [31:0] sd_lba;
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wire sd_rd;
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wire sd_wr;
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wire sd_ack;
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wire [8:0] sd_buff_addr;
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wire [7:0] sd_buff_dout;
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wire [7:0] sd_buff_din;
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wire sd_buff_wr;
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wire sd_ack_conf;
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wire img_mounted;
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wire img_readonly;
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wire [63:0] img_size;
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hps_io #(
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.STRLEN($size(CONF_STR)>>3),
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.PS2DIV (2000)
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) hps_io
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(
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.clk_sys(CLK_50M),
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.HPS_BUS(HPS_BUS),
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.conf_str(CONF_STR),
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.buttons(buttons),
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.status(status),
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.forced_scandoubler(forced_scandoubler),
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.ps2_kbd_clk_out(PS2_CLK),
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.ps2_kbd_data_out(PS2_DAT),
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.sd_lba(sd_lba),
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.sd_rd(sd_rd),
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.sd_wr(sd_wr),
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.sd_ack(sd_ack),
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.sd_ack_conf(sd_ack_conf),
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.sd_buff_addr(sd_buff_addr),
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.sd_buff_dout(sd_buff_dout),
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.sd_buff_din(sd_buff_din),
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.sd_buff_wr(sd_buff_wr),
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.img_mounted(img_mounted),
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.img_readonly(img_readonly),
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.img_size(img_size),
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.uart_mode(16'b000_11111_000_11111)
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);
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/////////////////////// CLOCKS ///////////////////////////////
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wire clk_sys, locked;
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pll pll
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(
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.refclk(CLK_50M),
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.rst(0),
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.outclk_0(clk_sys),
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.locked(locked)
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);
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///////////////// RESET /////////////////////////
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wire reset = RESET | status[0] | buttons[1] | (status[15] && img_mounted);
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///////////////// SDCARD ////////////////////////
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// SD card interface signal declarations
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// _sd suffix for SD controller signals
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// _img suffix for image controller signals
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// _mux suffix for multiplexed signals
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wire sdclk_sd, sdmosi_sd, sdcs_sd; // SD controller outputs
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wire sdclk_img, sdmosi_img, sdcs_img; // Image controller outputs
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wire driveLED_sd, driveLED_img; // Drive activity indicators
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// Multiplexed signals that route to physical SD interface
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wire sdclk_mux, sdmosi_mux, sdcs_mux; // Multiplexed control signals
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wire sdmiso_mux; // Multiplexed data input
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wire driveLED_mux; // Multiplexed activity indicator
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// Controller selection - determines which controller drives SD interface
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wire storage_ctrl_select = status[13]; // 0=SD controller, 1=image controller
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// Multiplex between SD and image controller outputs
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assign sdclk_mux = storage_ctrl_select ? sdclk_img : sdclk_sd; // Clock output
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assign sdmosi_mux = storage_ctrl_select ? sdmosi_img : sdmosi_sd; // Data output to SD
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assign sdcs_mux = storage_ctrl_select ? sdcs_img : sdcs_sd; // Chip select
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assign driveLED_mux = storage_ctrl_select ? driveLED_img : driveLED_sd; // Activity LED
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// MISO input routing - selects between SD card and virtual SD based on vsd_sel
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assign sdmiso_mux = vsd_sel ? vsdmiso : SD_MISO;
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// Virtual SD interface enable
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reg vsd_sel = 0;
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always @(posedge clk_sys) if(img_mounted) vsd_sel <= |img_size;
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// Map multiplexed signals to physical SD interface
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// Keep physical SD enabled when using SD controller
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assign SD_SCK = (vsd_sel || !storage_ctrl_select) ? sdclk_mux : 1'bZ;
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assign SD_MOSI = (vsd_sel || !storage_ctrl_select) ? sdmosi_mux : 1'bZ;
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assign SD_CS = (vsd_sel || !storage_ctrl_select) ? sdcs_mux : 1'bZ;
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// Serial port selection
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wire serial_port_select = status[12]; // 0 = Console Port (UART), 1 = User IO Port
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// Flow control enable
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wire flow_control_enable = status[14]; // 0 = No flow control, 1 = RTS/CTS enabled
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// Serial interface routing
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wire serial_rx = serial_port_select ? user_rx : UART_RXD;
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wire serial_tx;
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localparam INIT_TIMEOUT = 24'd50000; // 1ms at 50MHz clock
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reg [23:0] init_counter = 0;
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reg init_complete = 0;
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always @(posedge clk_sys) begin
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if (reset) begin
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init_complete <= 0;
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init_counter <= 0;
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end
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else if (!init_complete) begin
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if (init_counter == INIT_TIMEOUT) begin
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init_complete <= 1;
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end
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else begin
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init_counter <= init_counter + 1;
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end
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end
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end
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// CTS handling - active low when flow control enabled
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wire serial_cts = flow_control_enable ?
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(init_complete ? (serial_port_select ? user_cts : UART_CTS) : 1'b0) :
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1'b0;
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// Serial interface output routing
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wire serial_rts; // RTS signal from CPUs
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// Serial port output routing
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assign UART_TXD = serial_port_select ? 1'b1 : serial_tx;
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assign UART_RTS = (serial_port_select || !flow_control_enable) ? 1'b1 : serial_rts;
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// USER_IO port control - single assignment for all outputs
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assign USER_OUT = {
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3'b0, // [6:4] unused
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serial_port_select && flow_control_enable, // [3] CTS input enable
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(serial_port_select && flow_control_enable) ? serial_rts : 1'b1, // [2] RTS output
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serial_port_select ? serial_tx : 1'b1, // [1] TX output
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serial_port_select // [0] RX input enable
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};
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// Connect the read-only signals to the USER_OUT bits for monitoring
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assign user_rx_en = USER_OUT[0];
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assign user_tx = USER_OUT[1];
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assign user_rts = USER_OUT[2];
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assign user_cts_en = USER_OUT[3];
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// Virtual SD card implementation
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sd_card sd_card
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(
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.*,
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.clk_spi(clk_sys),
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.sdhc(1),
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.sck(sdclk_mux),
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.ss(sdcs_mux | ~vsd_sel),
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.mosi(sdmosi_mux),
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.miso(vsdmiso)
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);
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// Drive activity detection
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reg sd_act;
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always @(posedge clk_sys) begin
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reg old_mosi, old_miso;
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integer timeout = 0;
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old_mosi <= sdmosi_mux;
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old_miso <= sdmiso_mux;
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sd_act <= 0;
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if(timeout < 1000000) begin
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timeout <= timeout + 1;
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sd_act <= 1;
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end
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if((old_mosi ^ sdmosi_mux) || (old_miso ^ sdmiso_mux)) timeout <= 0;
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end
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// Map drive LED to system LED output
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assign LED_USER = vsd_sel & sd_act;
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assign LED_DISK = {2{~driveLED_mux}};
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///////////////////////////////////////////////////
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assign CLK_VIDEO = clk_sys;
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typedef enum {cpuZ80CPM='b00, cpuZ80Basic='b01, cpu6502Basic='b10, cpu6809Basic='b11} cpu_type_enum;
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wire [1:0] cpu_type = status[8:7];
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typedef enum {baud115200='b000, baud38400='b001, baud19200='b010, baud9600='b011, baud4800='b100, baud2400='b101} baud_rate_enum;
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wire [2:0] baud_rate = status[11:9];
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wire hblank, vblank;
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wire hs, vs;
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wire [1:0] r,g,b;
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wire [3:0] _hblank, _vblank;
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wire [3:0] _hs, _vs;
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wire [1:0] _r[3:0], _g[3:0], _b[3:0];
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wire [3:0] _CE_PIXEL;
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wire [3:0] _txd;
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wire [3:0] _rts; // RTS signals from CPUs
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// Define signal arrays for each microcomputer's SD interface
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wire [3:0] sdcs_ctrl; // SD chip select signals from controllers
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wire [3:0] sdmosi_ctrl; // SD MOSI signals from controllers
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wire [3:0] sdclk_ctrl; // SD clock signals from controllers
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wire [3:0] driveLED_ctrl; // Drive LED signals from controllers
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// Add baud rate selection logic
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reg [15:0] baud_increment;
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always @(*) begin
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case(baud_rate)
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baud115200: baud_increment = 16'd2416; // 115200
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baud38400: baud_increment = 16'd805; // 38400
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baud19200: baud_increment = 16'd403; // 19200
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baud9600: baud_increment = 16'd201; // 9600
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baud4800: baud_increment = 16'd101; // 4800
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baud2400: baud_increment = 16'd50; // 2400
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default: baud_increment = 16'd2416; // Default to 115200
|
||
endcase
|
||
end
|
||
|
||
always_comb
|
||
begin
|
||
hblank <= _hblank[cpu_type];
|
||
vblank <= _vblank[cpu_type];
|
||
hs <= _hs[cpu_type];
|
||
vs <= _vs[cpu_type];
|
||
r <= _r[cpu_type][1:0];
|
||
g <= _g[cpu_type][1:0];
|
||
b <= _b[cpu_type][1:0];
|
||
CE_PIXEL <= _CE_PIXEL[cpu_type];
|
||
serial_tx <= _txd[cpu_type];
|
||
serial_rts <= _rts[cpu_type];
|
||
|
||
// Override based on selected CPU
|
||
case(cpu_type)
|
||
cpuZ80CPM: begin
|
||
sdcs_sd = sdcs_ctrl[cpuZ80CPM];
|
||
sdmosi_sd = sdmosi_ctrl[cpuZ80CPM];
|
||
sdclk_sd = sdclk_ctrl[cpuZ80CPM];
|
||
driveLED_sd = driveLED_ctrl[cpuZ80CPM];
|
||
end
|
||
cpuZ80Basic: begin
|
||
sdcs_sd = sdcs_ctrl[cpuZ80Basic];
|
||
sdmosi_sd = sdmosi_ctrl[cpuZ80Basic];
|
||
sdclk_sd = sdclk_ctrl[cpuZ80Basic];
|
||
driveLED_sd = driveLED_ctrl[cpuZ80Basic];
|
||
end
|
||
cpu6502Basic: begin
|
||
sdcs_sd = sdcs_ctrl[cpu6502Basic];
|
||
sdmosi_sd = sdmosi_ctrl[cpu6502Basic];
|
||
sdclk_sd = sdclk_ctrl[cpu6502Basic];
|
||
driveLED_sd = driveLED_ctrl[cpu6502Basic];
|
||
end
|
||
cpu6809Basic: begin
|
||
sdcs_sd = sdcs_ctrl[cpu6809Basic];
|
||
sdmosi_sd = sdmosi_ctrl[cpu6809Basic];
|
||
sdclk_sd = sdclk_ctrl[cpu6809Basic];
|
||
driveLED_sd = driveLED_ctrl[cpu6809Basic];
|
||
end
|
||
endcase
|
||
end
|
||
|
||
MicrocomputerZ80CPM MicrocomputerZ80CPM
|
||
(
|
||
.N_RESET(~reset & cpu_type == cpuZ80CPM),
|
||
.clk(cpu_type == cpuZ80CPM ? clk_sys : 0),
|
||
.baud_increment(baud_increment),
|
||
.R(_r[cpuZ80CPM][1:0]),
|
||
.G(_g[cpuZ80CPM][1:0]),
|
||
.B(_b[cpuZ80CPM][1:0]),
|
||
.HS(_hs[cpuZ80CPM]),
|
||
.VS(_vs[cpuZ80CPM]),
|
||
.hBlank(_hblank[cpuZ80CPM]),
|
||
.vBlank(_vblank[cpuZ80CPM]),
|
||
.cepix(_CE_PIXEL[cpuZ80CPM]),
|
||
.ps2Clk(PS2_CLK),
|
||
.ps2Data(PS2_DAT),
|
||
.sdCS(sdcs_ctrl[cpuZ80CPM]),
|
||
.sdMOSI(sdmosi_ctrl[cpuZ80CPM]),
|
||
.sdMISO(sdmiso_mux),
|
||
.sdSCLK(sdclk_ctrl[cpuZ80CPM]),
|
||
.driveLED(driveLED_ctrl[cpuZ80CPM]),
|
||
.sd_ctrl_sel(storage_ctrl_select),
|
||
.rxd1(serial_rx),
|
||
.txd1(_txd[cpuZ80CPM]),
|
||
.rts1(_rts[cpuZ80CPM]),
|
||
.cts1(serial_cts)
|
||
);
|
||
|
||
MicrocomputerZ80Basic MicrocomputerZ80Basic
|
||
(
|
||
.N_RESET(~reset & cpu_type == cpuZ80Basic),
|
||
.clk(cpu_type == cpuZ80Basic ? clk_sys : 0),
|
||
.baud_increment(baud_increment),
|
||
.R(_r[cpuZ80Basic][1:0]),
|
||
.G(_g[cpuZ80Basic][1:0]),
|
||
.B(_b[cpuZ80Basic][1:0]),
|
||
.HS(_hs[cpuZ80Basic]),
|
||
.VS(_vs[cpuZ80Basic]),
|
||
.hBlank(_hblank[cpuZ80Basic]),
|
||
.vBlank(_vblank[cpuZ80Basic]),
|
||
.cepix(_CE_PIXEL[cpuZ80Basic]),
|
||
.ps2Clk(PS2_CLK),
|
||
.ps2Data(PS2_DAT),
|
||
.sdCS(sdcs_ctrl[cpuZ80Basic]),
|
||
.sdMOSI(sdmosi_ctrl[cpuZ80Basic]),
|
||
.sdMISO(sdmiso_mux),
|
||
.sdSCLK(sdclk_ctrl[cpuZ80Basic]),
|
||
.driveLED(driveLED_ctrl[cpuZ80Basic]),
|
||
.sd_ctrl_sel(storage_ctrl_select),
|
||
.rxd1(serial_rx),
|
||
.txd1(_txd[cpuZ80Basic]),
|
||
.rts1(_rts[cpuZ80Basic]),
|
||
.cts1(serial_cts)
|
||
);
|
||
|
||
Microcomputer6502Basic Microcomputer6502Basic
|
||
(
|
||
.N_RESET(~reset & cpu_type == cpu6502Basic),
|
||
.clk(cpu_type == cpu6502Basic ? clk_sys : 0),
|
||
.baud_increment(baud_increment),
|
||
.R(_r[cpu6502Basic][1:0]),
|
||
.G(_g[cpu6502Basic][1:0]),
|
||
.B(_b[cpu6502Basic][1:0]),
|
||
.HS(_hs[cpu6502Basic]),
|
||
.VS(_vs[cpu6502Basic]),
|
||
.hBlank(_hblank[cpu6502Basic]),
|
||
.vBlank(_vblank[cpu6502Basic]),
|
||
.cepix(_CE_PIXEL[cpu6502Basic]),
|
||
.ps2Clk(PS2_CLK),
|
||
.ps2Data(PS2_DAT),
|
||
.sdCS(sdcs_ctrl[cpu6502Basic]),
|
||
.sdMOSI(sdmosi_ctrl[cpu6502Basic]),
|
||
.sdMISO(sdmiso_mux),
|
||
.sdSCLK(sdclk_ctrl[cpu6502Basic]),
|
||
.driveLED(driveLED_ctrl[cpu6502Basic]),
|
||
.sd_ctrl_sel(storage_ctrl_select),
|
||
.rxd1(serial_rx),
|
||
.txd1(_txd[cpu6502Basic]),
|
||
.rts1(_rts[cpu6502Basic]),
|
||
.cts1(serial_cts)
|
||
);
|
||
|
||
//Reset is not working (even on the original Grant's 6809)
|
||
Microcomputer6809Basic Microcomputer6809Basic
|
||
(
|
||
.N_RESET(~reset & cpu_type == cpu6809Basic),
|
||
.clk(cpu_type == cpu6809Basic ? clk_sys : 0),
|
||
.baud_increment(baud_increment),
|
||
.R(_r[cpu6809Basic][1:0]),
|
||
.G(_g[cpu6809Basic][1:0]),
|
||
.B(_b[cpu6809Basic][1:0]),
|
||
.HS(_hs[cpu6809Basic]),
|
||
.VS(_vs[cpu6809Basic]),
|
||
.hBlank(_hblank[cpu6809Basic]),
|
||
.vBlank(_vblank[cpu6809Basic]),
|
||
.cepix(_CE_PIXEL[cpu6809Basic]),
|
||
.ps2Clk(PS2_CLK),
|
||
.ps2Data(PS2_DAT),
|
||
.sdCS(sdcs_ctrl[cpu6809Basic]),
|
||
.sdMOSI(sdmosi_ctrl[cpu6809Basic]),
|
||
.sdMISO(sdmiso_mux),
|
||
.sdSCLK(sdclk_ctrl[cpu6809Basic]),
|
||
.driveLED(driveLED_ctrl[cpu6809Basic]),
|
||
.sd_ctrl_sel(storage_ctrl_select),
|
||
.rxd1(serial_rx),
|
||
.txd1(_txd[cpu6809Basic]),
|
||
.rts1(_rts[cpu6809Basic]),
|
||
.cts1(serial_cts)
|
||
);
|
||
|
||
video_cleaner video_cleaner
|
||
(
|
||
.clk_vid(CLK_VIDEO),
|
||
.ce_pix(CE_PIXEL),
|
||
|
||
.R({4{r}}),
|
||
.G({4{g}}),
|
||
.B({4{b}}),
|
||
.HSync(hs),
|
||
.VSync(vs),
|
||
.HBlank(hblank),
|
||
.VBlank(vblank),
|
||
|
||
.VGA_R(VGA_R),
|
||
.VGA_G(VGA_G),
|
||
.VGA_B(VGA_B),
|
||
.VGA_VS(VGA_VS),
|
||
.VGA_HS(VGA_HS),
|
||
.VGA_DE(VGA_DE)
|
||
);
|
||
|
||
|
||
endmodule
|