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https://github.com/MiSTer-devel/MultiComp_MiSTer.git
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301 lines
8.0 KiB
VHDL
301 lines
8.0 KiB
VHDL
-- This file is copyright by Grant Searle 2014
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-- You are free to use this file in your own projects but must never charge for it nor use it without
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-- acknowledgement.
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-- Please ask permission from Grant Searle before republishing elsewhere.
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-- If you use this file or any part of it, please add an acknowledgement to myself and
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-- a link back to my main web site http://searle.hostei.com/grant/
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-- and to the "multicomp" page at http://searle.hostei.com/grant/Multicomp/index.html
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--
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-- Please check on the above web pages to see if there are any updates before using this file.
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-- If for some reason the page is no longer available, please search for "Grant Searle"
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-- on the internet to see if I have moved to another web hosting service.
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--
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-- Grant Searle
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-- eMail address available on my main web page link above.
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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entity MicrocomputerZ80Basic is
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port(
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N_RESET : in std_logic;
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clk : in std_logic;
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sramData : inout std_logic_vector(7 downto 0);
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sramAddress : out std_logic_vector(15 downto 0);
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n_sRamWE : out std_logic;
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n_sRamCS : out std_logic;
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n_sRamOE : out std_logic;
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n_sRamLB : out std_logic;
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n_sRamUB : out std_logic;
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rxd1 : in std_logic;
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txd1 : out std_logic;
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rts1 : out std_logic;
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rxd2 : in std_logic;
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txd2 : out std_logic;
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rts2 : out std_logic;
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videoSync : out std_logic;
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video : out std_logic;
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R : out std_logic_vector(1 downto 0);
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G : out std_logic_vector(1 downto 0);
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B : out std_logic_vector(1 downto 0);
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HS : out std_logic;
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VS : out std_logic;
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hBlank : out std_logic;
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vBlank : out std_logic;
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cepix : out std_logic;
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ps2Clk : in std_logic;
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ps2Data : in std_logic;
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sdCS : out std_logic;
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sdMOSI : out std_logic;
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sdMISO : in std_logic;
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sdSCLK : out std_logic;
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driveLED : out std_logic :='1'
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);
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end MicrocomputerZ80Basic;
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architecture struct of MicrocomputerZ80Basic is
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signal n_WR : std_logic;
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signal n_RD : std_logic;
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signal cpuAddress : std_logic_vector(15 downto 0);
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signal cpuDataOut : std_logic_vector(7 downto 0);
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signal cpuDataIn : std_logic_vector(7 downto 0);
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signal basRomData : std_logic_vector(7 downto 0);
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signal internalRam1DataOut : std_logic_vector(7 downto 0);
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signal internalRam2DataOut : std_logic_vector(7 downto 0);
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signal interface1DataOut : std_logic_vector(7 downto 0);
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signal interface2DataOut : std_logic_vector(7 downto 0);
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signal sdCardDataOut : std_logic_vector(7 downto 0);
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signal n_memWR : std_logic :='1';
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signal n_memRD : std_logic :='1';
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signal n_ioWR : std_logic :='1';
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signal n_ioRD : std_logic :='1';
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signal n_MREQ : std_logic :='1';
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signal n_IORQ : std_logic :='1';
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signal n_int1 : std_logic :='1';
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signal n_int2 : std_logic :='1';
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signal n_externalRamCS : std_logic :='1';
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signal n_internalRam1CS : std_logic :='1';
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signal n_internalRam2CS : std_logic :='1';
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signal n_basRomCS : std_logic :='1';
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signal n_interface1CS : std_logic :='1';
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signal n_interface2CS : std_logic :='1';
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signal n_sdCardCS : std_logic :='1';
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signal serialClkCount : std_logic_vector(15 downto 0);
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signal cpuClkCount : std_logic_vector(5 downto 0);
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signal sdClkCount : std_logic_vector(5 downto 0);
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signal cpuClock : std_logic;
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signal serialClock : std_logic;
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signal sdClock : std_logic;
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begin
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-- ____________________________________________________________________________________
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-- CPU CHOICE GOES HERE
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cpu1 : entity work.t80s
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generic map(mode => 1, t2write => 1, iowait => 0)
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port map(
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reset_n => N_RESET,
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clk_n => cpuClock,
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wait_n => '1',
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int_n => '1',
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nmi_n => '1',
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busrq_n => '1',
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mreq_n => n_MREQ,
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iorq_n => n_IORQ,
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rd_n => n_RD,
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wr_n => n_WR,
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a => cpuAddress,
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di => cpuDataIn,
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do => cpuDataOut
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);
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-- ____________________________________________________________________________________
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-- ROM GOES HERE
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rom1 : entity work.Z80_BASIC_ROM -- 8KB BASIC
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port map(
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address => cpuAddress(12 downto 0),
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clock => clk,
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q => basRomData
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);
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-- ____________________________________________________________________________________
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-- RAM GOES HERE
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ram1: entity work.InternalRam64K
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port map
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(
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address => cpuAddress(15 downto 0),
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clock => clk,
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data => cpuDataOut,
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wren => not(n_memWR or n_internalRam1CS),
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q => internalRam1DataOut
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);
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-- ____________________________________________________________________________________
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-- INPUT/OUTPUT DEVICES GO HERE
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io1 : entity work.SBCTextDisplayRGB
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port map (
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n_reset => N_RESET,
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clk => clk,
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-- RGB video signals
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hSync => HS,
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vSync => VS,
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videoR0 => R(1),
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videoR1 => R(0),
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videoG0 => G(1),
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videoG1 => G(0),
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videoB0 => B(1),
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videoB1 => B(0),
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hBlank => hBlank,
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vBlank => vBlank,
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cepix => cepix,
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-- Monochrome video signals (when using TV timings only)
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sync => videoSync,
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video => video,
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n_wr => n_interface1CS or n_ioWR,
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n_rd => n_interface1CS or n_ioRD,
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n_int => n_int1,
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regSel => cpuAddress(0),
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dataIn => cpuDataOut,
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dataOut => interface1DataOut,
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ps2Clk => ps2Clk,
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ps2Data => ps2Data
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);
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io2 : entity work.bufferedUART
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port map(
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clk => clk,
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n_wr => n_interface2CS or n_ioWR,
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n_rd => n_interface2CS or n_ioRD,
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n_int => n_int2,
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regSel => cpuAddress(0),
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dataIn => cpuDataOut,
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dataOut => interface2DataOut,
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rxClock => serialClock,
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txClock => serialClock,
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rxd => rxd1,
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txd => txd1,
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n_cts => '0',
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n_dcd => '0',
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n_rts => rts1
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);
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sd1 : entity work.sd_controller
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port map(
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sdCS => sdCS,
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sdMOSI => sdMOSI,
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sdMISO => sdMISO,
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sdSCLK => sdSCLK,
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n_wr => n_sdCardCS or n_ioWR,
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n_rd => n_sdCardCS or n_ioRD,
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n_reset => N_RESET,
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dataIn => cpuDataOut,
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dataOut => sdCardDataOut,
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regAddr => cpuAddress(2 downto 0),
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driveLED => driveLED,
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clk => sdClock -- twice the spi clk
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);
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-- ____________________________________________________________________________________
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-- MEMORY READ/WRITE LOGIC GOES HERE
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n_ioWR <= n_WR or n_IORQ;
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n_memWR <= n_WR or n_MREQ;
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n_ioRD <= n_RD or n_IORQ;
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n_memRD <= n_RD or n_MREQ;
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-- ____________________________________________________________________________________
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-- CHIP SELECTS GO HERE
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n_basRomCS <= '0' when cpuAddress(15 downto 13) = "000" else '1'; --8K at bottom of memory
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n_interface1CS <= '0' when cpuAddress(7 downto 1) = "1000000" and (n_ioWR='0' or n_ioRD = '0') else '1'; -- 2 Bytes $80-$81
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n_interface2CS <= '0' when cpuAddress(7 downto 1) = "1000001" and (n_ioWR='0' or n_ioRD = '0') else '1'; -- 2 Bytes $82-$83
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n_sdCardCS <= '0' when cpuAddress(7 downto 3) = "10001" and (n_ioWR='0' or n_ioRD = '0') else '1'; -- 8 Bytes $88-$8F
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n_internalRam1CS <= not n_basRomCS; -- Full Internal RAM - 64 K
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-- ____________________________________________________________________________________
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-- BUS ISOLATION GOES HERE
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cpuDataIn <=
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interface1DataOut when n_interface1CS = '0' else
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interface2DataOut when n_interface2CS = '0' else
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sdCardDataOut when n_sdCardCS = '0' else
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basRomData when n_basRomCS = '0' else
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internalRam1DataOut when n_internalRam1CS= '0' else
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sramData when n_externalRamCS= '0' else
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x"FF";
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-- ____________________________________________________________________________________
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-- SYSTEM CLOCKS GO HERE
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-- SUB-CIRCUIT CLOCK SIGNALS
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serialClock <= serialClkCount(15);
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process (clk)
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begin
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if rising_edge(clk) then
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if cpuClkCount < 4 then -- 4 = 10MHz, 3 = 12.5MHz, 2=16.6MHz, 1=25MHz
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cpuClkCount <= cpuClkCount + 1;
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else
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cpuClkCount <= (others=>'0');
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end if;
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if cpuClkCount < 2 then -- 2 when 10MHz, 2 when 12.5MHz, 2 when 16.6MHz, 1 when 25MHz
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cpuClock <= '0';
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else
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cpuClock <= '1';
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end if;
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if sdClkCount < 49 then -- 1MHz
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sdClkCount <= sdClkCount + 1;
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else
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sdClkCount <= (others=>'0');
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end if;
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if sdClkCount < 25 then
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sdClock <= '0';
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else
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sdClock <= '1';
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end if;
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-- Serial clock DDS
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-- 50MHz master input clock:
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-- Baud Increment
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-- 115200 2416
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-- 38400 805
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-- 19200 403
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-- 9600 201
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-- 4800 101
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-- 2400 50
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serialClkCount <= serialClkCount + 2416;
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end if;
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end process;
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end;
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