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https://github.com/MiSTer-devel/MultiComp_MiSTer.git
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145 lines
5.6 KiB
VHDL
145 lines
5.6 KiB
VHDL
-- megafunction wizard: %ROM: 1-PORT%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: altsyncram
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-- ============================================================
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-- File Name: Z80_BASIC_ROM.vhd
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-- Megafunction Name(s):
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-- altsyncram
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--
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-- Simulation Library Files(s):
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-- altera_mf
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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-- ************************************************************
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--Copyright (C) 2017 Intel Corporation. All rights reserved.
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--Your use of Intel Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Intel Program License
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--Subscription Agreement, the Intel Quartus Prime License Agreement,
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--the Intel MegaCore Function License Agreement, or other
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--applicable license agreement, including, without limitation,
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--that your use is for the sole purpose of programming logic
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--devices manufactured by Intel and sold by Intel or its
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--authorized distributors. Please refer to the applicable
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--agreement for further details.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.altera_mf_components.all;
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ENTITY Z80_BASIC_ROM IS
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PORT
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(
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address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
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clock : IN STD_LOGIC := '1';
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q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
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);
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END Z80_BASIC_ROM;
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ARCHITECTURE SYN OF z80_basic_rom IS
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
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BEGIN
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q <= sub_wire0(7 DOWNTO 0);
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altsyncram_component : altsyncram
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GENERIC MAP (
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address_aclr_a => "NONE",
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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init_file => "./ROMS/Z80/BASIC.HEX",
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intended_device_family => "Cyclone V",
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lpm_hint => "ENABLE_RUNTIME_MOD=NO",
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lpm_type => "altsyncram",
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numwords_a => 8192,
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operation_mode => "ROM",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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widthad_a => 13,
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width_a => 8,
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width_byteena_a => 1
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)
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PORT MAP (
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address_a => address,
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clock0 => clock,
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q_a => sub_wire0
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);
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END SYN;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
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-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
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-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
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-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
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-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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-- Retrieval info: PRIVATE: Clken NUMERIC "0"
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-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
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-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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-- Retrieval info: PRIVATE: MIFfilename STRING "./ROMS/Z80/BASIC.HEX"
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-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
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-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
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-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
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-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
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-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
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-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
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-- Retrieval info: PRIVATE: rden NUMERIC "0"
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-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
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-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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-- Retrieval info: CONSTANT: INIT_FILE STRING "./ROMS/Z80/BASIC.HEX"
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-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
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-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
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-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
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-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
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-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
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-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
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-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
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-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
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-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
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-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
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-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
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-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
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-- Retrieval info: GEN_FILE: TYPE_NORMAL Z80_BASIC_ROM.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL Z80_BASIC_ROM.inc FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL Z80_BASIC_ROM.cmp TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL Z80_BASIC_ROM.bsf FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL Z80_BASIC_ROM_inst.vhd FALSE
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-- Retrieval info: LIB_FILE: altera_mf
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