diff --git a/Components/SDCARD/image_card.sv b/Components/SDCARD/image_card.sv new file mode 100644 index 0000000..8ca3b93 --- /dev/null +++ b/Components/SDCARD/image_card.sv @@ -0,0 +1,540 @@ +// +// sd_card.v +// +// Copyright (c) 2014 Till Harbaum +// Copyright (c) 2015-2018 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the Lesser GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// http://elm-chan.org/docs/mmc/mmc_e.html +// +///////////////////////////////////////////////////////////////////////// + +// +// Made module syncrhronous. Total code refactoring. (Sorgelig) +// clk_spi must be at least 4 x sck for proper work. +// +// this is the old sd_card.sv from sys that worked (there are timing and control code issues with thr new one.) +// could also be in the cpm bios with some of the wait states and timing +// +module image_card #(parameter WIDE = 0) +( + input clk_sys, + input reset, + + input sdhc, + + output [31:0] sd_lba, + output reg sd_rd, + output reg sd_wr, + input sd_ack, + input sd_ack_conf, + + input [AW:0] sd_buff_addr, + input [DW:0] sd_buff_dout, + output [DW:0] sd_buff_din, + input sd_buff_wr, + + // SPI interface + input clk_spi, + + input ss, + input sck, + input mosi, + output reg miso +); + +localparam AW = WIDE ? 7 : 8; +localparam DW = WIDE ? 15 : 7; + +assign sd_lba = sdhc ? lba : {9'd0, lba[31:9]}; + +wire[31:0] OCR = { 1'b1, sdhc, 30'd0 }; // bit30 = 1 -> high capaciry card (sdhc) // bit31 = 0 -> card power up finished +wire [7:0] READ_DATA_TOKEN = 8'hfe; +wire [7:0] WRITE_DATA_RESPONSE = 8'he5; + +// number of bytes to wait after a command before sending the reply +localparam NCR=3; + +localparam RD_STATE_IDLE = 0; +localparam RD_STATE_WAIT_IO = 1; +localparam RD_STATE_SEND_TOKEN = 2; +localparam RD_STATE_SEND_DATA = 3; +localparam RD_STATE_WAIT_M = 4; + +localparam WR_STATE_IDLE = 0; +localparam WR_STATE_EXP_DTOKEN = 1; +localparam WR_STATE_RECV_DATA = 2; +localparam WR_STATE_RECV_CRC0 = 3; +localparam WR_STATE_RECV_CRC1 = 4; +localparam WR_STATE_SEND_DRESP = 5; +localparam WR_STATE_BUSY = 6; + +sdbuf #(WIDE) buffer +( + .clock_a(clk_sys), + .address_a(sd_buff_addr), + .data_a(sd_buff_dout), + .wren_a(sd_ack & sd_buff_wr), + .q_a(sd_buff_din), + + .clock_b(clk_spi), + .address_b(buffer_ptr), + .data_b(buffer_din), + .wren_b(buffer_wr), + .q_b(buffer_dout) +); + +sdbuf #(WIDE) conf +( + .clock_a(clk_sys), + .address_a(sd_buff_addr), + .data_a(sd_buff_dout), + .wren_a(sd_ack_conf & sd_buff_wr), + + .clock_b(clk_spi), + .address_b(buffer_ptr), + .q_b(config_dout) +); + +reg [31:0] lba, new_lba; +reg [8:0] buffer_ptr; +reg [7:0] buffer_din; +wire [7:0] buffer_dout; +wire [7:0] config_dout; +reg buffer_wr; + +always @(posedge clk_spi) begin + reg [2:0] read_state; + reg [2:0] write_state; + reg [6:0] sbuf; + reg cmd55; + reg [7:0] cmd; + reg [2:0] bit_cnt; + reg [3:0] byte_cnt; + reg [7:0] reply; + reg [7:0] reply0, reply1, reply2, reply3; + reg [3:0] reply_len; + reg tx_finish; + reg rx_finish; + reg old_sck; + reg synced; + reg [5:0] ack; + reg io_ack; + reg [4:0] idle_cnt = 0; + reg [2:0] wait_m_cnt; + + if(buffer_wr & ~&buffer_ptr) buffer_ptr <= buffer_ptr + 1'd1; + buffer_wr <= 0; + + ack <= {ack[4:0], sd_ack}; + if(ack[5:4] == 2'b10) io_ack <= 1; + if(ack[5:4] == 2'b01) {sd_rd,sd_wr} <= 0; + + old_sck <= sck; + + if(~ss) idle_cnt <= 31; + else if(~old_sck && sck && idle_cnt) idle_cnt <= idle_cnt - 1'd1; + + if(reset || !idle_cnt) begin + bit_cnt <= 0; + byte_cnt <= 15; + synced <= 0; + miso <= 1; + sbuf <= 7'b1111111; + tx_finish <= 0; + rx_finish <= 0; + read_state <= RD_STATE_IDLE; + write_state <= WR_STATE_IDLE; + end + + if(old_sck & ~sck & ~ss) begin + tx_finish <= 0; + miso <= 1; // default: send 1's (busy/wait) + + if(byte_cnt == 5+NCR) begin + miso <= reply[~bit_cnt]; + + if(bit_cnt == 7) begin + // these three commands all have a reply_len of 0 and will thus + // not send more than a single reply byte + + // CMD9: SEND_CSD + // CMD10: SEND_CID + if((cmd == 'h49) | (cmd == 'h4a)) + read_state <= RD_STATE_SEND_TOKEN; // jump directly to data transmission + + // CMD17/CMD18 + if((cmd == 'h51) | (cmd == 'h52)) begin + io_ack <= 0; + read_state <= RD_STATE_WAIT_IO; // start waiting for data from io controller + lba <= new_lba; + sd_rd <= 1; // trigger request to io controller + end + end + end + else if((reply_len > 0) && (byte_cnt == 5+NCR+1)) miso <= reply0[~bit_cnt]; + else if((reply_len > 1) && (byte_cnt == 5+NCR+2)) miso <= reply1[~bit_cnt]; + else if((reply_len > 2) && (byte_cnt == 5+NCR+3)) miso <= reply2[~bit_cnt]; + else if((reply_len > 3) && (byte_cnt == 5+NCR+4)) miso <= reply3[~bit_cnt]; + else begin + if(byte_cnt > 5+NCR && read_state==RD_STATE_IDLE && write_state==WR_STATE_IDLE) tx_finish <= 1; + end + + // ---------- read state machine processing ------------- + + case(read_state) + RD_STATE_IDLE: ; // do nothing + + + // waiting for io controller to return data + RD_STATE_WAIT_IO: begin + if(io_ack & (bit_cnt == 7)) read_state <= RD_STATE_SEND_TOKEN; + end + + // send data token + RD_STATE_SEND_TOKEN: begin + miso <= READ_DATA_TOKEN[~bit_cnt]; + + if(bit_cnt == 7) begin + read_state <= RD_STATE_SEND_DATA; // next: send data + buffer_ptr <= 0; + if(cmd == 'h49) buffer_ptr <= 16; + end + end + + // send data + RD_STATE_SEND_DATA: begin + + miso <= ((cmd == 'h49) | (cmd == 'h4A)) ? config_dout[~bit_cnt] : buffer_dout[~bit_cnt]; + + if(bit_cnt == 7) begin + + // sent 512 sector data bytes? + if((cmd == 'h51) & &buffer_ptr) read_state <= RD_STATE_IDLE; + else if((cmd == 'h52) & &buffer_ptr) begin + read_state <= RD_STATE_WAIT_M; + wait_m_cnt <= 0; + end + + // sent 16 cid/csd data bytes? + else if(((cmd == 'h49) | (cmd == 'h4a)) & (&buffer_ptr[3:0])) read_state <= RD_STATE_IDLE; + + // not done yet -> trigger read of next data byte + else buffer_ptr <= buffer_ptr + 1'd1; + end + end + + RD_STATE_WAIT_M: begin + if(bit_cnt == 7) begin + wait_m_cnt <= wait_m_cnt + 1'd1; + if(&wait_m_cnt) begin + lba <= lba + 1; + io_ack <= 0; + sd_rd <= 1; + read_state <= RD_STATE_WAIT_IO; + end + end + end + endcase + + // ------------------ write support ---------------------- + // send write data response + if(write_state == WR_STATE_SEND_DRESP) miso <= WRITE_DATA_RESPONSE[~bit_cnt]; + + // busy after write until the io controller sends ack + if(write_state == WR_STATE_BUSY) miso <= 0; + end + + if(~old_sck & sck & ~ss) begin + + if(synced) bit_cnt <= bit_cnt + 1'd1; + + // assemble byte + if(bit_cnt != 7) begin + sbuf[6:0] <= { sbuf[5:0], mosi }; + + // resync while waiting for token + if(write_state==WR_STATE_EXP_DTOKEN) begin + if(cmd == 'h58) begin + if({sbuf,mosi} == 8'hfe) begin + write_state <= WR_STATE_RECV_DATA; + buffer_ptr <= 0; + bit_cnt <= 0; + end + end + else begin + if({sbuf,mosi} == 8'hfc) begin + write_state <= WR_STATE_RECV_DATA; + buffer_ptr <= 0; + bit_cnt <= 0; + end + if({sbuf,mosi} == 8'hfd) begin + write_state <= WR_STATE_IDLE; + rx_finish <= 1; + bit_cnt <= 0; + end + end + end + end + else begin + // finished reading one byte + // byte counter runs against 15 byte boundary + if(byte_cnt != 15) byte_cnt <= byte_cnt + 1'd1; + + // byte_cnt > 6 -> complete command received + // first byte of valid command is 01xxxxxx + // don't accept new commands once a write or read command has been accepted + if((byte_cnt > 5) & (write_state == WR_STATE_IDLE) & (read_state == RD_STATE_IDLE) && !rx_finish) begin + byte_cnt <= 0; + cmd <= { sbuf, mosi}; + + // set cmd55 flag if previous command was 55 + cmd55 <= (cmd == 'h77); + end + + if((byte_cnt > 5) & (read_state == RD_STATE_WAIT_M) && ({sbuf, mosi} == 8'h4c)) begin + byte_cnt <= 0; + rx_finish <= 0; + cmd <= {sbuf, mosi}; + read_state <= RD_STATE_IDLE; + end + + // parse additional command bytes + if(byte_cnt == 0) new_lba[31:24] <= { sbuf, mosi}; + if(byte_cnt == 1) new_lba[23:16] <= { sbuf, mosi}; + if(byte_cnt == 2) new_lba[15:8] <= { sbuf, mosi}; + if(byte_cnt == 3) new_lba[7:0] <= { sbuf, mosi}; + + // last byte (crc) received, evaluate + if(byte_cnt == 4) begin + + // default: + reply <= 4; // illegal command + reply_len <= 0; // no extra reply bytes + rx_finish <= 1; + + case(cmd) + // CMD0: GO_IDLE_STATE + 'h40: reply <= 1; // ok, busy + + // CMD1: SEND_OP_COND + 'h41: reply <= 0; // ok, not busy + + // CMD8: SEND_IF_COND (V2 only) + 'h48: begin + reply <= 1; // ok, busy + + reply0 <= 'h00; + reply1 <= 'h00; + reply2 <= 'h01; + reply3 <= 'hAA; + reply_len <= 4; + end + + // CMD9: SEND_CSD + 'h49: reply <= 0; // ok + + // CMD10: SEND_CID + 'h4a: reply <= 0; // ok + + // CMD12: STOP_TRANSMISSION + 'h4c: reply <= 0; // ok + + // CMD13: SEND_STATUS + 'h4d: begin + reply <= 'h00; // ok + reply0 <='h00; + reply_len <= 1; + end + + // CMD16: SET_BLOCKLEN + 'h50: begin + // we only support a block size of 512 + if(new_lba == 512) reply <= 0; // ok + else reply <= 'h40; // parmeter error + end + + // CMD17: READ_SINGLE_BLOCK + 'h51: reply <= 0; // ok + + // CMD18: READ_MULTIPLE + 'h52: reply <= 0; // ok + // ACMD23: SET_WR_BLK_ERASE_COUNT + 'h57: reply <= 0; //ok + + // CMD24: WRITE_BLOCK + 'h58, + // CMD25: WRITE_MULTIPLE + 'h59: begin + reply <= 0; // ok + write_state <= WR_STATE_EXP_DTOKEN; // expect data token + rx_finish <=0; + lba <= new_lba; + end + + // ACMD41: APP_SEND_OP_COND + 'h69: if(cmd55) reply <= 0; // ok, not busy + + // CMD55: APP_COND + 'h77: reply <= 1; // ok, busy + + // CMD58: READ_OCR + 'h7a: begin + reply <= 0; // ok + + reply0 <= OCR[31:24]; // bit 30 = 1 -> high capacity card + reply1 <= OCR[23:16]; + reply2 <= OCR[15:8]; + reply3 <= OCR[7:0]; + reply_len <= 4; + end + + // CMD59: CRC_ON_OFF + 'h7b: reply <= 0; // ok + endcase + end + + // ---------- handle write ----------- + case(write_state) + // do nothing in idle state + WR_STATE_IDLE: ; + + // waiting for data token + WR_STATE_EXP_DTOKEN: begin + buffer_ptr <= 0; + if(cmd == 'h58) begin + if({sbuf,mosi} == 8'hfe) write_state <= WR_STATE_RECV_DATA; + end + else begin + if({sbuf,mosi} == 8'hfc) write_state <= WR_STATE_RECV_DATA; + if({sbuf,mosi} == 8'hfd) begin + write_state <= WR_STATE_IDLE; + rx_finish <= 1; + end + end + end + + // transfer 512 bytes + WR_STATE_RECV_DATA: begin + // push one byte into local buffer + buffer_wr <= 1; + buffer_din <= {sbuf, mosi}; + + // all bytes written? + if(&buffer_ptr) write_state <= WR_STATE_RECV_CRC0; + end + + // transfer 1st crc byte + WR_STATE_RECV_CRC0: + write_state <= WR_STATE_RECV_CRC1; + + // transfer 2nd crc byte + WR_STATE_RECV_CRC1: + write_state <= WR_STATE_SEND_DRESP; + + // send data response + WR_STATE_SEND_DRESP: begin + write_state <= WR_STATE_BUSY; + io_ack <= 0; + sd_wr <= 1; + end + + // wait for io controller to accept data + WR_STATE_BUSY: + if(io_ack) begin + if(cmd == 'h59) begin + write_state <= WR_STATE_EXP_DTOKEN; + lba <= lba + 1; + end + else begin + write_state <= WR_STATE_IDLE; + rx_finish <= 1; + end + end + endcase + end + + // wait for first 0 bit until start counting bits + if(!synced && !mosi) begin + synced <= 1; + bit_cnt <= 1; // byte assembly prepare for next time loop + sbuf <= 7'b1111110; // byte assembly prepare for next time loop + rx_finish<= 0; + end else if (synced && tx_finish && rx_finish ) begin + synced <= 0; + bit_cnt <= 0; + rx_finish<= 0; + end + end +end + +endmodule + +module sdbuf #(parameter WIDE) +( + input clock_a, + input [AW:0] address_a, + input [DW:0] data_a, + input wren_a, + output reg [DW:0] q_a, + + input clock_b, + input [8:0] address_b, + input [7:0] data_b, + input wren_b, + output reg [7:0] q_b +); + +localparam AW = WIDE ? 7 : 8; +localparam DW = WIDE ? 15 : 7; + +always@(posedge clock_a) begin + if(wren_a) begin + ram[address_a] <= data_a; + q_a <= data_a; + end + else begin + q_a <= ram[address_a]; + end +end + +generate + if(WIDE) begin + reg [1:0][7:0] ram[1<<8]; + always@(posedge clock_b) begin + if(wren_b) begin + ram[address_b[8:1]][address_b[0]] <= data_b; + q_b <= data_b; + end + else begin + q_b <= ram[address_b[8:1]][address_b[0]]; + end + end + end + else begin + reg [7:0] ram[1<<9]; + always@(posedge clock_b) begin + if(wren_b) begin + ram[address_b] <= data_b; + q_b <= data_b; + end + else begin + q_b <= ram[address_b]; + end + end + end +endgenerate + +endmodule diff --git a/MultiComp-lite.qsf b/MultiComp-lite.qsf index cc9c504..0118ff8 100644 --- a/MultiComp-lite.qsf +++ b/MultiComp-lite.qsf @@ -371,6 +371,7 @@ set_global_assignment -name VHDL_FILE Components/M6502/T65.vhd set_global_assignment -name VHDL_FILE Components/UART/bufferedUART.vhd set_global_assignment -name VHDL_FILE Components/SDCARD/sd_controller.vhd set_global_assignment -name VHDL_FILE Components/SDCARD/image_controller.vhd +set_global_assignment -name VHDL_FILE Components/SDCARD/image_card.sv set_global_assignment -name QIP_FILE Components/INTERNALRAM/InternalRam64K.qip set_global_assignment -name VHDL_FILE Components/TERMINAL/SBCTextDisplayRGB.vhd set_global_assignment -name VHDL_FILE Components/TERMINAL/CGABoldRom.vhd diff --git a/MultiComp.qsf b/MultiComp.qsf index f32bced..3376412 100644 --- a/MultiComp.qsf +++ b/MultiComp.qsf @@ -293,6 +293,9 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_* set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_* set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_* +set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name USE_SIGNALTAP_FILE "output_files/status13-stp1.stp" +set_global_assignment -name SYSTEMVERILOG_FILE Components/SDCARD/image_card.sv set_global_assignment -name VERILOG_FILE Components/USB/spi_master_simple.v set_global_assignment -name VERILOG_FILE Components/USB/ch376s.v set_global_assignment -name CDF_FILE jtag.cdf @@ -329,86 +332,6 @@ set_global_assignment -name VHDL_FILE MicrocomputerZ80CPM.vhd set_global_assignment -name VHDL_FILE Microcomputer6502Basic.vhd set_global_assignment -name VHDL_FILE Microcomputer6809Basic.vhd set_global_assignment -name VHDL_FILE MicrocomputerZ80Basic.vhd -set_global_assignment -name ENABLE_SIGNALTAP ON -set_global_assignment -name USE_SIGNALTAP_FILE "output_files/status13-stp1.stp" set_global_assignment -name SIGNALTAP_FILE "output_files/status13-stp1.stp" -set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "emu:emu|CLK_50M" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|dataOut[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|dataOut[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|dataOut[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|dataOut[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|dataOut[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|dataOut[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|dataOut[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|dataOut[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|n_reset" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|dataOut[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|dataOut[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|dataOut[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|dataOut[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|dataOut[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|dataOut[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|dataOut[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|dataOut[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "emu:emu|MicrocomputerZ80CPM:MicrocomputerZ80CPM|sd_controller:sd1|n_reset" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=9" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=9" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=9" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=48" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to auto_signaltap_0|vcc -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|gnd -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0 set_global_assignment -name SLD_FILE "db/status13-stp1_auto_stripped.stp" set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/MultiComp.sv b/MultiComp.sv index 65aec92..cc965e9 100644 --- a/MultiComp.sv +++ b/MultiComp.sv @@ -35,7 +35,7 @@ module emu input RESET, //Must be passed to hps_io module - inout [45:0] HPS_BUS, + inout [48:0] HPS_BUS, //Base video clock. Usually equals to CLK_SYS. output CLK_VIDEO, @@ -45,8 +45,9 @@ module emu output CE_PIXEL, //Video aspect ratio for HDMI. Most retro systems have ratio 4:3. - output [7:0] VIDEO_ARX, - output [7:0] VIDEO_ARY, + //if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio. + output [12:0] VIDEO_ARX, + output [12:0] VIDEO_ARY, output [7:0] VGA_R, output [7:0] VGA_G, @@ -56,15 +57,22 @@ module emu output VGA_DE, // = ~(VBlank | HBlank) output VGA_F1, output [1:0] VGA_SL, + output VGA_SCALER, // Force VGA scaler + output VGA_DISABLE, // analog out is off - /* - // Use framebuffer from DDRAM (USE_FB=1 in qsf) + input [11:0] HDMI_WIDTH, + input [11:0] HDMI_HEIGHT, + output HDMI_FREEZE, + output HDMI_BLACKOUT, + +`ifdef MISTER_FB + // Use framebuffer in DDRAM // FB_FORMAT: // [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp // [3] : 0=16bits 565 1=16bits 1555 // [4] : 0=RGB 1=BGR (for 16/24/32 modes) // - // FB_STRIDE either 0 (rounded to 256 bytes) or multiple of 16 bytes. + // FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes) output FB_EN, output [4:0] FB_FORMAT, output [11:0] FB_WIDTH, @@ -75,6 +83,7 @@ module emu input FB_LL, output FB_FORCE_BLANK, +`ifdef MISTER_FB_PALETTE // Palette control for 8bit modes. // Ignored for other video modes. output FB_PAL_CLK, @@ -82,7 +91,8 @@ module emu output [23:0] FB_PAL_DOUT, input [23:0] FB_PAL_DIN, output FB_PAL_WR, - */ +`endif +`endif output LED_USER, // 1 - ON, 0 - OFF. @@ -106,7 +116,7 @@ module emu //ADC inout [3:0] ADC_BUS, - //SD-SPI SECONDARY SDCARD + //SD-SPI output SD_SCK, output SD_MOSI, input SD_MISO, @@ -139,6 +149,20 @@ module emu output SDRAM_nRAS, output SDRAM_nWE, +`ifdef MISTER_DUAL_SDRAM + //Secondary SDRAM + //Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0 + input SDRAM2_EN, + output SDRAM2_CLK, + output [12:0] SDRAM2_A, + output [1:0] SDRAM2_BA, + inout [15:0] SDRAM2_DQ, + output SDRAM2_nCS, + output SDRAM2_nCAS, + output SDRAM2_nRAS, + output SDRAM2_nWE, +`endif + input UART_CTS, output UART_RTS, input UART_RXD, @@ -149,7 +173,7 @@ module emu // Open-drain User port. // 0 - D+/RX // 1 - D-/TX - // 2..6 - RTS,CTS,DTR,DSR,IO6 + // 2..6 - USR2..USR6 // Set USER_OUT to 1 to read from USER_IN. input [6:0] USER_IN, output [6:0] USER_OUT, @@ -221,7 +245,7 @@ assign AUDIO_R = 0; assign AUDIO_MIX = 0; `include "build_id.v" -localparam CONF_STR = { +parameter CONF_STR = { "MultiComp;;", "S,IMG;", "OF,Reset after Mount,No,Yes;", @@ -238,20 +262,20 @@ localparam CONF_STR = { ////////////////// HPS I/O /////////////////// wire [1:0] buttons; -wire [31:0] status; +wire [127:0] status; wire PS2_CLK; wire PS2_DAT; wire forced_scandoubler; -wire [31:0] sd_lba; +wire [31:0] sd_lba[1]; wire sd_rd; wire sd_wr; wire sd_ack; wire [8:0] sd_buff_addr; wire [7:0] sd_buff_dout; -wire [7:0] sd_buff_din; +wire [7:0] sd_buff_din[1]; wire sd_buff_wr; wire sd_ack_conf; wire img_mounted; @@ -259,15 +283,13 @@ wire img_readonly; wire [63:0] img_size; hps_io #( - .STRLEN($size(CONF_STR)>>3), + .CONF_STR(CONF_STR), .PS2DIV (2000) ) hps_io ( .clk_sys(CLK_50M), .HPS_BUS(HPS_BUS), - .conf_str(CONF_STR), - .buttons(buttons), .status(status), .forced_scandoubler(forced_scandoubler), @@ -279,7 +301,6 @@ hps_io #( .sd_rd(sd_rd), .sd_wr(sd_wr), .sd_ack(sd_ack), - .sd_ack_conf(sd_ack_conf), .sd_buff_addr(sd_buff_addr), .sd_buff_dout(sd_buff_dout), .sd_buff_din(sd_buff_din), @@ -287,9 +308,7 @@ hps_io #( .img_mounted(img_mounted), .img_readonly(img_readonly), - .img_size(img_size), - - .uart_mode(16'b000_11111_000_11111) + .img_size(img_size) ); /////////////////////// CLOCKS /////////////////////////////// @@ -305,7 +324,22 @@ pll pll ///////////////// RESET ///////////////////////// -wire reset = RESET | status[0] | buttons[1] | (status[15] && img_mounted); +reg reset_from_mount = 0; +reg [15:0] reset_counter = 0; + +always @(posedge clk_sys) begin + if(img_mounted & status[15]) begin + reset_from_mount <= 1; + reset_counter <= 0; + end else if(reset_from_mount) begin + if(reset_counter < 16'hffff) + reset_counter <= reset_counter + 1; + else + reset_from_mount <= 0; + end +end + +wire reset = RESET | status[0] | buttons[1] | reset_from_mount; ///////////////// SDCARD //////////////////////// @@ -317,18 +351,43 @@ wire sdss; wire vsdmiso; reg vsd_sel = 0; -always @(posedge clk_sys) if(img_mounted) vsd_sel <= |img_size; +always @(posedge clk_sys) begin + if(RESET) begin // Only clear on hard reset + vsd_sel <= 0; + end + else begin + if(img_mounted) begin + // Latch the selection based on image size + vsd_sel <= |img_size; + end + end +end -sd_card sd_card +//always @(posedge clk_sys) if(img_mounted) vsd_sel <= |img_size; + +image_card image_card ( - .*, + .clk_sys(clk_sys), + .reset(reset), + .sdhc(1), + //.img_mounted(img_mounted), + //.img_size(img_size), - .clk_spi(clk_sys), - .sdhc(1), - .sck(sdclk), - .ss(sdss | ~vsd_sel), - .mosi(sdmosi), - .miso(vsdmiso) + .sd_lba(sd_lba[0]), + .sd_rd(sd_rd), // New connection + .sd_wr(sd_wr), // New connection + .sd_ack(sd_ack), // New connection + + .sd_buff_addr(sd_buff_addr), // New connection + .sd_buff_dout(sd_buff_dout), // New connection + .sd_buff_din(sd_buff_din[0]), + .sd_buff_wr(sd_buff_wr), // New connection + + .clk_spi(clk_sys), + .ss(sdss | ~vsd_sel), + .sck(sdclk), + .mosi(sdmosi), + .miso(vsdmiso) ); assign SD_CS = sdss | vsd_sel; diff --git a/build_id.v b/build_id.v index e387467..077f20d 100644 --- a/build_id.v +++ b/build_id.v @@ -1 +1 @@ -`define BUILD_DATE "241215" \ No newline at end of file +`define BUILD_DATE "241216" \ No newline at end of file diff --git a/releases/MultiComp_20241216.rbf b/releases/MultiComp_20241216.rbf new file mode 100644 index 0000000..dd4f17d Binary files /dev/null and b/releases/MultiComp_20241216.rbf differ diff --git a/sys/arcade_video.v b/sys/arcade_video.v index 1f853d1..f41d042 100644 --- a/sys/arcade_video.v +++ b/sys/arcade_video.v @@ -1,296 +1,329 @@ -//============================================================================ -// -// Copyright (C) 2017-2020 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -// -//============================================================================ - -////////////////////////////////////////////////////////// -// DW: -// 6 : 2R 2G 2B -// 8 : 3R 3G 2B -// 9 : 3R 3G 3B -// 12 : 4R 4G 4B -// 24 : 8R 8G 8B - -module arcade_video #(parameter WIDTH=320, DW=8, GAMMA=1) -( - input clk_video, - input ce_pix, - - input[DW-1:0] RGB_in, - input HBlank, - input VBlank, - input HSync, - input VSync, - - output CLK_VIDEO, - output CE_PIXEL, - output [7:0] VGA_R, - output [7:0] VGA_G, - output [7:0] VGA_B, - output VGA_HS, - output VGA_VS, - output VGA_DE, - output [1:0] VGA_SL, - - input [2:0] fx, - input forced_scandoubler, - inout [21:0] gamma_bus -); - -assign CLK_VIDEO = clk_video; - -wire hs_fix,vs_fix; -sync_fix sync_v(CLK_VIDEO, HSync, hs_fix); -sync_fix sync_h(CLK_VIDEO, VSync, vs_fix); - -reg [DW-1:0] RGB_fix; - -reg CE,HS,VS,HBL,VBL; -always @(posedge CLK_VIDEO) begin - reg old_ce; - old_ce <= ce_pix; - CE <= 0; - if(~old_ce & ce_pix) begin - CE <= 1; - HS <= hs_fix; - if(~HS & hs_fix) VS <= vs_fix; - - RGB_fix <= RGB_in; - HBL <= HBlank; - if(HBL & ~HBlank) VBL <= VBlank; - end -end - -wire [7:0] R,G,B; - -generate - if(DW == 6) begin - assign R = {RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4]}; - assign G = {RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2]}; - assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]}; - end - else if(DW == 8) begin - assign R = {RGB_fix[7:5],RGB_fix[7:5],RGB_fix[7:6]}; - assign G = {RGB_fix[4:2],RGB_fix[4:2],RGB_fix[4:3]}; - assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]}; - end - else if(DW == 9) begin - assign R = {RGB_fix[8:6],RGB_fix[8:6],RGB_fix[8:7]}; - assign G = {RGB_fix[5:3],RGB_fix[5:3],RGB_fix[5:4]}; - assign B = {RGB_fix[2:0],RGB_fix[2:0],RGB_fix[2:1]}; - end - else if(DW == 12) begin - assign R = {RGB_fix[11:8],RGB_fix[11:8]}; - assign G = {RGB_fix[7:4],RGB_fix[7:4]}; - assign B = {RGB_fix[3:0],RGB_fix[3:0]}; - end - else begin // 24 - assign R = RGB_fix[23:16]; - assign G = RGB_fix[15:8]; - assign B = RGB_fix[7:0]; - end -endgenerate - -assign VGA_SL = sl[1:0]; -wire [2:0] sl = fx ? fx - 1'd1 : 3'd0; -wire scandoubler = fx || forced_scandoubler; - -video_mixer #(.LINE_LENGTH(WIDTH+4), .HALF_DEPTH(DW!=24), .GAMMA(GAMMA)) video_mixer -( - .clk_vid(CLK_VIDEO), - .ce_pix(CE), - .ce_pix_out(CE_PIXEL), - - .scandoubler(scandoubler), - .hq2x(fx==1), - .gamma_bus(gamma_bus), - - .R((DW!=24) ? R[7:4] : R), - .G((DW!=24) ? G[7:4] : G), - .B((DW!=24) ? B[7:4] : B), - - .HSync (HS), - .VSync (VS), - .HBlank(HBL), - .VBlank(VBL), - - .VGA_R(VGA_R), - .VGA_G(VGA_G), - .VGA_B(VGA_B), - .VGA_VS(VGA_VS), - .VGA_HS(VGA_HS), - .VGA_DE(VGA_DE) -); - -endmodule - -//============================================================================ -// -// Screen +90/-90 deg. rotation -// Copyright (C) 2020 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -// -//============================================================================ - -module screen_rotate -( - input CLK_VIDEO, - input CE_PIXEL, - - input [7:0] VGA_R, - input [7:0] VGA_G, - input [7:0] VGA_B, - input VGA_HS, - input VGA_VS, - input VGA_DE, - - input rotate_ccw, - input no_rotate, - - output FB_EN, - output [4:0] FB_FORMAT, - output [11:0] FB_WIDTH, - output [11:0] FB_HEIGHT, - output [31:0] FB_BASE, - output [13:0] FB_STRIDE, - input FB_VBL, - input FB_LL, - - output DDRAM_CLK, - input DDRAM_BUSY, - output [7:0] DDRAM_BURSTCNT, - output [28:0] DDRAM_ADDR, - output [63:0] DDRAM_DIN, - output [7:0] DDRAM_BE, - output DDRAM_WE, - output DDRAM_RD -); - -parameter MEM_BASE = 7'b0010010; // buffer at 0x24000000, 3x8MB - -assign DDRAM_CLK = CLK_VIDEO; -assign DDRAM_BURSTCNT = 1; -assign DDRAM_ADDR = {MEM_BASE, i_fb, ram_addr[22:3]}; -assign DDRAM_BE = ram_addr[2] ? 8'hF0 : 8'h0F; -assign DDRAM_DIN = {ram_data,ram_data}; -assign DDRAM_WE = ram_wr; -assign DDRAM_RD = 0; - -assign FB_EN = ~no_rotate; -assign FB_FORMAT = 5'b00110; -assign FB_BASE = {MEM_BASE,o_fb,23'd0}; -assign FB_WIDTH = vsz; -assign FB_HEIGHT = hsz; -assign FB_STRIDE = stride; - -function [1:0] buf_next; - input [1:0] a,b; - begin - buf_next = 1; - if ((a==0 && b==1) || (a==1 && b==0)) buf_next = 2; - if ((a==1 && b==2) || (a==2 && b==1)) buf_next = 0; - end -endfunction - -reg [1:0] i_fb,o_fb; -always @(posedge CLK_VIDEO) begin - reg old_vbl,old_vs; - old_vbl <= FB_VBL; - old_vs <= VGA_VS; - - if(FB_LL) begin - if(~old_vbl & FB_VBL) o_fb<={1'b0,~i_fb[0]}; - if(~old_vs & VGA_VS) i_fb<={1'b0,~i_fb[0]}; - end - else begin - if(~old_vbl & FB_VBL) o_fb<=buf_next(o_fb,i_fb); - if(~old_vs & VGA_VS) i_fb<=buf_next(i_fb,o_fb); - end -end - -reg [11:0] hsz = 320, vsz = 240; -reg [11:0] bwidth; -reg [22:0] bufsize; -always @(posedge CLK_VIDEO) begin - reg [11:0] hcnt = 0, vcnt = 0; - reg old_vs, old_de; - - if(CE_PIXEL) begin - old_vs <= VGA_VS; - old_de <= VGA_DE; - - hcnt <= hcnt + 1'd1; - if(~old_de & VGA_DE) begin - hcnt <= 1; - vcnt <= vcnt + 1'd1; - end - if(old_de & ~VGA_DE) hsz <= hcnt; - if(~old_vs & VGA_VS) begin - vsz <= vcnt; - bwidth <= vcnt + 2'd3; - vcnt <= 0; - end - if(old_vs & ~VGA_VS) bufsize <= hsz * stride; - end -end - -wire [13:0] stride = {bwidth[11:2], 4'd0}; - -reg [22:0] ram_addr, next_addr; -reg [31:0] ram_data; -reg ram_wr; -always @(posedge CLK_VIDEO) begin - reg [13:0] hcnt = 0; - reg old_vs, old_de; - - ram_wr <= 0; - if(CE_PIXEL) begin - old_vs <= VGA_VS; - old_de <= VGA_DE; - - if(~old_vs & VGA_VS) begin - next_addr <= rotate_ccw ? (bufsize - stride) : {vsz-1'd1, 2'b00}; - hcnt <= rotate_ccw ? 3'd4 : {vsz-2'd2, 2'b00}; - end - if(VGA_DE) begin - ram_wr <= 1; - ram_data <= {VGA_B,VGA_G,VGA_R}; - ram_addr <= next_addr; - next_addr <= rotate_ccw ? (next_addr - stride) : (next_addr + stride); - end - if(old_de & ~VGA_DE) begin - next_addr <= rotate_ccw ? (bufsize - stride + hcnt) : hcnt; - hcnt <= rotate_ccw ? (hcnt + 3'd4) : (hcnt - 3'd4); - end - end -end - -endmodule +//============================================================================ +// +// Copyright (C) 2017-2020 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +//============================================================================ + +////////////////////////////////////////////////////////// +// DW: +// 6 : 2R 2G 2B +// 8 : 3R 3G 2B +// 9 : 3R 3G 3B +// 12 : 4R 4G 4B +// 24 : 8R 8G 8B + +module arcade_video #(parameter WIDTH=320, DW=8, GAMMA=1) +( + input clk_video, + input ce_pix, + + input[DW-1:0] RGB_in, + input HBlank, + input VBlank, + input HSync, + input VSync, + + output CLK_VIDEO, + output CE_PIXEL, + output [7:0] VGA_R, + output [7:0] VGA_G, + output [7:0] VGA_B, + output VGA_HS, + output VGA_VS, + output VGA_DE, + output [1:0] VGA_SL, + + input [2:0] fx, + input forced_scandoubler, + inout [21:0] gamma_bus +); + +assign CLK_VIDEO = clk_video; + +wire hs_fix,vs_fix; +sync_fix sync_v(CLK_VIDEO, HSync, hs_fix); +sync_fix sync_h(CLK_VIDEO, VSync, vs_fix); + +reg [DW-1:0] RGB_fix; + +reg CE,HS,VS,HBL,VBL; +always @(posedge CLK_VIDEO) begin + reg old_ce; + old_ce <= ce_pix; + CE <= 0; + if(~old_ce & ce_pix) begin + CE <= 1; + HS <= hs_fix; + if(~HS & hs_fix) VS <= vs_fix; + + RGB_fix <= RGB_in; + HBL <= HBlank; + if(HBL & ~HBlank) VBL <= VBlank; + end +end + +wire [7:0] R,G,B; + +generate + if(DW == 6) begin + assign R = {RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4]}; + assign G = {RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2]}; + assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]}; + end + else if(DW == 8) begin + assign R = {RGB_fix[7:5],RGB_fix[7:5],RGB_fix[7:6]}; + assign G = {RGB_fix[4:2],RGB_fix[4:2],RGB_fix[4:3]}; + assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]}; + end + else if(DW == 9) begin + assign R = {RGB_fix[8:6],RGB_fix[8:6],RGB_fix[8:7]}; + assign G = {RGB_fix[5:3],RGB_fix[5:3],RGB_fix[5:4]}; + assign B = {RGB_fix[2:0],RGB_fix[2:0],RGB_fix[2:1]}; + end + else if(DW == 12) begin + assign R = {RGB_fix[11:8],RGB_fix[11:8]}; + assign G = {RGB_fix[7:4],RGB_fix[7:4]}; + assign B = {RGB_fix[3:0],RGB_fix[3:0]}; + end + else if(DW == 18) begin + assign R = {RGB_fix[17:12],RGB_fix[17:16]}; + assign G = {RGB_fix[11: 6],RGB_fix[11:10]}; + assign B = {RGB_fix[ 5: 0],RGB_fix[ 5: 4]}; + end + else begin // 24 + assign R = RGB_fix[23:16]; + assign G = RGB_fix[15:8]; + assign B = RGB_fix[7:0]; + end +endgenerate + +assign VGA_SL = sl[1:0]; +wire [2:0] sl = fx ? fx - 1'd1 : 3'd0; +wire scandoubler = fx || forced_scandoubler; + +video_mixer #(.LINE_LENGTH(WIDTH+4), .HALF_DEPTH(DW!=24), .GAMMA(GAMMA)) video_mixer +( + .CLK_VIDEO(CLK_VIDEO), + .ce_pix(CE), + .CE_PIXEL(CE_PIXEL), + + .scandoubler(scandoubler), + .hq2x(fx==1), + .gamma_bus(gamma_bus), + + .R((DW!=24) ? R[7:4] : R), + .G((DW!=24) ? G[7:4] : G), + .B((DW!=24) ? B[7:4] : B), + + .HSync (HS), + .VSync (VS), + .HBlank(HBL), + .VBlank(VBL), + + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_VS(VGA_VS), + .VGA_HS(VGA_HS), + .VGA_DE(VGA_DE) +); + +endmodule + +//============================================================================ +// +// Screen +90/-90 deg. rotation +// Copyright (C) 2020 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +//============================================================================ + +module screen_rotate +( + input CLK_VIDEO, + input CE_PIXEL, + + input [7:0] VGA_R, + input [7:0] VGA_G, + input [7:0] VGA_B, + input VGA_HS, + input VGA_VS, + input VGA_DE, + + input rotate_ccw, + input no_rotate, + input flip, + output video_rotated, + + output FB_EN, + output [4:0] FB_FORMAT, + output reg [11:0] FB_WIDTH, + output reg [11:0] FB_HEIGHT, + output [31:0] FB_BASE, + output [13:0] FB_STRIDE, + input FB_VBL, + input FB_LL, + + output DDRAM_CLK, + input DDRAM_BUSY, + output [7:0] DDRAM_BURSTCNT, + output [28:0] DDRAM_ADDR, + output [63:0] DDRAM_DIN, + output [7:0] DDRAM_BE, + output DDRAM_WE, + output DDRAM_RD +); + +parameter MEM_BASE = 7'b0010010; // buffer at 0x24000000, 3x8MB + +reg do_flip; + +assign DDRAM_CLK = CLK_VIDEO; +assign DDRAM_BURSTCNT = 1; +assign DDRAM_ADDR = {MEM_BASE, i_fb, ram_addr[22:3]}; +assign DDRAM_BE = ram_addr[2] ? 8'hF0 : 8'h0F; +assign DDRAM_DIN = {ram_data,ram_data}; +assign DDRAM_WE = ram_wr; +assign DDRAM_RD = 0; + +assign FB_EN = fb_en[2]; +assign FB_FORMAT = 5'b00110; +assign FB_BASE = {MEM_BASE,o_fb,23'd0}; +assign FB_STRIDE = stride; + +function [1:0] buf_next; + input [1:0] a,b; + begin + buf_next = 1; + if ((a==0 && b==1) || (a==1 && b==0)) buf_next = 2; + if ((a==1 && b==2) || (a==2 && b==1)) buf_next = 0; + end +endfunction + +assign video_rotated = ~no_rotate; + +always @(posedge CLK_VIDEO) begin + do_flip <= no_rotate && flip; + if( do_flip ) begin + FB_WIDTH <= hsz; + FB_HEIGHT <= vsz; + end else begin + FB_WIDTH <= vsz; + FB_HEIGHT <= hsz; + end +end + +reg [1:0] i_fb,o_fb; +always @(posedge CLK_VIDEO) begin + reg old_vbl,old_vs; + old_vbl <= FB_VBL; + old_vs <= VGA_VS; + + if(FB_LL) begin + if(~old_vbl & FB_VBL) o_fb<={1'b0,~i_fb[0]}; + if(~old_vs & VGA_VS) i_fb<={1'b0,~i_fb[0]}; + end + else begin + if(~old_vbl & FB_VBL) o_fb<=buf_next(o_fb,i_fb); + if(~old_vs & VGA_VS) i_fb<=buf_next(i_fb,o_fb); + end +end + +initial begin + fb_en = 0; +end + +reg [2:0] fb_en = 0; +reg [11:0] hsz = 320, vsz = 240; +reg [11:0] bwidth; +reg [22:0] bufsize; +always @(posedge CLK_VIDEO) begin + reg [11:0] hcnt = 0, vcnt = 0; + reg old_vs, old_de; + + if(CE_PIXEL) begin + old_vs <= VGA_VS; + old_de <= VGA_DE; + + hcnt <= hcnt + 1'd1; + if(~old_de & VGA_DE) begin + hcnt <= 1; + vcnt <= vcnt + 1'd1; + end + if(old_de & ~VGA_DE) begin + hsz <= hcnt; + if( do_flip ) bwidth <= hcnt + 2'd3; + end + if(~old_vs & VGA_VS) begin + vsz <= vcnt; + if( !do_flip ) bwidth <= vcnt + 2'd3; + vcnt <= 0; + fb_en <= {fb_en[1:0], ~no_rotate | flip}; + end + if(old_vs & ~VGA_VS) bufsize <= (do_flip ? vsz : hsz ) * stride; + end +end + +wire [13:0] stride = {bwidth[11:2], 4'd0}; + +reg [22:0] ram_addr, next_addr; +reg [31:0] ram_data; +reg ram_wr; +always @(posedge CLK_VIDEO) begin + reg [13:0] hcnt = 0; + reg old_vs, old_de; + + ram_wr <= 0; + if(CE_PIXEL && FB_EN) begin + old_vs <= VGA_VS; + old_de <= VGA_DE; + + if(~old_vs & VGA_VS) begin + next_addr <= + do_flip ? bufsize-3'd4 : + rotate_ccw ? (bufsize - stride) : {vsz-1'd1, 2'b00}; + hcnt <= rotate_ccw ? 3'd4 : {vsz-2'd2, 2'b00}; + end + if(VGA_DE) begin + ram_wr <= 1; + ram_data <= {8'd0,VGA_B,VGA_G,VGA_R}; + ram_addr <= next_addr; + next_addr <= + do_flip ? next_addr-3'd4 : + rotate_ccw ? (next_addr - stride) : (next_addr + stride); + end + if(old_de & ~VGA_DE & ~do_flip) begin + next_addr <= rotate_ccw ? (bufsize - stride + hcnt) : hcnt; + hcnt <= rotate_ccw ? (hcnt + 3'd4) : (hcnt - 3'd4); + end + end +end + +endmodule diff --git a/sys/ascal.vhd b/sys/ascal.vhd index 30d6287..a79f7ec 100644 --- a/sys/ascal.vhd +++ b/sys/ascal.vhd @@ -112,2449 +112,2816 @@ USE ieee.numeric_std.ALL; -- N_BURST : Burst size in bytes. Power of two. ENTITY ascal IS - GENERIC ( - MASK : unsigned(7 DOWNTO 0) :=x"FF"; - RAMBASE : unsigned(31 DOWNTO 0); - RAMSIZE : unsigned(31 DOWNTO 0) := x"0080_0000"; -- =8MB - INTER : boolean := true; - HEADER : boolean := true; - DOWNSCALE : boolean := true; - BYTESWAP : boolean := true; - PALETTE : boolean := true; - PALETTE2 : boolean := true; - FRAC : natural RANGE 4 TO 6 :=4; - OHRES : natural RANGE 1 TO 4096 :=2048; - IHRES : natural RANGE 1 TO 2048 :=2048; - N_DW : natural RANGE 64 TO 128 := 128; - N_AW : natural RANGE 8 TO 32 := 32; - N_BURST : natural := 256 -- 256 bytes per burst - ); - PORT ( - ------------------------------------ - -- Input video - i_r : IN unsigned(7 DOWNTO 0); - i_g : IN unsigned(7 DOWNTO 0); - i_b : IN unsigned(7 DOWNTO 0); - i_hs : IN std_logic; -- H sync - i_vs : IN std_logic; -- V sync - i_fl : IN std_logic; -- Interlaced field - i_de : IN std_logic; -- Display Enable - i_ce : IN std_logic; -- Clock Enable - i_clk : IN std_logic; -- Input clock - - ------------------------------------ - -- Output video - o_r : OUT unsigned(7 DOWNTO 0); - o_g : OUT unsigned(7 DOWNTO 0); - o_b : OUT unsigned(7 DOWNTO 0); - o_hs : OUT std_logic; -- H sync - o_vs : OUT std_logic; -- V sync - o_de : OUT std_logic; -- Display Enable - o_vbl : OUT std_logic; -- V blank - o_ce : IN std_logic; -- Clock Enable - o_clk : IN std_logic; -- Output clock - - -- Border colour R G B - o_border : IN unsigned(23 DOWNTO 0) := x"000000"; - - ------------------------------------ - -- Framebuffer mode - o_fb_ena : IN std_logic :='0'; -- Enable Framebuffer Mode - o_fb_hsize : IN natural RANGE 0 TO 4095 :=0; - o_fb_vsize : IN natural RANGE 0 TO 4095 :=0; - o_fb_format : IN unsigned(5 DOWNTO 0) :="000100"; - o_fb_base : IN unsigned(31 DOWNTO 0) :=x"0000_0000"; - o_fb_stride : IN unsigned(13 DOWNTO 0) :=(OTHERS =>'0'); - - -- Framebuffer palette in 8bpp mode - pal1_clk : IN std_logic :='0'; - pal1_dw : IN unsigned(47 DOWNTO 0) :=x"000000000000"; -- R1 G1 B1 R0 G0 B0 - pal1_dr : OUT unsigned(47 DOWNTO 0) :=x"000000000000"; - pal1_a : IN unsigned(6 DOWNTO 0) :="0000000"; -- Colour index/2 - pal1_wr : IN std_logic :='0'; + GENERIC ( + MASK : unsigned(7 DOWNTO 0) :=x"FF"; + RAMBASE : unsigned(31 DOWNTO 0); + RAMSIZE : unsigned(31 DOWNTO 0) := x"0080_0000"; -- =8MB + INTER : boolean := true; + HEADER : boolean := true; + DOWNSCALE : boolean := true; + BYTESWAP : boolean := true; + PALETTE : boolean := true; + PALETTE2 : boolean := true; + ADAPTIVE : boolean := true; + DOWNSCALE_NN : boolean := false; + FRAC : natural RANGE 4 TO 8 :=4; + OHRES : natural RANGE 1 TO 4096 :=2048; + IHRES : natural RANGE 1 TO 2048 :=2048; + N_DW : natural RANGE 64 TO 128 := 128; + N_AW : natural RANGE 8 TO 32 := 32; + N_BURST : natural := 256 -- 256 bytes per burst + ); + PORT ( + ------------------------------------ + -- Input video + i_r : IN unsigned(7 DOWNTO 0); + i_g : IN unsigned(7 DOWNTO 0); + i_b : IN unsigned(7 DOWNTO 0); + i_hs : IN std_logic; -- H sync + i_vs : IN std_logic; -- V sync + i_fl : IN std_logic; -- Interlaced field + i_de : IN std_logic; -- Display Enable + i_ce : IN std_logic; -- Clock Enable + i_clk : IN std_logic; -- Input clock - pal_n : IN std_logic :='0'; + ------------------------------------ + -- Output video + o_r : OUT unsigned(7 DOWNTO 0); + o_g : OUT unsigned(7 DOWNTO 0); + o_b : OUT unsigned(7 DOWNTO 0); + o_hs : OUT std_logic; -- H sync + o_vs : OUT std_logic; -- V sync + o_de : OUT std_logic; -- Display Enable + o_vbl : OUT std_logic; -- V blank + o_brd : OUT std_logic; -- border enable + o_ce : IN std_logic; -- Clock Enable + o_clk : IN std_logic; -- Output clock - pal2_clk : IN std_logic :='0'; - pal2_dw : IN unsigned(23 DOWNTO 0) :=x"000000"; -- R G B - pal2_dr : OUT unsigned(23 DOWNTO 0) :=x"000000"; - pal2_a : IN unsigned(7 DOWNTO 0) :="00000000"; -- Colour index - pal2_wr : IN std_logic :='0'; - - ------------------------------------ - -- Low lag PLL tuning - o_lltune : OUT unsigned(15 DOWNTO 0); - - ------------------------------------ - -- Input video parameters - iauto : IN std_logic :='1'; -- 1=Autodetect image size 0=Choose window - himin : IN natural RANGE 0 TO 4095 :=0; -- MIN < MAX, MIN >=0, MAX < DISP - himax : IN natural RANGE 0 TO 4095 :=0; - vimin : IN natural RANGE 0 TO 4095 :=0; - vimax : IN natural RANGE 0 TO 4095 :=0; + -- Border colour R G B + o_border : IN unsigned(23 DOWNTO 0) := x"000000"; - -- Detected input image size - i_hdmax : OUT natural RANGE 0 TO 4095; - i_vdmax : OUT natural RANGE 0 TO 4095; - - -- Output video parameters - run : IN std_logic :='1'; -- 1=Enable output image. 0=No image - freeze : IN std_logic :='0'; -- 1=Disable framebuffer writes - mode : IN unsigned(4 DOWNTO 0); - -- SYNC |_________________________/"""""""""\_______| - -- DE |""""""""""""""""""\________________________| - -- RGB | <#IMAGE#> ^HDISP | - -- ^HMIN ^HMAX ^HSSTART ^HSEND ^HTOTAL - htotal : IN natural RANGE 0 TO 4095; - hsstart : IN natural RANGE 0 TO 4095; - hsend : IN natural RANGE 0 TO 4095; - hdisp : IN natural RANGE 0 TO 4095; - hmin : IN natural RANGE 0 TO 4095; - hmax : IN natural RANGE 0 TO 4095; -- 0 <= hmin < hmax < hdisp - vtotal : IN natural RANGE 0 TO 4095; - vsstart : IN natural RANGE 0 TO 4095; - vsend : IN natural RANGE 0 TO 4095; - vdisp : IN natural RANGE 0 TO 4095; - vmin : IN natural RANGE 0 TO 4095; - vmax : IN natural RANGE 0 TO 4095; -- 0 <= vmin < vmax < vdisp - - -- Scaler format. 00=16bpp 565, 01=24bpp 10=32bpp - format : IN unsigned(1 DOWNTO 0) :="01"; - - ------------------------------------ - -- Polyphase filter coefficients - -- Order : - -- [Horizontal] [Vertical] - -- [0]...[2**FRAC-1] - -- [-1][0][1][2] - poly_clk : IN std_logic; - poly_dw : IN unsigned(8 DOWNTO 0); - poly_a : IN unsigned(FRAC+2 DOWNTO 0); - poly_wr : IN std_logic; - - ------------------------------------ - -- Avalon - avl_clk : IN std_logic; -- Avalon clock - avl_waitrequest : IN std_logic; - avl_readdata : IN std_logic_vector(N_DW-1 DOWNTO 0); - avl_readdatavalid : IN std_logic; - avl_burstcount : OUT std_logic_vector(7 DOWNTO 0); - avl_writedata : OUT std_logic_vector(N_DW-1 DOWNTO 0); - avl_address : OUT std_logic_vector(N_AW-1 DOWNTO 0); - avl_write : OUT std_logic; - avl_read : OUT std_logic; - avl_byteenable : OUT std_logic_vector(N_DW/8-1 DOWNTO 0); - - ------------------------------------ - reset_na : IN std_logic - ); + ------------------------------------ + -- Framebuffer mode + o_fb_ena : IN std_logic :='0'; -- Enable Framebuffer Mode + o_fb_hsize : IN natural RANGE 0 TO 4095 :=0; + o_fb_vsize : IN natural RANGE 0 TO 4095 :=0; + o_fb_format : IN unsigned(5 DOWNTO 0) :="000100"; + o_fb_base : IN unsigned(31 DOWNTO 0) :=x"0000_0000"; + o_fb_stride : IN unsigned(13 DOWNTO 0) :=(OTHERS =>'0'); + + -- Framebuffer palette in 8bpp mode + pal1_clk : IN std_logic :='0'; + pal1_dw : IN unsigned(47 DOWNTO 0) :=x"000000000000"; -- R1 G1 B1 R0 G0 B0 + pal1_dr : OUT unsigned(47 DOWNTO 0) :=x"000000000000"; + pal1_a : IN unsigned(6 DOWNTO 0) :="0000000"; -- Colour index/2 + pal1_wr : IN std_logic :='0'; + + pal_n : IN std_logic :='0'; + + pal2_clk : IN std_logic :='0'; + pal2_dw : IN unsigned(23 DOWNTO 0) :=x"000000"; -- R G B + pal2_dr : OUT unsigned(23 DOWNTO 0) :=x"000000"; + pal2_a : IN unsigned(7 DOWNTO 0) :="00000000"; -- Colour index + pal2_wr : IN std_logic :='0'; + + ------------------------------------ + -- Low lag PLL tuning + o_lltune : OUT unsigned(15 DOWNTO 0); + + ------------------------------------ + -- Input video parameters + iauto : IN std_logic :='1'; -- 1=Autodetect image size 0=Choose window + himin : IN natural RANGE 0 TO 4095 :=0; -- MIN < MAX, MIN >=0, MAX < DISP + himax : IN natural RANGE 0 TO 4095 :=0; + vimin : IN natural RANGE 0 TO 4095 :=0; + vimax : IN natural RANGE 0 TO 4095 :=0; + + -- Detected input image size + i_hdmax : OUT natural RANGE 0 TO 4095; + i_vdmax : OUT natural RANGE 0 TO 4095; + + -- Output video parameters + run : IN std_logic :='1'; -- 1=Enable output image. 0=No image + freeze : IN std_logic :='0'; -- 1=Disable framebuffer writes + mode : IN unsigned(4 DOWNTO 0); + -- SYNC |_________________________/"""""""""\_______| + -- DE |""""""""""""""""""\________________________| + -- RGB | <#IMAGE#> ^HDISP | + -- ^HMIN ^HMAX ^HSSTART ^HSEND ^HTOTAL + htotal : IN natural RANGE 0 TO 4095; + hsstart : IN natural RANGE 0 TO 4095; + hsend : IN natural RANGE 0 TO 4095; + hdisp : IN natural RANGE 0 TO 4095; + hmin : IN natural RANGE 0 TO 4095; + hmax : IN natural RANGE 0 TO 4095; -- 0 <= hmin < hmax < hdisp + vtotal : IN natural RANGE 0 TO 4095; + vsstart : IN natural RANGE 0 TO 4095; + vsend : IN natural RANGE 0 TO 4095; + vdisp : IN natural RANGE 0 TO 4095; + vmin : IN natural RANGE 0 TO 4095; + vmax : IN natural RANGE 0 TO 4095; -- 0 <= vmin < vmax < vdisp + vrr : IN std_logic := '0'; + vrrmax : IN natural RANGE 0 TO 4095 := 0; + swblack : IN std_logic := '0'; -- will output 3 black frame on every resolution switch + + -- Scaler format. 00=16bpp 565, 01=24bpp 10=32bpp + format : IN unsigned(1 DOWNTO 0) :="01"; + + ------------------------------------ + -- Polyphase filter coefficients + -- Order : + -- [Horizontal] [Vertical] [Horizontal2] [Vertical2] + -- [0]...[2**FRAC-1] + -- [-1][0][1][2] + poly_clk : IN std_logic; + poly_dw : IN unsigned(9 DOWNTO 0); + poly_a : IN unsigned(FRAC+3 DOWNTO 0); + poly_wr : IN std_logic; + + ------------------------------------ + -- Avalon + avl_clk : IN std_logic; -- Avalon clock + avl_waitrequest : IN std_logic; + avl_readdata : IN std_logic_vector(N_DW-1 DOWNTO 0); + avl_readdatavalid : IN std_logic; + avl_burstcount : OUT std_logic_vector(7 DOWNTO 0); + avl_writedata : OUT std_logic_vector(N_DW-1 DOWNTO 0); + avl_address : OUT std_logic_vector(N_AW-1 DOWNTO 0); + avl_write : OUT std_logic; + avl_read : OUT std_logic; + avl_byteenable : OUT std_logic_vector(N_DW/8-1 DOWNTO 0); + + ------------------------------------ + reset_na : IN std_logic + ); BEGIN - ASSERT N_DW=64 OR N_DW=128 REPORT "DW" SEVERITY failure; - + ASSERT N_DW=64 OR N_DW=128 REPORT "DW" SEVERITY failure; + END ENTITY ascal; --############################################################################## ARCHITECTURE rtl OF ascal IS - - CONSTANT MASK_NEAREST : natural :=0; - CONSTANT MASK_BILINEAR : natural :=1; - CONSTANT MASK_SHARP_BILINEAR : natural :=2; - CONSTANT MASK_BICUBIC : natural :=3; - CONSTANT MASK_POLY : natural :=4; - - ---------------------------------------------------------- - FUNCTION ilog2 (CONSTANT v : natural) RETURN natural IS - VARIABLE r : natural := 1; - VARIABLE n : natural := 0; - BEGIN - WHILE v>r LOOP - n:=n+1; - r:=r*2; - END LOOP; - RETURN n; - END FUNCTION ilog2; - FUNCTION to_std_logic (a : boolean) RETURN std_logic IS - BEGIN - IF a THEN RETURN '1'; - ELSE RETURN '0'; - END IF; - END FUNCTION to_std_logic; - - ---------------------------------------------------------- - CONSTANT NB_BURST : natural :=ilog2(N_BURST); - CONSTANT NB_LA : natural :=ilog2(N_DW/8); -- Low address bits - CONSTANT BLEN : natural :=N_BURST / N_DW * 8; -- Burst length - - ---------------------------------------------------------- - TYPE arr_dw IS ARRAY (natural RANGE <>) OF unsigned(N_DW-1 DOWNTO 0); - - TYPE type_pix IS RECORD - r,g,b : unsigned(7 DOWNTO 0); -- 0.8 - END RECORD; - TYPE arr_pix IS ARRAY (natural RANGE <>) OF type_pix; - ATTRIBUTE ramstyle : string; - - SUBTYPE uint12 IS natural RANGE 0 TO 4095; - SUBTYPE uint13 IS natural RANGE 0 TO 8191; - - TYPE arr_uv48 IS ARRAY (natural RANGE <>) OF unsigned(47 DOWNTO 0); - TYPE arr_uv24 IS ARRAY (natural RANGE <>) OF unsigned(23 DOWNTO 0); - TYPE arr_uv36 IS ARRAY (natural RANGE <>) OF unsigned(35 DOWNTO 0); - TYPE arr_int9 IS ARRAY (natural RANGE <>) OF integer RANGE -256 TO 255; - TYPE arr_uint12 IS ARRAY (natural RANGE <>) OF uint12; - ---------------------------------------------------------- - -- Input image - SIGNAL i_pvs,i_pfl,i_pde,i_pce : std_logic; - SIGNAL i_ppix : type_pix; - SIGNAL i_freeze : std_logic; - SIGNAL i_count : unsigned(2 DOWNTO 0); - SIGNAL i_hsize,i_hmin,i_hmax,i_hcpt : uint12; - SIGNAL i_hrsize,i_vrsize : uint12; - SIGNAL i_himax,i_vimax : uint12; - SIGNAL i_vsize,i_vmaxmin,i_vmin,i_vmax,i_vcpt : uint12; - SIGNAL i_iauto : std_logic; - SIGNAL i_mode : unsigned(4 DOWNTO 0); - SIGNAL i_format : unsigned(1 DOWNTO 0); - SIGNAL i_ven,i_sof : std_logic; - SIGNAL i_wr : std_logic; - SIGNAL i_divstart,i_divrun : std_logic; - SIGNAL i_de_pre,i_vs_pre,i_fl_pre : std_logic; - SIGNAL i_de_delay : natural RANGE 0 TO 31; - SIGNAL i_intercnt : natural RANGE 0 TO 3; - SIGNAL i_inter,i_half,i_flm : std_logic; - SIGNAL i_write,i_wreq,i_alt,i_line,i_wline,i_wline_mem : std_logic; - SIGNAL i_walt,i_walt_mem,i_wreq_mem : std_logic; - SIGNAL i_wdelay : natural RANGE 0 TO 7; - SIGNAL i_push,i_pushend,i_pushend2 : std_logic; - SIGNAL i_eol : std_logic; - SIGNAL i_pushhead,i_pushhead2,i_pushhead3 : std_logic; - SIGNAL i_hburst,i_hbcpt : natural RANGE 0 TO 31; - SIGNAL i_shift : unsigned(0 TO 119) := (OTHERS =>'0'); - SIGNAL i_head : unsigned(127 DOWNTO 0); - SIGNAL i_acpt : natural RANGE 0 TO 15; - SIGNAL i_dpram : arr_dw(0 TO BLEN*2-1); - ATTRIBUTE ramstyle OF i_dpram : SIGNAL IS "no_rw_check"; - SIGNAL i_endframe0,i_endframe1,i_vss : std_logic; - SIGNAL i_wad : natural RANGE 0 TO BLEN*2-1; - SIGNAL i_dw : unsigned(N_DW-1 DOWNTO 0); - SIGNAL i_adrs,i_adrsi,i_wadrs,i_wadrs_mem : unsigned(31 DOWNTO 0); - SIGNAL i_reset_na : std_logic; - SIGNAL i_hnp,i_vnp : std_logic; - SIGNAL i_mem : arr_pix(0 TO IHRES-1); -- Downscale line buffer - ATTRIBUTE ramstyle OF i_mem : SIGNAL IS "no_rw_check"; - SIGNAL i_ohsize,i_ovsize : uint12; - SIGNAL i_vdivi : unsigned(12 DOWNTO 0); - SIGNAL i_vdivr : unsigned(24 DOWNTO 0); - SIGNAL i_div : unsigned(16 DOWNTO 0); - SIGNAL i_dir : unsigned(11 DOWNTO 0); - SIGNAL i_h_frac,i_v_frac : unsigned(11 DOWNTO 0); - SIGNAL i_hacc,i_vacc : uint13; - SIGNAL i_hdown,i_vdown : std_logic; - SIGNAL i_divcpt : natural RANGE 0 TO 36; - SIGNAL i_lwad,i_lrad : natural RANGE 0 TO OHRES-1; - SIGNAL i_lwr,i_bil : std_logic; - SIGNAL i_ldw,i_ldrm : type_pix; - SIGNAL i_hpixp,i_hpix0,i_hpix1,i_hpix2,i_hpix3,i_hpix4 : type_pix; - SIGNAL i_hpix,i_pix : type_pix; - SIGNAL i_hnp1,i_hnp2,i_hnp3,i_hnp4 : std_logic; - SIGNAL i_ven1,i_ven2,i_ven3,i_ven4,i_ven5,i_ven6 : std_logic; - - ---------------------------------------------------------- - -- Avalon - TYPE type_avl_state IS (sIDLE,sWRITE,sREAD); - SIGNAL avl_state : type_avl_state; - SIGNAL avl_write_i,avl_write_sync,avl_write_sync2 : std_logic; - SIGNAL avl_read_i,avl_read_sync,avl_read_sync2 : std_logic; - SIGNAL avl_read_pulse,avl_write_pulse : std_logic; - SIGNAL avl_read_sr,avl_write_sr,avl_read_clr,avl_write_clr : std_logic; - SIGNAL avl_rad,avl_rad_c,avl_wad : natural RANGE 0 TO 2*BLEN-1; - SIGNAL avl_walt,avl_wline,avl_rline : std_logic; - SIGNAL avl_dw,avl_dr : unsigned(N_DW-1 DOWNTO 0); - SIGNAL avl_wr : std_logic; - SIGNAL avl_readdataack,avl_readack : std_logic; - SIGNAL avl_radrs,avl_wadrs : unsigned(31 DOWNTO 0); - SIGNAL avl_i_offset0,avl_o_offset0 : unsigned(31 DOWNTO 0); - SIGNAL avl_i_offset1,avl_o_offset1 : unsigned(31 DOWNTO 0); - SIGNAL avl_reset_na : std_logic; - SIGNAL avl_o_vs_sync,avl_o_vs : std_logic; - SIGNAL avl_fb_ena : std_logic; - - FUNCTION buf_next(a,b : natural RANGE 0 TO 2) RETURN natural IS - BEGIN - IF (a=0 AND b=1) OR (a=1 AND b=0) THEN RETURN 2; END IF; - IF (a=1 AND b=2) OR (a=2 AND b=1) THEN RETURN 0; END IF; - RETURN 1; - END FUNCTION; - FUNCTION buf_offset(b : natural RANGE 0 TO 2; - base : unsigned(31 DOWNTO 0); - size : unsigned(31 DOWNTO 0)) RETURN unsigned IS - BEGIN - IF b=1 THEN RETURN base+size; END IF; - IF b=2 THEN RETURN base+(size(30 DOWNTO 0) & '0'); END IF; - RETURN base; - END FUNCTION; - - ---------------------------------------------------------- - -- Output - SIGNAL o_run : std_logic; - SIGNAL o_mode,o_hmode,o_vmode : unsigned(4 DOWNTO 0); - SIGNAL o_format : unsigned(5 DOWNTO 0); - SIGNAL o_fb_pal_dr : unsigned(23 DOWNTO 0); - SIGNAL o_fb_pal_dr2 : unsigned(23 DOWNTO 0); - SIGNAL o_fb_pal_dr_x2 : unsigned(47 DOWNTO 0); - SIGNAL pal_idx: unsigned(7 DOWNTO 0); - SIGNAL pal_idx_lsb: std_logic; - SIGNAL pal1_mem : arr_uv48(0 TO 127); - SIGNAL pal2_mem : arr_uv24(0 TO 255); - ATTRIBUTE ramstyle of pal1_mem : signal is "no_rw_check"; - ATTRIBUTE ramstyle of pal2_mem : signal is "no_rw_check"; - SIGNAL o_htotal,o_hsstart,o_hsend : uint12; - SIGNAL o_hmin,o_hmax,o_hdisp : uint12; - SIGNAL o_hsize,o_vsize : uint12; - SIGNAL o_vtotal,o_vsstart,o_vsend : uint12; - SIGNAL o_vmin,o_vmax,o_vdisp : uint12; - SIGNAL o_divcpt : natural RANGE 0 TO 36; - SIGNAL o_iendframe0,o_iendframe02,o_iendframe1,o_iendframe12 : std_logic; - SIGNAL o_bufup0,o_bufup1,o_inter : std_logic; - SIGNAL o_ibuf0,o_ibuf1,o_obuf0,o_obuf1 : natural RANGE 0 TO 2; - TYPE enum_o_state IS (sDISP,sHSYNC,sREAD,sWAITREAD); - SIGNAL o_state : enum_o_state; - TYPE enum_o_copy IS (sWAIT,sSHIFT,sCOPY); - SIGNAL o_copy : enum_o_copy; - SIGNAL o_pshift : natural RANGE 0 TO 15; - SIGNAL o_readack,o_readack_sync,o_readack_sync2 : std_logic; - SIGNAL o_readdataack,o_readdataack_sync,o_readdataack_sync2 : std_logic; - SIGNAL o_copyv : unsigned(0 TO 8); - SIGNAL o_adrs : unsigned(31 DOWNTO 0); -- Avalon address - SIGNAL o_adrs_pre : natural RANGE 0 TO 2**23-1; - SIGNAL o_stride : unsigned(13 DOWNTO 0); - SIGNAL o_adrsa,o_adrsb,o_rline : std_logic; - SIGNAL o_ad,o_ad1,o_ad2,o_ad3 : natural RANGE 0 TO 2*BLEN-1; - SIGNAL o_adturn : std_logic; - SIGNAL o_dr : unsigned(N_DW-1 DOWNTO 0); - SIGNAL o_shift : unsigned(0 TO N_DW+15); - SIGNAL o_sh,o_sh1,o_sh2,o_sh3,o_sh4 : std_logic; - SIGNAL o_reset_na : std_logic; - SIGNAL o_dpram : arr_dw(0 TO BLEN*2-1); - ATTRIBUTE ramstyle OF o_dpram : SIGNAL IS "no_rw_check"; - SIGNAL o_line0,o_line1,o_line2,o_line3 : arr_pix(0 TO OHRES-1); - ATTRIBUTE ramstyle OF o_line0 : SIGNAL IS "no_rw_check"; - ATTRIBUTE ramstyle OF o_line1 : SIGNAL IS "no_rw_check"; - ATTRIBUTE ramstyle OF o_line2 : SIGNAL IS "no_rw_check"; - ATTRIBUTE ramstyle OF o_line3 : SIGNAL IS "no_rw_check"; - SIGNAL o_wadl,o_radl : natural RANGE 0 TO OHRES-1; - SIGNAL o_ldw,o_ldr0,o_ldr1,o_ldr2,o_ldr3 : type_pix; - SIGNAL o_wr : unsigned(3 DOWNTO 0); - SIGNAL o_hcpt,o_vcpt,o_vcpt_pre,o_vcpt_pre2,o_vcpt_pre3 : uint12; - SIGNAL o_ihsize,o_ihsizem,o_ivsize : uint12; - SIGNAL o_ihsize_temp, o_ihsize_temp2 : natural RANGE 0 TO 32767; + CONSTANT MASK_NEAREST : natural :=0; + CONSTANT MASK_BILINEAR : natural :=1; + CONSTANT MASK_SHARP_BILINEAR : natural :=2; + CONSTANT MASK_BICUBIC : natural :=3; + CONSTANT MASK_POLY : natural :=4; - SIGNAL o_vfrac,o_hfrac,o_hfrac1,o_hfrac2,o_hfrac3,o_hfrac4 : unsigned(11 DOWNTO 0); - SIGNAL o_hacc,o_hacc_ini,o_hacc_next,o_vacc,o_vacc_next,o_vacc_ini : natural RANGE 0 TO 4*OHRES-1; - SIGNAL o_hsv,o_vsv,o_dev,o_pev,o_end : unsigned(0 TO 5); - SIGNAL o_hsp,o_vss : std_logic; - SIGNAL o_read,o_read_pre : std_logic; - SIGNAL o_readlev,o_copylev : natural RANGE 0 TO 2; - SIGNAL o_hburst,o_hbcpt : natural RANGE 0 TO 31; - SIGNAL o_fload : natural RANGE 0 TO 3; - SIGNAL o_acpt,o_acpt1,o_acpt2,o_acpt3,o_acpt4 : natural RANGE 0 TO 15; -- Alternance pixels FIFO - SIGNAL o_dshi : natural RANGE 0 TO 3; - SIGNAL o_first,o_last,o_last1,o_last2,o_last3 : std_logic; - SIGNAL o_lastt1,o_lastt2,o_lastt3 : std_logic; - SIGNAL o_alt,o_altx : unsigned(3 DOWNTO 0); - SIGNAL o_hdown,o_vdown : std_logic; - SIGNAL o_primv,o_lastv,o_bibv : unsigned(0 TO 2); - TYPE arr_uint4 IS ARRAY (natural RANGE <>) OF natural RANGE 0 TO 15; - SIGNAL o_off : arr_uint4(0 TO 2); - SIGNAL o_bibu : std_logic :='0'; - SIGNAL o_dcptv : arr_uint12(1 TO 8); - SIGNAL o_dcpt : uint12; - SIGNAL o_hpixs,o_hpix0,o_hpix1,o_hpix2,o_hpix3 : type_pix; - SIGNAL o_hpixq,o_vpixq,o_vpixq1 : arr_pix(0 TO 3); - - SIGNAL o_vpe : std_logic; - SIGNAL o_div,o_div2 : unsigned(18 DOWNTO 0); --uint12; - SIGNAL o_dir,o_dir2 : unsigned(11 DOWNTO 0); - SIGNAL o_vdivi : unsigned(12 DOWNTO 0); - SIGNAL o_vdivr : unsigned(24 DOWNTO 0); - SIGNAL o_divstart : std_logic; - SIGNAL o_divrun : std_logic; - SIGNAL o_hacpt,o_vacpt : unsigned(11 DOWNTO 0); - - ----------------------------------------------------------------------------- - FUNCTION shift_ishift(shift : unsigned(0 TO 119); - pix : type_pix; - format : unsigned(1 DOWNTO 0)) RETURN unsigned IS - BEGIN - CASE format IS - WHEN "01" => -- 24bpp - RETURN shift(24 TO 119) & pix.r & pix.g & pix.b; - WHEN "10" => -- 32bpp - RETURN shift(32 TO 119) & pix.r & pix.g & pix.b & x"00"; - WHEN OTHERS => -- 16bpp 565 - RETURN shift(16 TO 119) & - pix.g(4 DOWNTO 2) & pix.r(7 DOWNTO 3) & - pix.b(7 DOWNTO 3) & pix.g(7 DOWNTO 5); - END CASE; - END FUNCTION; - - FUNCTION shift_ipack(i_dw : unsigned(N_DW-1 DOWNTO 0); - acpt : natural RANGE 0 TO 15; - shift : unsigned(0 TO 119); - pix : type_pix; - format : unsigned(1 DOWNTO 0)) RETURN unsigned IS - VARIABLE dw : unsigned(N_DW-1 DOWNTO 0); - BEGIN - dw:=i_dw; - CASE format IS - WHEN "01" => -- 24bpp - IF N_DW=128 THEN - IF acpt=5 THEN dw:=shift(0 TO 119) & pix.r; - ELSIF acpt=10 THEN dw:=shift(8 TO 119) & pix.r & pix.g; - ELSIF acpt=15 THEN dw:=shift(16 TO 119) & pix.r & pix.g & pix.b; - END IF; - ELSE -- N_DW=64 - IF (acpt MOD 8)=2 THEN dw:=shift(72 TO 119) & pix.r & pix.g; - ELSIF (acpt MOD 8)=5 THEN dw:=shift(64 TO 119) & pix.r; - ELSIF (acpt MOD 8)=7 THEN dw:=shift(80 TO 119) & pix.r & pix.g & pix.b; - END IF; - END IF; - WHEN "10" => -- 32bpp - IF (N_DW=128 AND (acpt MOD 4)=3) OR (N_DW=64 AND (acpt MOD 8)=7) THEN - dw:=shift(128-N_DW+24 TO 119) & pix.r & pix.g & pix.b & x"00"; - END IF; - WHEN OTHERS => -- 16bpp 565 - IF (N_DW=128 AND (acpt MOD 8)=7) OR (N_DW=64 AND (acpt MOD 4)=3) THEN - dw:=shift(128-N_DW+8 TO 119) & pix.g(4 DOWNTO 2) & pix.r(7 DOWNTO 3) & - pix.b(7 DOWNTO 3) & pix.g(7 DOWNTO 5); - END IF; - END CASE; - RETURN dw; - END FUNCTION; - - FUNCTION shift_inext (acpt : natural RANGE 0 TO 15; - format : unsigned(1 DOWNTO 0)) RETURN boolean IS - BEGIN - CASE format IS - WHEN "01" => -- 24bpp - RETURN (N_DW=128 AND (acpt=5 OR acpt=10 OR acpt=15)) OR - (N_DW=64 AND ((acpt MOD 8)=2 OR (acpt MOD 8)=5 OR (acpt MOD 8)=7)); - WHEN "10" => -- 32bpp - RETURN (N_DW=128 AND ((acpt MOD 4)=3)) OR - (N_DW=64 AND ((acpt MOD 2)=1)); - WHEN OTHERS => -- 16bpp - RETURN (N_DW=128 AND ((acpt MOD 8)=7)) OR - (N_DW=64 AND ((acpt MOD 4)=3)); - END CASE; - END FUNCTION; - - FUNCTION shift_opack(acpt : natural RANGE 0 TO 15; - shift : unsigned(0 TO N_DW+15); - dr : unsigned(N_DW-1 DOWNTO 0); - format : unsigned(5 DOWNTO 0)) RETURN unsigned IS - VARIABLE shift_v : unsigned(0 TO N_DW+15); - BEGIN - CASE format(2 DOWNTO 0) IS - WHEN "011" => -- 8bpp - IF (N_DW=128 AND acpt=0) OR (N_DW=64 AND (acpt MOD 8)=0) THEN - shift_v:=dr & dr(15 DOWNTO 0); - ELSE - shift_v:=shift(8 TO N_DW+15) & dr(7 DOWNTO 0); - END IF; - - WHEN "100" => -- 16bpp - IF (N_DW=128 AND (acpt MOD 8)=0) OR (N_DW=64 AND (acpt MOD 4)=0) THEN - shift_v:=dr & dr(15 DOWNTO 0); - ELSE - shift_v:=shift(16 TO N_DW+15) & dr(15 DOWNTO 0); - END IF; - - WHEN "101" => -- 24bpp - IF N_DW=128 THEN - IF acpt=0 THEN - shift_v:=dr & dr(15 DOWNTO 0); - ELSIF acpt=5 THEN - shift_v:=shift(24 TO 31) & dr & dr(7 DOWNTO 0); - ELSIF acpt=10 THEN - shift_v:=shift(24 TO 39) & dr; - ELSE - shift_v:=shift(24 TO N_DW+15) & dr(23 DOWNTO 0); - END IF; - ELSE -- N_DW=64 - IF (acpt MOD 8)=0 THEN - shift_v:=dr & dr(15 DOWNTO 0); - ELSIF (acpt MOD 8)=2 THEN - shift_v:=shift(24 TO 39) & dr; - ELSIF (acpt MOD 8)=5 THEN - shift_v:=shift(24 TO 31) & dr & dr(7 DOWNTO 0); - ELSE - shift_v:=shift(24 TO N_DW+15) & dr(23 DOWNTO 0); - END IF; - END IF; - WHEN OTHERS => -- 32bpp - IF (N_DW=128 AND (acpt MOD 4)=0) OR (N_DW=64 AND (acpt MOD 2)=0) THEN - shift_v:=dr & dr(15 DOWNTO 0); - ELSE - shift_v:=shift(32 TO N_DW+15) & dr(31 DOWNTO 0); - END IF; - END CASE; - RETURN shift_v; - END FUNCTION; - - FUNCTION shift_onext (acpt : natural RANGE 0 TO 15; - format : unsigned(5 DOWNTO 0)) RETURN boolean IS - BEGIN - CASE format(2 DOWNTO 0) IS - WHEN "011" => -- 8bpp - RETURN (N_DW=128 AND acpt=0) OR - (N_DW=64 AND ((acpt MOD 8)=0)); - WHEN "100" => -- 16bpp - RETURN (N_DW=128 AND ((acpt MOD 8)=0)) OR - (N_DW=64 AND ((acpt MOD 4)=0)); - WHEN "101" => -- 24bpp - RETURN (N_DW=128 AND (acpt=0 OR acpt=5 OR acpt=10)) OR - (N_DW=64 AND ((acpt MOD 8)=0 OR (acpt MOD 8)=2 OR (acpt MOD 8)=5)); - WHEN OTHERS => -- 32bpp - RETURN (N_DW=128 AND ((acpt MOD 4)=0)) OR - (N_DW=64 AND ((acpt MOD 2)=0)); - END CASE; - END FUNCTION; - - FUNCTION shift_opix (shift : unsigned(0 TO N_DW+15); - format : unsigned(5 DOWNTO 0)) RETURN type_pix IS - BEGIN - CASE format(3 DOWNTO 0) IS - WHEN "0100" => -- 16bpp 565 - RETURN (b=>shift(8 TO 12) & shift(8 TO 10), - g=>shift(13 TO 15) & shift(0 TO 2) & shift(13 TO 14), - r=>shift(3 TO 7) & shift(3 TO 5)); - WHEN "1100" => -- 16bpp 1555 - RETURN (b=>shift(9 TO 13) & shift(9 TO 11), - g=>shift(14 TO 15) & shift(0 TO 2) & shift(14 TO 15) & shift(0), - r=>shift(3 TO 7) & shift(3 TO 5)); - WHEN "0101" | "0110" => -- 24bpp / 32bpp - RETURN (r=>shift(0 TO 7),g=>shift(8 TO 15),b=>shift(16 TO 23)); - - WHEN OTHERS => - RETURN (r=>shift(0 TO 7),g=>shift(8 TO 15),b=>shift(16 TO 23)); - - END CASE; - END FUNCTION; - - FUNCTION pixoffset(adrs : unsigned(31 DOWNTO 0); - format : unsigned (5 DOWNTO 0)) RETURN natural IS - BEGIN - CASE format(2 DOWNTO 0) IS - WHEN "011" => -- 8bbp - RETURN to_integer(adrs(NB_LA-1 DOWNTO 0)); - WHEN "100" => -- 16bpp 565 - RETURN to_integer(adrs(NB_LA-1 DOWNTO 1)); - WHEN OTHERS => -- 32bpp - RETURN to_integer(adrs(NB_LA-1 DOWNTO 2)); - END CASE; - END FUNCTION; - - FUNCTION swap(d : unsigned(N_DW-1 DOWNTO 0)) RETURN unsigned IS - VARIABLE e : unsigned(N_DW-1 DOWNTO 0); - BEGIN - IF BYTESWAP THEN - FOR i IN 0 TO N_DW/8-1 LOOP - e(i*8+7 DOWNTO i*8):=d(N_DW-i*8-1 DOWNTO N_DW-i*8-8); - END LOOP; - RETURN e; - ELSE - RETURN d; - END IF; - END FUNCTION swap; - - ----------------------------------------------------------------------------- - FUNCTION altx (a : unsigned(1 DOWNTO 0)) RETURN unsigned IS - BEGIN - CASE a IS - WHEN "00" => RETURN "0001"; - WHEN "01" => RETURN "0010"; - WHEN "10" => RETURN "0100"; - WHEN OTHERS => RETURN "1000"; - END CASE; - END FUNCTION; - - ----------------------------------------------------------------------------- - FUNCTION bound(a : unsigned; - s : natural) RETURN unsigned IS - BEGIN - IF a(a'left)='1' THEN - RETURN x"00"; - ELSIF a(a'left DOWNTO s)/=0 THEN - RETURN x"FF"; - ELSE - RETURN a(s-1 DOWNTO s-8); - END IF; - END FUNCTION bound; - - ----------------------------------------------------------------------------- - -- Nearest - FUNCTION near_frac(f : unsigned) RETURN unsigned IS - VARIABLE x : unsigned(FRAC-1 DOWNTO 0); - BEGIN - x:=(OTHERS =>f(f'left)); - RETURN x; - END FUNCTION; - - SIGNAL o_h_frac2,o_v_frac : unsigned(FRAC-1 DOWNTO 0); - SIGNAL o_h_bil_pix,o_v_bil_pix : type_pix; - - ----------------------------------------------------------------------------- - -- Nearest + Bilinear + Sharp Bilinear - FUNCTION bil_frac(f : unsigned) RETURN unsigned IS - BEGIN - RETURN f(f'left DOWNTO f'left+1-FRAC); - END FUNCTION; - - TYPE type_bil_t IS RECORD - r,g,b : unsigned(8+FRAC DOWNTO 0); - END RECORD; - FUNCTION bil_calc(f : unsigned(FRAC-1 DOWNTO 0); - p : arr_pix(0 TO 3)) RETURN type_bil_t IS - VARIABLE fp,fn : unsigned(FRAC DOWNTO 0); - VARIABLE u : unsigned(8+FRAC DOWNTO 0); - VARIABLE x : type_bil_t; - CONSTANT Z : unsigned(FRAC-1 DOWNTO 0):=(OTHERS =>'0'); - BEGIN - fp:='0' & f; - fn:=('1' & Z) - fp; - u:=p(2).r * fp + p(1).r * fn; - x.r:=u; - u:=p(2).g * fp + p(1).g * fn; - x.g:=u; - u:=p(2).b * fp + p(1).b * fn; - x.b:=u; - RETURN x; - END FUNCTION; - SIGNAL o_h_bil_t,o_v_bil_t : type_bil_t; - SIGNAL i_h_bil_t : type_bil_t; - - ----------------------------------------------------------------------------- - -- Sharp Bilinear - -- <0.5 : x*x*x*4 - -- >0.5 : 1 - (1-x)*(1-x)*(1-x)*4 - - TYPE type_sbil_tt IS RECORD - f : unsigned(FRAC-1 DOWNTO 0); - s : unsigned(FRAC-1 DOWNTO 0); - END RECORD; - - SIGNAL o_h_sbil_t,o_v_sbil_t : type_sbil_tt; - - FUNCTION sbil_frac1(f : unsigned(11 DOWNTO 0)) RETURN type_sbil_tt IS - VARIABLE u : unsigned(FRAC-1 DOWNTO 0); - VARIABLE v : unsigned(2*FRAC-1 DOWNTO 0); - VARIABLE x : type_sbil_tt; - BEGIN - IF f(11)='0' THEN - u:=f(11 DOWNTO 12-FRAC); - ELSE - u:=NOT f(11 DOWNTO 12-FRAC); - END IF; - v:=u*u; - x.f:=u; - x.s:=v(2*FRAC-2 DOWNTO FRAC-1); - RETURN x; - END FUNCTION; - - FUNCTION sbil_frac2(f : unsigned(11 DOWNTO 0); - t : type_sbil_tt) RETURN unsigned IS - VARIABLE v : unsigned(2*FRAC-1 DOWNTO 0); - BEGIN - v:=t.f*t.s; - IF f(11)='0' THEN - RETURN v(2*FRAC-2 DOWNTO FRAC-1); - ELSE - RETURN NOT v(2*FRAC-2 DOWNTO FRAC-1); - END IF; - END FUNCTION; - - ----------------------------------------------------------------------------- - -- Bicubic - TYPE type_bic_abcd IS RECORD - a : unsigned(7 DOWNTO 0); -- 0.8 - b : signed(8 DOWNTO 0); -- 0.9 - c : signed(11 DOWNTO 0); -- 3.9 - d : signed(10 DOWNTO 0); -- 2.9 - xx : signed(8 DOWNTO 0); -- X.X 1.8 - END RECORD; - TYPE type_bic_pix_abcd IS RECORD - r,g,b : type_bic_abcd; - END RECORD; - TYPE type_bic_tt1 IS RECORD -- Intermediate result - r_bx,g_bx,b_bx : signed(8 DOWNTO 0); -- B.X 1.8 - r_cxx,g_cxx,b_cxx : signed(11 DOWNTO 0); -- C.XX 3.9 - r_dxx,g_dxx,b_dxx : signed(10 DOWNTO 0); -- D.XX 2.9 - END RECORD; - TYPE type_bic_tt2 IS RECORD -- Intermediate result - r_abxcxx,g_abxcxx,b_abxcxx : signed(9 DOWNTO 0); -- A + B.X + C.XX 2.8 - r_dxxx,g_dxxx,b_dxxx : signed(9 DOWNTO 0); -- D.X.X.X 2.8 - END RECORD; - - ---------------------------------------------------------- - -- Y = A + B.X + C.X.X + D.X.X.X = A + X.(B + X.(C + X.D)) - -- A = Y(0) 0 .. 1 unsigned - -- B = Y(1)/2 - Y(-1)/2 -1/2 .. +1/2 signed - -- C = Y(-1) - 5*Y(0)/2 + 2*Y(1) - Y(2)/2 -3 .. +3 signed - -- D = -Y(-1)/2 + 3*Y(0)/2 - 3*Y(1)/2 + Y(2)/2 -2 .. +2 signed - - FUNCTION bic_calc0(f : unsigned(11 DOWNTO 0); - pm,p0,p1,p2 : unsigned(7 DOWNTO 0)) RETURN type_bic_abcd IS - VARIABLE xx : signed(2*FRAC+1 DOWNTO 0); -- 2.(2*FRAC) - BEGIN - xx := signed('0' & f(11 DOWNTO 12-FRAC)) * - signed('0' & f(11 DOWNTO 12-FRAC)); -- 2.(2*FRAC) - RETURN type_bic_abcd'( - a=>p0,-- 0.8 - b=>signed(('0' & p1) - ('0' & pm)), -- 0.9 - c=>signed(("000" & pm & '0') - ("00" & p0 & "00") - ("0000" & p0) + - ("00" & p1 & "00") - ("0000" & p2)), -- 3.9 - d=>signed(("00" & p0 & '0') - ("00" & p1 & '0') - ("000" & p1) + - ("000" & p0) + ("000" & p2) - ("000" & pm)), -- 2.9 - xx=>xx(2*FRAC DOWNTO 2*FRAC-8)); -- 1.8 - END FUNCTION; - FUNCTION bic_calc0(f : unsigned(11 DOWNTO 0); - p : arr_pix(0 TO 3)) RETURN type_bic_pix_abcd IS - BEGIN - RETURN type_bic_pix_abcd'(r=>bic_calc0(f,p(0).r,p(1).r,p(2).r,p(3).r), - g=>bic_calc0(f,p(0).g,p(1).g,p(2).g,p(3).g), - b=>bic_calc0(f,p(0).b,p(1).b,p(2).b,p(3).b)); - END FUNCTION; - - ---------------------------------------------------------- - -- Calc : B.X, C.XX, D.XX - FUNCTION bic_calc1(f : unsigned(11 DOWNTO 0); - abcd : type_bic_pix_abcd) RETURN type_bic_tt1 IS - VARIABLE t : type_bic_tt1; - VARIABLE bx : signed(9+FRAC DOWNTO 0); -- 1.(FRAC+9) - VARIABLE cxx : signed(20 DOWNTO 0); -- 4.17 - VARIABLE dxx : signed(19 DOWNTO 0); -- 3.17 - BEGIN - bx := abcd.r.b * signed('0' & f(11 DOWNTO 12-FRAC)); -- 1.(FRAC+9) - t.r_bx:=bx(9+FRAC DOWNTO 9+FRAC-8); -- 1.8 - cxx:= abcd.r.c * abcd.r.xx; -- 3.9 * 1.8 = 4.17 - t.r_cxx:=cxx(19 DOWNTO 8); -- 3.9 - dxx:= abcd.r.d * abcd.r.xx; -- 2.9 * 1.8 = 3.17 - t.r_dxx:=dxx(18 DOWNTO 8); -- 2.9 - bx := abcd.g.b * signed('0' & f(11 DOWNTO 12-FRAC)); -- 1.(FRAC+9) - t.g_bx:=bx(9+FRAC DOWNTO 9+FRAC-8); -- 1.8 - cxx:= abcd.g.c * abcd.g.xx; -- 3.9 * 1.8 = 4.17 - t.g_cxx:=cxx(19 DOWNTO 8); -- 3.9 - dxx:= abcd.g.d * abcd.g.xx; -- 2.9 * 1.8 = 3.17 - t.g_dxx:=dxx(18 DOWNTO 8); -- 2.9 - bx := abcd.b.b * signed('0' & f(11 DOWNTO 12-FRAC)); -- 1.(FRAC+9) - t.b_bx:=bx(9+FRAC DOWNTO 9+FRAC-8); -- 1.8 - cxx:= abcd.b.c * abcd.b.xx; -- 3.9 * 1.8 = 4.17 - t.b_cxx:=cxx(19 DOWNTO 8); -- 3.9 - dxx:= abcd.b.d * abcd.b.xx; -- 2.9 * 1.8 = 3.17 - t.b_dxx:=dxx(18 DOWNTO 8); -- 2.9 - RETURN t; - END FUNCTION; - - ---------------------------------------------------------- - -- Calc A + BX + CXX , X.DXX - FUNCTION bic_calc2(f : unsigned(11 DOWNTO 0); - t : type_bic_tt1; - abcd : type_bic_pix_abcd) RETURN type_bic_tt2 IS - VARIABLE u : type_bic_tt2; - VARIABLE x : signed(11+FRAC DOWNTO 0); -- 3.(9+FRAC) - BEGIN - u.r_abxcxx:=(t.r_bx(8) & t.r_bx) + ("00" & signed(abcd.r.a)) + t.r_cxx(10 DOWNTO 1); -- 2.8 - u.g_abxcxx:=(t.g_bx(8) & t.g_bx) + ("00" & signed(abcd.g.a)) + t.g_cxx(10 DOWNTO 1); -- 2.8 - u.b_abxcxx:=(t.b_bx(8) & t.b_bx) + ("00" & signed(abcd.b.a)) + t.b_cxx(10 DOWNTO 1); -- 2.8 + ---------------------------------------------------------- + FUNCTION ilog2 (CONSTANT v : natural) RETURN natural IS + VARIABLE r : natural := 1; + VARIABLE n : natural := 0; + BEGIN + WHILE v>r LOOP + n:=n+1; + r:=r*2; + END LOOP; + RETURN n; + END FUNCTION ilog2; + FUNCTION to_std_logic (a : boolean) RETURN std_logic IS + BEGIN + IF a THEN RETURN '1'; + ELSE RETURN '0'; + END IF; + END FUNCTION to_std_logic; - x:=t.r_dxx * signed('0' & f(11 DOWNTO 12-FRAC)); --2.9 * 1.FRAC =3.(9+FRAC) - u.r_dxxx:=x(10+FRAC DOWNTO 9+FRAC-8); -- 2.8 - x:=t.g_dxx * signed('0' & f(11 DOWNTO 12-FRAC)); --2.9 * 1.FRAC =3.(9+FRAC) - u.g_dxxx:=x(10+FRAC DOWNTO 9+FRAC-8); -- 2.8 - x:=t.b_dxx * signed('0' & f(11 DOWNTO 12-FRAC)); --2.9 * 1.FRAC =3.(9+FRAC) - u.b_dxxx:=x(10+FRAC DOWNTO 9+FRAC-8); -- 2.8 - RETURN u; - END FUNCTION; - - ---------------------------------------------------------- - -- Calc (A + BX + CXX) + (DXXX) - FUNCTION bic_calc3(f : unsigned(11 DOWNTO 0); - t : type_bic_tt2; - abcd : type_bic_pix_abcd) RETURN type_pix IS - VARIABLE x : type_pix; - VARIABLE v : signed(9 DOWNTO 0); -- 2.8 - BEGIN - v:=t.r_abxcxx + t.r_dxxx; - x.r:=bound(unsigned(v),8); - v:=t.g_abxcxx + t.g_dxxx; - x.g:=bound(unsigned(v),8); - v:=t.b_abxcxx + t.b_dxxx; - x.b:=bound(unsigned(v),8); - RETURN x; - END FUNCTION; - - ----------------------------------------------------------------------------- - SIGNAL o_h_bic_pix,o_v_bic_pix : type_pix; - SIGNAL o_h_bic_abcd1,o_h_bic_abcd2 : type_bic_pix_abcd; - SIGNAL o_v_bic_abcd1,o_v_bic_abcd2 : type_bic_pix_abcd; - SIGNAL o_h_bic_tt1,o_v_bic_tt1 : type_bic_tt1; - SIGNAL o_h_bic_tt2,o_v_bic_tt2 : type_bic_tt2; - - ----------------------------------------------------------------------------- - -- Polyphase - - CONSTANT POLY16 : arr_int9 := ( - -24,-21,-15,-9,-5,-1,4,8,6,8,5,4,3,1,0,0, - 176,174,169,160,150,131,115,85,58,27,4,-6,-20,-24,-26,-25, - -24,-25,-26,-24,-20,-6,4,27,58,85,115,131,150,160,169,174, - 0,0,0,1,3,4,5,8,6,8,4,-1,-5,-9,-15,-21); - - CONSTANT POLY32 : arr_int9 := ( - -24,-22,-20,-18,-16,-13,-11,-8,-6,-3,-1,0,2,3,5,5,6,6,6,5,5,4,4,3,2,1,1,0,0,0,0,0, - 176,175,174,172,169,164,160,153,147,138,129,119,109,96,84,71,58,40,22,12,3,-4,-12,-16,-20,-22,-25,-25,-26,-25,-25,-25, - -24,-25,-26,-26,-26,-24,-23,-19,-16,-10,-4,4,11,22,32,45,58,77,96,108,119,129,140,147,154,159,165,168,172,173,175,175, - 0,0,0,0,1,1,2,2,3,3,4,5,6,7,7,7,6,5,4,3,1,-1,-4,-6,-8,-10,-13,-15,-18,-20,-22,-22); - - FUNCTION init_poly RETURN arr_uv36 IS - VARIABLE m : arr_uv36(0 TO 2**FRAC-1) :=(OTHERS =>x"000000000"); - BEGIN - IF FRAC=4 THEN - FOR i IN 0 TO 15 LOOP - m(i):=unsigned(to_signed(POLY16(i),9) & to_signed(POLY16(i+16),9) & - to_signed(POLY16(i+32),9) & to_signed(POLY16(i+48),9)); - END LOOP; - ELSIF FRAC=5 THEN - FOR i IN 0 TO 31 LOOP - m(i):=unsigned(to_signed(POLY32(i),9) & to_signed(POLY32(i+32),9) & - to_signed(POLY32(i+64),9) & to_signed(POLY32(i+96),9)); - END LOOP; - END IF; - RETURN m; - END FUNCTION; - - SIGNAL o_h_poly : arr_uv36(0 TO 2**FRAC-1):=init_poly; - SIGNAL o_v_poly : arr_uv36(0 TO 2**FRAC-1):=init_poly; - ATTRIBUTE ramstyle OF o_h_poly : SIGNAL IS "no_rw_check"; - ATTRIBUTE ramstyle OF o_v_poly : SIGNAL IS "no_rw_check"; - SIGNAL o_h_poly_a,o_v_poly_a : integer RANGE 0 TO 2**FRAC-1; - SIGNAL o_h_poly_dr,o_h_poly_dr2,o_v_poly_dr,o_v_poly_dr2 : unsigned(35 DOWNTO 0); - SIGNAL o_h_poly_pix,o_v_poly_pix : type_pix; - SIGNAL poly_h_wr,poly_v_wr : std_logic; - SIGNAL poly_tdw : unsigned(35 DOWNTO 0); - SIGNAL poly_a2 : unsigned(FRAC-1 DOWNTO 0); - - TYPE type_poly_t IS RECORD - r0,r1,b0,b1,g0,g1 : signed(17 DOWNTO 0); - END RECORD; - - SIGNAL o_h_poly_t,o_v_poly_t : type_poly_t; - - FUNCTION poly_calc1(fi : unsigned(35 DOWNTO 0); - p : arr_pix(0 TO 3)) RETURN type_poly_t IS - VARIABLE t : type_poly_t; - BEGIN - -- 2.7 * 1.8 = 3.15 - t.r0:=(signed(fi(35 DOWNTO 27)) * signed('0' & p(0).r) + - signed(fi(26 DOWNTO 18)) * signed('0' & p(1).r)); - t.r1:=(signed(fi(17 DOWNTO 9)) * signed('0' & p(2).r) + - signed(fi( 8 DOWNTO 0)) * signed('0' & p(3).r)); - t.g0:=(signed(fi(35 DOWNTO 27)) * signed('0' & p(0).g) + - signed(fi(26 DOWNTO 18)) * signed('0' & p(1).g)); - t.g1:=(signed(fi(17 DOWNTO 9)) * signed('0' & p(2).g) + - signed(fi( 8 DOWNTO 0)) * signed('0' & p(3).g)); - t.b0:=(signed(fi(35 DOWNTO 27)) * signed('0' & p(0).b) + - signed(fi(26 DOWNTO 18)) * signed('0' & p(1).b)); - t.b1:=(signed(fi(17 DOWNTO 9)) * signed('0' & p(2).b) + - signed(fi( 8 DOWNTO 0)) * signed('0' & p(3).b)); - RETURN t; - END FUNCTION; - - FUNCTION poly_calc2(t : type_poly_t) RETURN type_pix IS - VARIABLE p : type_pix; - BEGIN - p.r:=bound(unsigned(t.r0+t.r1),15); - p.g:=bound(unsigned(t.g0+t.g1),15); - p.b:=bound(unsigned(t.b0+t.b1),15); - RETURN p; - END FUNCTION; - + ---------------------------------------------------------- + CONSTANT NB_BURST : natural :=ilog2(N_BURST); + CONSTANT NB_LA : natural :=ilog2(N_DW/8); -- Low address bits + CONSTANT BLEN : natural :=N_BURST / N_DW * 8; -- Burst length + + ---------------------------------------------------------- + TYPE arr_dw IS ARRAY (natural RANGE <>) OF unsigned(N_DW-1 DOWNTO 0); + + TYPE type_pix IS RECORD + r,g,b : unsigned(7 DOWNTO 0); -- 0.8 + END RECORD; + TYPE arr_pix IS ARRAY (natural RANGE <>) OF type_pix; + TYPE arr_pixq IS ARRAY(natural RANGE <>) OF arr_pix(0 TO 3); + ATTRIBUTE ramstyle : string; + + SUBTYPE uint12 IS natural RANGE 0 TO 4095; + SUBTYPE uint13 IS natural RANGE 0 TO 8191; + + TYPE arr_uv48 IS ARRAY (natural RANGE <>) OF unsigned(47 DOWNTO 0); + TYPE arr_uv24 IS ARRAY (natural RANGE <>) OF unsigned(23 DOWNTO 0); + TYPE arr_uv40 IS ARRAY (natural RANGE <>) OF unsigned(39 DOWNTO 0); + TYPE arr_int9 IS ARRAY (natural RANGE <>) OF integer RANGE -256 TO 255; + TYPE arr_uint12 IS ARRAY (natural RANGE <>) OF uint12; + TYPE arr_frac IS ARRAY (natural RANGE <>) OF unsigned(11 DOWNTO 0); + TYPE arr_div IS ARRAY (natural RANGE <>) OF unsigned(20 DOWNTO 0); + + ---------------------------------------------------------- + -- Input image + SIGNAL i_pvs,i_pfl,i_pde,i_pce : std_logic; + SIGNAL i_ppix : type_pix; + SIGNAL i_freeze : std_logic; + SIGNAL i_count : unsigned(2 DOWNTO 0); + SIGNAL i_hsize,i_hmin,i_hmax,i_hcpt : uint12; + SIGNAL i_hrsize,i_vrsize : uint12; + SIGNAL i_himax,i_vimax : uint12; + SIGNAL i_vsize,i_vmaxmin,i_vmin,i_vmax,i_vcpt : uint12; + SIGNAL i_iauto : std_logic; + SIGNAL i_mode : unsigned(4 DOWNTO 0); + SIGNAL i_format : unsigned(1 DOWNTO 0); + SIGNAL i_ven,i_sof : std_logic; + SIGNAL i_wr : std_logic; + SIGNAL i_divstart,i_divrun : std_logic; + SIGNAL i_de_pre,i_vs_pre,i_fl_pre : std_logic; + SIGNAL i_de_delay : natural RANGE 0 TO 31; + SIGNAL i_intercnt : natural RANGE 0 TO 3; + SIGNAL i_inter,i_half,i_flm : std_logic; + SIGNAL i_write,i_wreq,i_alt,i_line,i_wline,i_wline_mem : std_logic; + SIGNAL i_walt,i_walt_mem,i_wreq_mem : std_logic; + SIGNAL i_wdelay : natural RANGE 0 TO 7; + SIGNAL i_push,i_pushend,i_pushend2 : std_logic; + SIGNAL i_eol : std_logic; + SIGNAL i_pushhead,i_pushhead2,i_pushhead3 : std_logic; + SIGNAL i_hburst,i_hbcpt : natural RANGE 0 TO 31; + SIGNAL i_shift : unsigned(0 TO 119) := (OTHERS =>'0'); + SIGNAL i_head : unsigned(127 DOWNTO 0); + SIGNAL i_acpt : natural RANGE 0 TO 15; + SIGNAL i_dpram : arr_dw(0 TO BLEN*2-1); + ATTRIBUTE ramstyle OF i_dpram : SIGNAL IS "no_rw_check"; + SIGNAL i_endframe0,i_endframe1,i_vss : std_logic; + SIGNAL i_wad : natural RANGE 0 TO BLEN*2-1; + SIGNAL i_dw : unsigned(N_DW-1 DOWNTO 0); + SIGNAL i_adrs,i_adrsi,i_wadrs,i_wadrs_mem : unsigned(31 DOWNTO 0); + SIGNAL i_reset_na : std_logic; + SIGNAL i_hnp,i_vnp : std_logic; + SIGNAL i_mem : arr_pix(0 TO IHRES-1); -- Downscale line buffer + ATTRIBUTE ramstyle OF i_mem : SIGNAL IS "no_rw_check"; + SIGNAL i_ohsize,i_ovsize : uint12; + SIGNAL i_vdivi : unsigned(12 DOWNTO 0); + SIGNAL i_vdivr : unsigned(24 DOWNTO 0); + SIGNAL i_div : unsigned(16 DOWNTO 0); + SIGNAL i_dir : unsigned(11 DOWNTO 0); + SIGNAL i_h_frac,i_v_frac : unsigned(11 DOWNTO 0); + SIGNAL i_hacc,i_vacc : uint13; + SIGNAL i_hdown,i_vdown : std_logic; + SIGNAL i_divcpt : natural RANGE 0 TO 36; + SIGNAL i_lwad,i_lrad : natural RANGE 0 TO OHRES-1; + SIGNAL i_lwr,i_bil : std_logic; + SIGNAL i_ldw,i_ldrm : type_pix; + SIGNAL i_hpixp,i_hpix0,i_hpix1,i_hpix2,i_hpix3,i_hpix4 : type_pix; + SIGNAL i_hpix,i_pix : type_pix; + SIGNAL i_hnp1,i_hnp2,i_hnp3,i_hnp4 : std_logic; + SIGNAL i_ven1,i_ven2,i_ven3,i_ven4,i_ven5,i_ven6 : std_logic; + + ---------------------------------------------------------- + -- Avalon + TYPE type_avl_state IS (sIDLE,sWRITE,sREAD); + SIGNAL avl_state : type_avl_state; + SIGNAL avl_write_i,avl_write_sync,avl_write_sync2 : std_logic; + SIGNAL avl_read_i,avl_read_sync,avl_read_sync2 : std_logic; + SIGNAL avl_read_pulse,avl_write_pulse : std_logic; + SIGNAL avl_read_sr,avl_write_sr,avl_read_clr,avl_write_clr : std_logic; + SIGNAL avl_rad,avl_rad_c,avl_wad : natural RANGE 0 TO 2*BLEN-1; + SIGNAL avl_walt,avl_wline,avl_rline : std_logic; + SIGNAL avl_dw,avl_dr : unsigned(N_DW-1 DOWNTO 0); + SIGNAL avl_wr : std_logic; + SIGNAL avl_readdataack,avl_readack : std_logic; + SIGNAL avl_radrs,avl_wadrs : unsigned(31 DOWNTO 0); + SIGNAL avl_i_offset0,avl_o_offset0 : unsigned(31 DOWNTO 0); + SIGNAL avl_i_offset1,avl_o_offset1 : unsigned(31 DOWNTO 0); + SIGNAL avl_reset_na : std_logic; + SIGNAL avl_o_vs_sync,avl_o_vs : std_logic; + SIGNAL avl_fb_ena : std_logic; + + FUNCTION buf_next(a,b : natural RANGE 0 TO 2; freeze : std_logic := '0') RETURN natural IS + BEGIN + IF (freeze='1') THEN RETURN a; END IF; + IF (a=0 AND b=1) OR (a=1 AND b=0) THEN RETURN 2; END IF; + IF (a=1 AND b=2) OR (a=2 AND b=1) THEN RETURN 0; END IF; + RETURN 1; + END FUNCTION; + FUNCTION buf_offset(b : natural RANGE 0 TO 2; + base : unsigned(31 DOWNTO 0); + size : unsigned(31 DOWNTO 0)) RETURN unsigned IS + BEGIN + IF b=1 THEN RETURN base+size; END IF; + IF b=2 THEN RETURN base+(size(30 DOWNTO 0) & '0'); END IF; + RETURN base; + END FUNCTION; + + ---------------------------------------------------------- + -- Output + SIGNAL o_run : std_logic; + SIGNAL o_freeze : std_logic; + SIGNAL o_mode,o_hmode,o_vmode : unsigned(4 DOWNTO 0); + SIGNAL o_format : unsigned(5 DOWNTO 0); + SIGNAL o_fb_pal_dr : unsigned(23 DOWNTO 0); + SIGNAL o_fb_pal_dr2 : unsigned(23 DOWNTO 0); + SIGNAL o_fb_pal_dr_x2 : unsigned(47 DOWNTO 0); + SIGNAL pal_idx: unsigned(7 DOWNTO 0); + SIGNAL pal_idx_lsb: std_logic; + SIGNAL pal1_mem : arr_uv48(0 TO 127); + SIGNAL pal2_mem : arr_uv24(0 TO 255); + ATTRIBUTE ramstyle of pal1_mem : signal is "no_rw_check"; + ATTRIBUTE ramstyle of pal2_mem : signal is "no_rw_check"; + SIGNAL o_htotal,o_hsstart,o_hsend : uint12; + SIGNAL o_hmin,o_hmax,o_hdisp,o_v_hmin_adj : uint12; + SIGNAL o_hsize,o_vsize : uint12; + SIGNAL o_vtotal,o_vsstart,o_vsend : uint12; + SIGNAL o_vrr,o_isync,o_isync2 : std_logic; + SIGNAL o_vrr_sync,o_vrr_sync2 : boolean; + SIGNAL o_vrr_min,o_vrr_min2 : boolean; + SIGNAL o_vrr_max,o_vrr_max2 : boolean; + SIGNAL o_vcpt_sync,o_vcpt_sync2, o_vrrmax : uint12; + SIGNAL o_sync, o_sync_max : boolean; + SIGNAL o_vmin,o_vmax,o_vdisp : uint12; + SIGNAL o_divcpt : natural RANGE 0 TO 36; + SIGNAL o_iendframe0,o_iendframe02,o_iendframe1,o_iendframe12 : std_logic; + SIGNAL o_bufup0,o_bufup1,o_inter : std_logic; + SIGNAL o_ibuf0,o_ibuf1,o_obuf0,o_obuf1 : natural RANGE 0 TO 2; + TYPE enum_o_state IS (sDISP,sHSYNC,sREAD,sWAITREAD); + SIGNAL o_state : enum_o_state; + TYPE enum_o_copy IS (sWAIT,sSHIFT,sCOPY); + SIGNAL o_copy : enum_o_copy; + SIGNAL o_pshift : natural RANGE 0 TO 15; + SIGNAL o_readack,o_readack_sync,o_readack_sync2 : std_logic; + SIGNAL o_readdataack,o_readdataack_sync,o_readdataack_sync2 : std_logic; + SIGNAL o_copyv : unsigned(0 TO 14); + SIGNAL o_adrs : unsigned(31 DOWNTO 0); -- Avalon address + SIGNAL o_adrs_pre : natural RANGE 0 TO 2**24-1; + SIGNAL o_stride : unsigned(13 DOWNTO 0); + SIGNAL o_adrsa,o_adrsb,o_rline : std_logic; + SIGNAL o_ad,o_ad1,o_ad2,o_ad3 : natural RANGE 0 TO 2*BLEN-1; + SIGNAL o_adturn : std_logic; + SIGNAL o_dr : unsigned(N_DW-1 DOWNTO 0); + SIGNAL o_shift : unsigned(0 TO N_DW+15); + SIGNAL o_sh,o_sh1,o_sh2,o_sh3,o_sh4 : std_logic; + SIGNAL o_reset_na : std_logic; + SIGNAL o_dpram : arr_dw(0 TO BLEN*2-1); + ATTRIBUTE ramstyle OF o_dpram : SIGNAL IS "no_rw_check"; + SIGNAL o_line0,o_line1,o_line2,o_line3 : arr_pix(0 TO OHRES-1); + ATTRIBUTE ramstyle OF o_line0 : SIGNAL IS "no_rw_check"; + ATTRIBUTE ramstyle OF o_line1 : SIGNAL IS "no_rw_check"; + ATTRIBUTE ramstyle OF o_line2 : SIGNAL IS "no_rw_check"; + ATTRIBUTE ramstyle OF o_line3 : SIGNAL IS "no_rw_check"; + SIGNAL o_wadl,o_radl0,o_radl1,o_radl2,o_radl3 : natural RANGE 0 TO OHRES-1; + SIGNAL o_ldw,o_ldr0,o_ldr1,o_ldr2,o_ldr3 : type_pix; + SIGNAL o_wr : unsigned(3 DOWNTO 0); + SIGNAL o_hcpt,o_vcpt,o_vcpt_pre,o_vcpt_pre2,o_vcpt_pre3,o_vcpt2 : uint12; + SIGNAL o_ihsize,o_ihsizem,o_ivsize : uint12; + SIGNAL o_ihsize_temp, o_ihsize_temp2 : natural RANGE 0 TO 32767; + + SIGNAL o_vfrac : unsigned(11 DOWNTO 0); + SIGNAL o_hfrac : arr_frac(0 TO 9); + ATTRIBUTE ramstyle OF o_hfrac : SIGNAL IS "logic"; -- avoid blockram shift register + + SIGNAL o_hacc,o_hacc_ini,o_hacc_next,o_vacc,o_vacc_next,o_vacc_ini : natural RANGE 0 TO 4*OHRES-1; + SIGNAL o_hsv,o_vsv,o_dev,o_pev,o_end : unsigned(0 TO 11); + SIGNAL o_hsp,o_vss : std_logic; + SIGNAL o_vcarrym,o_prim : boolean; + SIGNAL o_read,o_read_pre : std_logic; + SIGNAL o_readlev,o_copylev : natural RANGE 0 TO 2; + SIGNAL o_hburst,o_hbcpt : natural RANGE 0 TO 31; + SIGNAL o_fload : natural RANGE 0 TO 3; + SIGNAL o_acpt,o_acpt1,o_acpt2,o_acpt3,o_acpt4 : natural RANGE 0 TO 15; -- Alternance pixels FIFO + SIGNAL o_dshi : natural RANGE 0 TO 3; + SIGNAL o_first,o_last,o_last1,o_last2 : std_logic; + SIGNAL o_lastt1,o_lastt2,o_lastt3,o_lastt4 : std_logic; + SIGNAL o_alt,o_altx : unsigned(3 DOWNTO 0); + SIGNAL o_hdown,o_vdown : std_logic; + SIGNAL o_primv,o_lastv,o_bibv : unsigned(0 TO 2); + TYPE arr_uint4 IS ARRAY (natural RANGE <>) OF natural RANGE 0 TO 15; + SIGNAL o_off : arr_uint4(0 TO 2); + SIGNAL o_bibu : std_logic :='0'; + SIGNAL o_dcptv : arr_uint12(1 TO 14); + SIGNAL o_dcpt : uint12; + SIGNAL o_hpixs,o_hpix0,o_hpix1,o_hpix2,o_hpix3 : type_pix; + SIGNAL o_hpixq : arr_pixq(2 TO 8); + ATTRIBUTE ramstyle OF o_hpixq : SIGNAL IS "logic"; -- avoid blockram shift register + SIGNAL o_vpixq, o_vpixq_pre : arr_pix(0 TO 3); + SIGNAL o_vpix_outer : arr_pix(0 TO 2); + SIGNAL o_vpix_inner : arr_pix(0 TO 6); + + + SIGNAL o_vpe : std_logic; + SIGNAL o_div : arr_div(0 TO 2); --uint12; + SIGNAL o_dir : arr_frac(0 TO 2); + ATTRIBUTE ramstyle OF o_div, o_dir : SIGNAL IS "logic"; -- avoid blockram shift register + SIGNAL o_vdivi : unsigned(12 DOWNTO 0); + SIGNAL o_vdivr : unsigned(24 DOWNTO 0); + SIGNAL o_divstart : std_logic; + SIGNAL o_divrun : std_logic; + SIGNAL o_hacpt,o_vacpt : unsigned(11 DOWNTO 0); + SIGNAL o_vacptl : unsigned(1 DOWNTO 0); + signal o_newres : integer range 0 to 3; + + ----------------------------------------------------------------------------- + FUNCTION shift_ishift(shift : unsigned(0 TO 119); + pix : type_pix; + format : unsigned(1 DOWNTO 0)) RETURN unsigned IS + BEGIN + CASE format IS + WHEN "01" => -- 24bpp + RETURN shift(24 TO 119) & pix.r & pix.g & pix.b; + WHEN "10" => -- 32bpp + RETURN shift(32 TO 119) & pix.r & pix.g & pix.b & x"00"; + WHEN OTHERS => -- 16bpp 565 + RETURN shift(16 TO 119) & + pix.g(4 DOWNTO 2) & pix.r(7 DOWNTO 3) & + pix.b(7 DOWNTO 3) & pix.g(7 DOWNTO 5); + END CASE; + END FUNCTION; + + FUNCTION shift_ipack( i_dw : unsigned(N_DW-1 DOWNTO 0); + acpt : natural RANGE 0 TO 15; + shift : unsigned(0 TO 119); + pix : type_pix; + format : unsigned(1 DOWNTO 0)) RETURN unsigned IS + VARIABLE dw : unsigned(N_DW-1 DOWNTO 0); + BEGIN + dw:=i_dw; + CASE format IS + WHEN "01" => -- 24bpp + IF N_DW=128 THEN + IF acpt=5 THEN dw:=shift(0 TO 119) & pix.r; + ELSIF acpt=10 THEN dw:=shift(8 TO 119) & pix.r & pix.g; + ELSIF acpt=15 THEN dw:=shift(16 TO 119) & pix.r & pix.g & pix.b; + END IF; + ELSE -- N_DW=64 + IF (acpt MOD 8)=2 THEN dw:=shift(72 TO 119) & pix.r & pix.g; + ELSIF (acpt MOD 8)=5 THEN dw:=shift(64 TO 119) & pix.r; + ELSIF (acpt MOD 8)=7 THEN dw:=shift(80 TO 119) & pix.r & pix.g & pix.b; + END IF; + END IF; + WHEN "10" => -- 32bpp + IF (N_DW=128 AND (acpt MOD 4)=3) OR (N_DW=64 AND (acpt MOD 8)=7) THEN + dw:=shift(128-N_DW+24 TO 119) & pix.r & pix.g & pix.b & x"00"; + END IF; + WHEN OTHERS => -- 16bpp 565 + IF (N_DW=128 AND (acpt MOD 8)=7) OR (N_DW=64 AND (acpt MOD 4)=3) THEN + dw:=shift(128-N_DW+8 TO 119) & pix.g(4 DOWNTO 2) & pix.r(7 DOWNTO 3) & + pix.b(7 DOWNTO 3) & pix.g(7 DOWNTO 5); + END IF; + END CASE; + RETURN dw; + END FUNCTION; + + FUNCTION shift_inext (acpt : natural RANGE 0 TO 15; + format : unsigned(1 DOWNTO 0)) RETURN boolean IS + BEGIN + CASE format IS + WHEN "01" => -- 24bpp + RETURN (N_DW=128 AND (acpt=5 OR acpt=10 OR acpt=15)) OR + (N_DW=64 AND ((acpt MOD 8)=2 OR (acpt MOD 8)=5 OR (acpt MOD 8)=7)); + WHEN "10" => -- 32bpp + RETURN (N_DW=128 AND ((acpt MOD 4)=3)) OR + (N_DW=64 AND ((acpt MOD 2)=1)); + WHEN OTHERS => -- 16bpp + RETURN (N_DW=128 AND ((acpt MOD 8)=7)) OR + (N_DW=64 AND ((acpt MOD 4)=3)); + END CASE; + END FUNCTION; + + FUNCTION shift_opack(acpt : natural RANGE 0 TO 15; + shift : unsigned(0 TO N_DW+15); + dr : unsigned(N_DW-1 DOWNTO 0); + format : unsigned(5 DOWNTO 0)) RETURN unsigned IS + VARIABLE shift_v : unsigned(0 TO N_DW+15); + BEGIN + CASE format(2 DOWNTO 0) IS + WHEN "011" => -- 8bpp + IF (N_DW=128 AND acpt=0) OR (N_DW=64 AND (acpt MOD 8)=0) THEN + shift_v:=dr & dr(15 DOWNTO 0); + ELSE + shift_v:=shift(8 TO N_DW+15) & dr(7 DOWNTO 0); + END IF; + + WHEN "100" => -- 16bpp + IF (N_DW=128 AND (acpt MOD 8)=0) OR (N_DW=64 AND (acpt MOD 4)=0) THEN + shift_v:=dr & dr(15 DOWNTO 0); + ELSE + shift_v:=shift(16 TO N_DW+15) & dr(15 DOWNTO 0); + END IF; + + WHEN "101" => -- 24bpp + IF N_DW=128 THEN + IF acpt=0 THEN + shift_v:=dr & dr(15 DOWNTO 0); + ELSIF acpt=5 THEN + shift_v:=shift(24 TO 31) & dr & dr(7 DOWNTO 0); + ELSIF acpt=10 THEN + shift_v:=shift(24 TO 39) & dr; + ELSE + shift_v:=shift(24 TO N_DW+15) & dr(23 DOWNTO 0); + END IF; + ELSE -- N_DW=64 + IF (acpt MOD 8)=0 THEN + shift_v:=dr & dr(15 DOWNTO 0); + ELSIF (acpt MOD 8)=2 THEN + shift_v:=shift(24 TO 39) & dr; + ELSIF (acpt MOD 8)=5 THEN + shift_v:=shift(24 TO 31) & dr & dr(7 DOWNTO 0); + ELSE + shift_v:=shift(24 TO N_DW+15) & dr(23 DOWNTO 0); + END IF; + END IF; + WHEN OTHERS => -- 32bpp + IF (N_DW=128 AND (acpt MOD 4)=0) OR (N_DW=64 AND (acpt MOD 2)=0) THEN + shift_v:=dr & dr(15 DOWNTO 0); + ELSE + shift_v:=shift(32 TO N_DW+15) & dr(31 DOWNTO 0); + END IF; + END CASE; + RETURN shift_v; + END FUNCTION; + + FUNCTION shift_onext (acpt : natural RANGE 0 TO 15; + format : unsigned(5 DOWNTO 0)) RETURN boolean IS + BEGIN + CASE format(2 DOWNTO 0) IS + WHEN "011" => -- 8bpp + RETURN (N_DW=128 AND acpt=0) OR + (N_DW=64 AND ((acpt MOD 8)=0)); + WHEN "100" => -- 16bpp + RETURN (N_DW=128 AND ((acpt MOD 8)=0)) OR + (N_DW=64 AND ((acpt MOD 4)=0)); + WHEN "101" => -- 24bpp + RETURN (N_DW=128 AND (acpt=0 OR acpt=5 OR acpt=10)) OR + (N_DW=64 AND ((acpt MOD 8)=0 OR (acpt MOD 8)=2 OR (acpt MOD 8)=5)); + WHEN OTHERS => -- 32bpp + RETURN (N_DW=128 AND ((acpt MOD 4)=0)) OR + (N_DW=64 AND ((acpt MOD 2)=0)); + END CASE; + END FUNCTION; + + FUNCTION shift_opix (shift : unsigned(0 TO N_DW+15); + format : unsigned(5 DOWNTO 0)) RETURN type_pix IS + BEGIN + CASE format(3 DOWNTO 0) IS + WHEN "0100" => -- 16bpp 565 + RETURN (b=>shift(8 TO 12) & shift(8 TO 10), + g=>shift(13 TO 15) & shift(0 TO 2) & shift(13 TO 14), + r=>shift(3 TO 7) & shift(3 TO 5)); + WHEN "1100" => -- 16bpp 1555 + RETURN (b=>shift(9 TO 13) & shift(9 TO 11), + g=>shift(14 TO 15) & shift(0 TO 2) & shift(14 TO 15) & shift(0), + r=>shift(3 TO 7) & shift(3 TO 5)); + WHEN "0101" | "0110" => -- 24bpp / 32bpp + RETURN (r=>shift(0 TO 7),g=>shift(8 TO 15),b=>shift(16 TO 23)); + + WHEN OTHERS => + RETURN (r=>shift(0 TO 7),g=>shift(8 TO 15),b=>shift(16 TO 23)); + + END CASE; + END FUNCTION; + + FUNCTION pixoffset(adrs : unsigned(31 DOWNTO 0); + format : unsigned (5 DOWNTO 0)) RETURN natural IS + BEGIN + CASE format(2 DOWNTO 0) IS + WHEN "011" => -- 8bbp + RETURN to_integer(adrs(NB_LA-1 DOWNTO 0)); + WHEN "100" => -- 16bpp 565 + RETURN to_integer(adrs(NB_LA-1 DOWNTO 1)); + WHEN OTHERS => -- 32bpp + RETURN to_integer(adrs(NB_LA-1 DOWNTO 2)); + END CASE; + END FUNCTION; + + FUNCTION swap(d : unsigned(N_DW-1 DOWNTO 0)) RETURN unsigned IS + VARIABLE e : unsigned(N_DW-1 DOWNTO 0); + BEGIN + IF BYTESWAP THEN + FOR i IN 0 TO N_DW/8-1 LOOP + e(i*8+7 DOWNTO i*8):=d(N_DW-i*8-1 DOWNTO N_DW-i*8-8); + END LOOP; + RETURN e; + ELSE + RETURN d; + END IF; + END FUNCTION swap; + + ----------------------------------------------------------------------------- + FUNCTION altx (a : unsigned(1 DOWNTO 0)) RETURN unsigned IS + BEGIN + CASE a IS + WHEN "00" => RETURN "0001"; + WHEN "01" => RETURN "0010"; + WHEN "10" => RETURN "0100"; + WHEN OTHERS => RETURN "1000"; + END CASE; + END FUNCTION; + + ----------------------------------------------------------------------------- + FUNCTION bound(a : unsigned; + s : natural) RETURN unsigned IS + BEGIN + IF a(a'left)='1' THEN + RETURN x"00"; + ELSIF a(a'left DOWNTO s)/=0 THEN + RETURN x"FF"; + ELSE + RETURN a(s-1 DOWNTO s-8); + END IF; + END FUNCTION bound; + + ----------------------------------------------------------------------------- + -- Nearest + FUNCTION near_frac(f : unsigned) RETURN unsigned IS + VARIABLE x : unsigned(FRAC-1 DOWNTO 0); + BEGIN + x:=(OTHERS =>f(f'left)); + RETURN x; + END FUNCTION; + + SIGNAL o_h_near_frac,o_v_near_frac : unsigned(FRAC-1 DOWNTO 0); + SIGNAL o_h_bil_frac,o_v_bil_frac : unsigned(FRAC-1 DOWNTO 0); + SIGNAL o_h_bil_pix,o_v_bil_pix : type_pix; + + ----------------------------------------------------------------------------- + -- Nearest + Bilinear + Sharp Bilinear + FUNCTION bil_frac(f : unsigned) RETURN unsigned IS + BEGIN + RETURN f(f'left DOWNTO f'left+1-FRAC); + END FUNCTION; + + TYPE type_bil_t IS RECORD + r,g,b : unsigned(8+FRAC DOWNTO 0); + END RECORD; + + FUNCTION bil_calc(f : unsigned(FRAC-1 DOWNTO 0); + p : arr_pix(0 TO 3)) RETURN type_bil_t IS + VARIABLE fp,fn : unsigned(FRAC DOWNTO 0); + VARIABLE u : unsigned(8+FRAC DOWNTO 0); + VARIABLE x : type_bil_t; + CONSTANT Z : unsigned(FRAC-1 DOWNTO 0):=(OTHERS =>'0'); + BEGIN + fp:=('0' & f) + (Z & f(FRAC-1)); + fn:=('1' & Z) - fp; + u:=p(2).r * fp + p(1).r * fn; + x.r:=u; + u:=p(2).g * fp + p(1).g * fn; + x.g:=u; + u:=p(2).b * fp + p(1).b * fn; + x.b:=u; + RETURN x; + END FUNCTION; + + FUNCTION near_calc(f : unsigned(FRAC-1 DOWNTO 0); + p : arr_pix(0 TO 3)) RETURN type_bil_t IS + VARIABLE fp,fn : unsigned(FRAC DOWNTO 0); + VARIABLE u : unsigned(8+FRAC DOWNTO 0); + VARIABLE x : type_bil_t; + CONSTANT Z : unsigned(FRAC-1 DOWNTO 0):=(OTHERS =>'0'); + BEGIN + IF f(FRAC-1)='0' THEN + x.r := '0' & p(1).r & Z; + x.g := '0' & p(1).g & Z; + x.b := '0' & p(1).b & Z; + ELSE + x.r := '0' & p(2).r & Z; + x.g := '0' & p(2).g & Z; + x.b := '0' & p(2).b & Z; + END IF; + RETURN x; + END FUNCTION; + + SIGNAL o_h_bil_t,o_v_bil_t : type_bil_t; + SIGNAL o_h_near_t,o_v_near_t : type_bil_t; + SIGNAL i_h_bil_t : type_bil_t; + + ----------------------------------------------------------------------------- + -- Sharp Bilinear + -- <0.5 : x*x*x*4 + -- >0.5 : 1 - (1-x)*(1-x)*(1-x)*4 + + TYPE type_sbil_tt IS RECORD + f : unsigned(FRAC-1 DOWNTO 0); + s : unsigned(FRAC-1 DOWNTO 0); + END RECORD; + + SIGNAL o_h_sbil_t,o_v_sbil_t : type_sbil_tt; + + FUNCTION sbil_frac1(f : unsigned(11 DOWNTO 0)) RETURN type_sbil_tt IS + VARIABLE u : unsigned(FRAC-1 DOWNTO 0); + VARIABLE v : unsigned(2*FRAC-1 DOWNTO 0); + VARIABLE x : type_sbil_tt; + BEGIN + IF f(11)='0' THEN + u:=f(11 DOWNTO 12-FRAC); + ELSE + u:=NOT f(11 DOWNTO 12-FRAC); + END IF; + v:=u*u; + x.f:=u; + x.s:=v(2*FRAC-2 DOWNTO FRAC-1); + RETURN x; + END FUNCTION; + + FUNCTION sbil_frac2(f : unsigned(11 DOWNTO 0); + t : type_sbil_tt) RETURN unsigned IS + VARIABLE v : unsigned(2*FRAC-1 DOWNTO 0); + BEGIN + v:=t.f*t.s; + IF f(11)='0' THEN + RETURN v(2*FRAC-2 DOWNTO FRAC-1); + ELSE + RETURN NOT v(2*FRAC-2 DOWNTO FRAC-1); + END IF; + END FUNCTION; + + ----------------------------------------------------------------------------- + -- Bicubic + TYPE type_bic_abcd IS RECORD + a : unsigned(7 DOWNTO 0); -- 0.8 + b : signed(8 DOWNTO 0); -- 0.9 + c : signed(11 DOWNTO 0); -- 3.9 + d : signed(10 DOWNTO 0); -- 2.9 + xx : signed(8 DOWNTO 0); -- X.X 1.8 + END RECORD; + TYPE type_bic_pix_abcd IS RECORD + r,g,b : type_bic_abcd; + END RECORD; + TYPE type_bic_tt1 IS RECORD -- Intermediate result + r_bx,g_bx,b_bx : signed(8 DOWNTO 0); -- B.X 1.8 + r_cxx,g_cxx,b_cxx : signed(11 DOWNTO 0); -- C.XX 3.9 + r_dxx,g_dxx,b_dxx : signed(10 DOWNTO 0); -- D.XX 2.9 + END RECORD; + TYPE type_bic_tt2 IS RECORD -- Intermediate result + r_abxcxx,g_abxcxx,b_abxcxx : signed(9 DOWNTO 0); -- A + B.X + C.XX 2.8 + r_dxxx,g_dxxx,b_dxxx : signed(9 DOWNTO 0); -- D.X.X.X 2.8 + END RECORD; + + ---------------------------------------------------------- + -- Y = A + B.X + C.X.X + D.X.X.X = A + X.(B + X.(C + X.D)) + -- A = Y(0) 0 .. 1 unsigned + -- B = Y(1)/2 - Y(-1)/2 -1/2 .. +1/2 signed + -- C = Y(-1) - 5*Y(0)/2 + 2*Y(1) - Y(2)/2 -3 .. +3 signed + -- D = -Y(-1)/2 + 3*Y(0)/2 - 3*Y(1)/2 + Y(2)/2 -2 .. +2 signed + + FUNCTION bic_calc0(f : unsigned(11 DOWNTO 0); + pm,p0,p1,p2 : unsigned(7 DOWNTO 0)) RETURN type_bic_abcd IS + VARIABLE xx : signed(2*FRAC+1 DOWNTO 0); -- 2.(2*FRAC) + BEGIN + xx := signed('0' & f(11 DOWNTO 12-FRAC)) * + signed('0' & f(11 DOWNTO 12-FRAC)); -- 2.(2*FRAC) + RETURN type_bic_abcd'( + a=>p0,-- 0.8 + b=>signed(('0' & p1) - ('0' & pm)), -- 0.9 + c=>signed(("000" & pm & '0') - ("00" & p0 & "00") - ("0000" & p0) + + ("00" & p1 & "00") - ("0000" & p2)), -- 3.9 + d=>signed(("00" & p0 & '0') - ("00" & p1 & '0') - ("000" & p1) + + ("000" & p0) + ("000" & p2) - ("000" & pm)), -- 2.9 + xx=>xx(2*FRAC DOWNTO 2*FRAC-8)); -- 1.8 + END FUNCTION; + FUNCTION bic_calc0(f : unsigned(11 DOWNTO 0); + p : arr_pix(0 TO 3)) RETURN type_bic_pix_abcd IS + BEGIN + RETURN type_bic_pix_abcd'( r=>bic_calc0(f,p(0).r,p(1).r,p(2).r,p(3).r), + g=>bic_calc0(f,p(0).g,p(1).g,p(2).g,p(3).g), + b=>bic_calc0(f,p(0).b,p(1).b,p(2).b,p(3).b)); + END FUNCTION; + + ---------------------------------------------------------- + -- Calc : B.X, C.XX, D.XX + FUNCTION bic_calc1(f : unsigned(11 DOWNTO 0); + abcd : type_bic_pix_abcd) RETURN type_bic_tt1 IS + VARIABLE t : type_bic_tt1; + VARIABLE bx : signed(9+FRAC DOWNTO 0); -- 1.(FRAC+9) + VARIABLE cxx : signed(20 DOWNTO 0); -- 4.17 + VARIABLE dxx : signed(19 DOWNTO 0); -- 3.17 + BEGIN + bx := abcd.r.b * signed('0' & f(11 DOWNTO 12-FRAC)); -- 1.(FRAC+9) + t.r_bx:=bx(9+FRAC DOWNTO 9+FRAC-8); -- 1.8 + cxx:= abcd.r.c * abcd.r.xx; -- 3.9 * 1.8 = 4.17 + t.r_cxx:=cxx(19 DOWNTO 8); -- 3.9 + dxx:= abcd.r.d * abcd.r.xx; -- 2.9 * 1.8 = 3.17 + t.r_dxx:=dxx(18 DOWNTO 8); -- 2.9 + bx := abcd.g.b * signed('0' & f(11 DOWNTO 12-FRAC)); -- 1.(FRAC+9) + t.g_bx:=bx(9+FRAC DOWNTO 9+FRAC-8); -- 1.8 + cxx:= abcd.g.c * abcd.g.xx; -- 3.9 * 1.8 = 4.17 + t.g_cxx:=cxx(19 DOWNTO 8); -- 3.9 + dxx:= abcd.g.d * abcd.g.xx; -- 2.9 * 1.8 = 3.17 + t.g_dxx:=dxx(18 DOWNTO 8); -- 2.9 + bx := abcd.b.b * signed('0' & f(11 DOWNTO 12-FRAC)); -- 1.(FRAC+9) + t.b_bx:=bx(9+FRAC DOWNTO 9+FRAC-8); -- 1.8 + cxx:= abcd.b.c * abcd.b.xx; -- 3.9 * 1.8 = 4.17 + t.b_cxx:=cxx(19 DOWNTO 8); -- 3.9 + dxx:= abcd.b.d * abcd.b.xx; -- 2.9 * 1.8 = 3.17 + t.b_dxx:=dxx(18 DOWNTO 8); -- 2.9 + RETURN t; + END FUNCTION; + + ---------------------------------------------------------- + -- Calc A + BX + CXX , X.DXX + FUNCTION bic_calc2(f : unsigned(11 DOWNTO 0); + t : type_bic_tt1; + abcd : type_bic_pix_abcd) RETURN type_bic_tt2 IS + VARIABLE u : type_bic_tt2; + VARIABLE x : signed(11+FRAC DOWNTO 0); -- 3.(9+FRAC) + BEGIN + u.r_abxcxx:=(t.r_bx(8) & t.r_bx) + ("00" & signed(abcd.r.a)) + t.r_cxx(10 DOWNTO 1); -- 2.8 + u.g_abxcxx:=(t.g_bx(8) & t.g_bx) + ("00" & signed(abcd.g.a)) + t.g_cxx(10 DOWNTO 1); -- 2.8 + u.b_abxcxx:=(t.b_bx(8) & t.b_bx) + ("00" & signed(abcd.b.a)) + t.b_cxx(10 DOWNTO 1); -- 2.8 + + x:=t.r_dxx * signed('0' & f(11 DOWNTO 12-FRAC)); --2.9 * 1.FRAC =3.(9+FRAC) + u.r_dxxx:=x(10+FRAC DOWNTO 9+FRAC-8); -- 2.8 + x:=t.g_dxx * signed('0' & f(11 DOWNTO 12-FRAC)); --2.9 * 1.FRAC =3.(9+FRAC) + u.g_dxxx:=x(10+FRAC DOWNTO 9+FRAC-8); -- 2.8 + x:=t.b_dxx * signed('0' & f(11 DOWNTO 12-FRAC)); --2.9 * 1.FRAC =3.(9+FRAC) + u.b_dxxx:=x(10+FRAC DOWNTO 9+FRAC-8); -- 2.8 + RETURN u; + END FUNCTION; + + ---------------------------------------------------------- + -- Calc (A + BX + CXX) + (DXXX) + FUNCTION bic_calc3(f : unsigned(11 DOWNTO 0); + t : type_bic_tt2; + abcd : type_bic_pix_abcd) RETURN type_pix IS + VARIABLE x : type_pix; + VARIABLE v : signed(9 DOWNTO 0); -- 2.8 + BEGIN + v:=t.r_abxcxx + t.r_dxxx; + x.r:=bound(unsigned(v),8); + v:=t.g_abxcxx + t.g_dxxx; + x.g:=bound(unsigned(v),8); + v:=t.b_abxcxx + t.b_dxxx; + x.b:=bound(unsigned(v),8); + RETURN x; + END FUNCTION; + + ----------------------------------------------------------------------------- + SIGNAL o_h_bic_pix,o_v_bic_pix : type_pix; + SIGNAL o_h_bic_abcd1,o_h_bic_abcd2 : type_bic_pix_abcd; + SIGNAL o_v_bic_abcd1,o_v_bic_abcd2 : type_bic_pix_abcd; + SIGNAL o_h_bic_tt1,o_v_bic_tt1 : type_bic_tt1; + SIGNAL o_h_bic_tt2,o_v_bic_tt2 : type_bic_tt2; + + ----------------------------------------------------------------------------- + -- Polyphase + -- 2.7 + TYPE poly_phase_t IS RECORD + t0, t1, t2, t3 : signed(9 DOWNTO 0); + END RECORD; + + -- 4.14 + TYPE poly_phase_interp_t IS RECORD + t0, t1, t2, t3 : signed(17 DOWNTO 0); + END RECORD; + + -- 5.22 + TYPE type_poly_t IS RECORD + r0,r1,b0,b1,g0,g1 : signed(26 DOWNTO 0); + END RECORD; + + SIGNAL o_h_poly_mem : arr_uv40(0 TO 2**FRAC-1); + SIGNAL o_v_poly_mem : arr_uv40(0 TO 2**FRAC-1); + SIGNAL o_a_poly_mem : arr_uv40(0 TO 2**FRAC-1); + ATTRIBUTE ramstyle OF o_h_poly_mem : SIGNAL IS "no_rw_check"; + ATTRIBUTE ramstyle OF o_v_poly_mem : SIGNAL IS "no_rw_check"; + ATTRIBUTE ramstyle OF o_a_poly_mem : SIGNAL IS "no_rw_check"; + SIGNAL o_a_poly_addr, o_v_poly_addr : integer RANGE 0 TO 2**FRAC-1; + SIGNAL o_h_poly_phase_a,o_h_poly_phase_a2,o_h_poly_phase_a3, o_h_poly_phase_a4, o_h_poly_phase_a5 : poly_phase_t; + SIGNAL o_v_poly_phase_a,o_v_poly_phase_a2,o_v_poly_phase_a3, o_v_poly_phase_a4, o_v_poly_phase_a5 : poly_phase_t; + SIGNAL o_poly_phase_a, o_poly_phase_a2, o_poly_phase_a3 : poly_phase_t; + SIGNAL o_poly_phase_b,o_poly_phase_b2,o_poly_phase_b3 : poly_phase_t; + SIGNAL o_v_poly_phase, o_v_poly_phase2, o_h_poly_phase, o_poly_phase, o_poly_phase1 : poly_phase_interp_t; + SIGNAL o_v_poly_pix, o_h_poly_pix, o_h_lum_pix, o_v_lum_pix : type_pix; + SIGNAL o_poly_lum, o_poly_lum1 : unsigned(7 DOWNTO 0); + SIGNAL o_poly_lerp_ta, o_poly_lerp_tb : signed(9 DOWNTO 0); + SIGNAL o_h_poly_t,o_h_poly_t2,o_v_poly_t : type_poly_t; + + SIGNAL o_v_poly_adaptive, o_h_poly_adaptive, o_v_poly_use_adaptive, o_h_poly_use_adaptive : std_logic; + SIGNAL poly_wr_mode : std_logic_vector(2 DOWNTO 0); + SIGNAL poly_tdw : unsigned(39 DOWNTO 0); + SIGNAL poly_a2 : unsigned(FRAC-1 DOWNTO 0); + + FUNCTION poly_unpack(a : unsigned(39 DOWNTO 0)) RETURN poly_phase_t IS + VARIABLE v : poly_phase_t; + BEGIN + v.t0 := signed(a(39 DOWNTO 30)); + v.t1 := signed(a(29 DOWNTO 20)); + v.t2 := signed(a(19 DOWNTO 10)); + v.t3 := signed(a( 9 DOWNTO 0)); + RETURN v; + END FUNCTION; + + -- 6 DSP 18*18 + 18*18 + FUNCTION poly_calc(fi : poly_phase_interp_t; + p : arr_pix(0 TO 3)) RETURN type_poly_t IS + VARIABLE t : type_poly_t; + BEGIN + -- 3.15 * 1.8 = 4.23 + t.r0:=(fi.t0 * signed('0' & p(0).r) + + fi.t1 * signed('0' & p(1).r)); + t.r1:=(fi.t2 * signed('0' & p(2).r) + + fi.t3 * signed('0' & p(3).r)); + t.g0:=(fi.t0 * signed('0' & p(0).g) + + fi.t1 * signed('0' & p(1).g)); + t.g1:=(fi.t2 * signed('0' & p(2).g) + + fi.t3 * signed('0' & p(3).g)); + t.b0:=(fi.t0 * signed('0' & p(0).b) + + fi.t1 * signed('0' & p(1).b)); + t.b1:=(fi.t2 * signed('0' & p(2).b) + + fi.t3 * signed('0' & p(3).b)); + RETURN t; + END FUNCTION; + + FUNCTION poly_final(t : type_poly_t) RETURN type_pix IS + VARIABLE p : type_pix; + BEGIN + p.r:=bound(unsigned(t.r0(26 DOWNTO 8)+t.r1(26 DOWNTO 8)),15); + p.g:=bound(unsigned(t.g0(26 DOWNTO 8)+t.g1(26 DOWNTO 8)),15); + p.b:=bound(unsigned(t.b0(26 DOWNTO 8)+t.b1(26 DOWNTO 8)),15); + RETURN p; + END FUNCTION; + + -- 4 DSP 18*18 + 18*18 + FUNCTION poly_lerp(a : poly_phase_t; + b : poly_phase_t; + ta : SIGNED(9 DOWNTO 0); + tb : SIGNED(9 DOWNTO 0)) RETURN poly_phase_interp_t IS + VARIABLE v : poly_phase_interp_t; + VARIABLE t0,t1,t2,t3 : signed(19 DOWNTO 0); + BEGIN + -- 2.8 * 2.8 = 4.16 + t0 := (a.t0 * ta) + (b.t0 * tb); + t1 := (a.t1 * ta) + (b.t1 * tb); + t2 := (a.t2 * ta) + (b.t2 * tb); + t3 := (a.t3 * ta) + (b.t3 * tb); + + -- 4.16 -> 3.15 + v.t0 := t0(18 DOWNTO 1); + v.t1 := t1(18 DOWNTO 1); + v.t2 := t2(18 DOWNTO 1); + v.t3 := t3(18 DOWNTO 1); + + RETURN v; + END FUNCTION; + + FUNCTION poly_cvt(a : poly_phase_t) RETURN poly_phase_interp_t IS + VARIABLE v : poly_phase_interp_t; + BEGIN + v.t0 := resize(signed( a.t0 & "0000000" ), v.t0'length); + v.t1 := resize(signed( a.t1 & "0000000" ), v.t1'length); + v.t2 := resize(signed( a.t2 & "0000000" ), v.t2'length); + v.t3 := resize(signed( a.t3 & "0000000" ), v.t3'length); + RETURN v; + END FUNCTION; + + -- Nearest neighbor polyphase ceoffs + FUNCTION poly_nn(frac : unsigned(FRAC-1 DOWNTO 0)) RETURN poly_phase_t IS + VARIABLE v : poly_phase_t; + BEGIN + IF frac(frac'left)='0' THEN + v := (t1=>to_signed(256, 10), OTHERS=>to_signed(0, 10)); + ELSE + v := (t2=>to_signed(256, 10), OTHERS=>to_signed(0, 10)); + END IF; + RETURN v; + END FUNCTION; + + + FUNCTION poly_lum(p : type_pix) RETURN unsigned IS + VARIABLE v : UNSIGNED(7 DOWNTO 0); + BEGIN + -- 0.375 R + 0.5 G + 0.125 B + --v := ("00" & p.r(7 DOWNTO 2)) + ("000" & p.r(7 DOWNTO 3)) + ("0" & p.g(7 DOWNTO 1)) + ("000" & p.b(7 DOWNTO 3)); + + -- 0.25 R + 0.5 G + 0.25 B + -- v := ( ("00" & p.r(7 DOWNTO 2)) + ("0" & p.g(7 DOWNTO 1)) + ("00" & p.b(7 DOWNTO 2)) ); + + -- Just OR them all together + --v := (p.r OR p.g OR p.b); + + -- Maximum + IF p.r > p.g THEN + v := p.r; + ELSE + v := p.g; + END IF; + + IF p.b > v THEN + v := p.b; + END IF; + + -- 100% + -- v := "1111111"; + + RETURN v; + END FUNCTION; BEGIN - - ----------------------------------------------------------------------------- - i_reset_na<='0' WHEN reset_na='0' ELSE '1' WHEN rising_edge(i_clk); - o_reset_na<='0' WHEN reset_na='0' ELSE '1' WHEN rising_edge(o_clk); - avl_reset_na<='0' WHEN reset_na='0' ELSE '1' WHEN rising_edge(avl_clk); - - ----------------------------------------------------------------------------- - -- Input pixels FIFO and shreg - InAT:PROCESS(i_clk,i_reset_na) IS - CONSTANT Z : unsigned(FRAC-1 DOWNTO 0):=(OTHERS =>'0'); - VARIABLE frac_v : unsigned(FRAC-1 DOWNTO 0); - VARIABLE div_v : unsigned(16 DOWNTO 0); - VARIABLE dir_v : unsigned(11 DOWNTO 0); - VARIABLE bil_t_v : type_bil_t; - BEGIN - IF i_reset_na='0' THEN - i_write<='0'; - - ELSIF rising_edge(i_clk) THEN - i_push<='0'; - i_pushhead<='0'; - i_eol<='0'; -- End Of Line - i_freeze <=freeze; -- - i_iauto<=iauto; -- - i_wreq<='0'; - i_wr<='0'; - - ------------------------------------------------------ - i_head(127 DOWNTO 120)<=x"01"; -- Header type - i_head(119 DOWNTO 112)<="000000" & i_format; -- Header format - i_head(111 DOWNTO 96)<="0000" & to_unsigned(N_BURST,12); -- Header size - i_head(95 DOWNTO 80)<=x"0000"; -- Attributes. TBD - i_head(80)<=i_inter; - i_head(81)<=i_flm; - i_head(82)<=i_hdown; - i_head(83)<=i_vdown; - i_head(84)<=i_mode(3); - i_head(87 DOWNTO 85)<=i_count; - i_head(79 DOWNTO 64)<="0000" & to_unsigned(i_hrsize,12); -- Image width - i_head(63 DOWNTO 48)<="0000" & to_unsigned(i_vrsize,12); -- Image height - i_head(47 DOWNTO 32)<= - to_unsigned(N_BURST * i_hburst,16); -- Line Length. Bytes - i_head(31 DOWNTO 16)<="0000" & to_unsigned(i_ohsize,12); - i_head(15 DOWNTO 0) <="0000" & to_unsigned(i_ovsize,12); - - ------------------------------------------------------ - i_ppix<=(i_r,i_g,i_b); - i_pvs<=i_vs; - i_pfl<=i_fl; - i_pde<=i_de; - i_pce<=i_ce; - - ------------------------------------------------------ - IF i_pce='1' THEN - ---------------------------------------------------- - i_vs_pre<=i_pvs; - i_de_pre<=i_pde; - i_fl_pre<=i_pfl; - - ---------------------------------------------------- - -- Detect interlaced video - IF NOT INTER THEN - i_intercnt<=0; - ELSIF i_pfl/=i_fl_pre THEN - i_intercnt<=3; - ELSIF i_pvs='1' AND i_vs_pre='0' AND i_intercnt>0 THEN - i_intercnt<=i_intercnt-1; - END IF; - i_inter<=to_std_logic(i_intercnt>0); - - ---------------------------------------------------- - IF i_pvs='1' AND i_vs_pre='0' THEN - i_sof<='1'; - END IF; - - IF i_pde='1' AND i_de_pre='0' THEN - i_flm<=i_pfl; - END IF; - - IF i_pde='1' AND i_sof='1' THEN - i_sof<='0'; - i_vcpt<=0; - IF i_inter='1' AND i_flm='0' AND i_half='0' AND INTER THEN - i_line<='1'; - i_adrsi<=to_unsigned(N_BURST * i_hburst,32) + - to_unsigned(N_BURST * to_integer( - unsigned'("00") & to_std_logic(HEADER)),32); - ELSE - i_line<='0'; - i_adrsi<=to_unsigned(N_BURST * to_integer( - unsigned'("00") & to_std_logic(HEADER)),32); - END IF; - END IF; - - i_ven<=to_std_logic(i_hcpt>=i_hmin AND i_hcpt<=i_hmax AND - i_vcpt>=i_vmin AND i_vcpt<=i_vmax); - - -- Detects end of frame for triple buffering. - i_endframe0<=i_vs AND (NOT i_inter OR i_flm); - i_endframe1<=i_vs AND (NOT i_inter OR NOT i_flm); - - i_vss<=to_std_logic(i_vcpt>=i_vmin AND i_vcpt<=i_vmax); - - ---------------------------------------------------- - IF i_pde='1' AND i_de_pre='0' THEN - i_vimax<=i_vcpt; - i_hcpt<=0; - ELSE - i_hcpt<=(i_hcpt+1) MOD 4096; - END IF; - - IF i_pde='0' AND i_de_pre='1' THEN - i_himax<=i_hcpt; - END IF; - - IF i_iauto='1' THEN - -- Auto-size - i_hmin<=0; - i_hmax<=i_himax; - i_vmin<=0; - IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN - i_vmax<=i_vimax; - END IF; - ELSE - -- Forced image - i_hmin<=himin; -- - i_hmax<=himax; -- - i_vmin<=vimin; -- - IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN - i_vmax<=vimax; -- - END IF; - END IF; - - IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN - i_vdmax<=i_vimax; - END IF; - i_hdmax<=i_himax; - - IF i_format="00" OR i_format="11" THEN -- 16bpp - i_hburst<=(i_hrsize*2 + N_BURST - 1) / N_BURST; - ELSIF i_format="01" THEN -- 24bpp - i_hburst<=(i_hrsize*3 + N_BURST - 1) / N_BURST; - ELSE -- 32bpp - i_hburst<=(i_hrsize*4 + N_BURST - 1) / N_BURST; - END IF; - ---------------------------------------------------- - i_mode<=mode; -- - i_format<=format; -- - - -- Downscaling : Nearest or bilinear - i_bil<=to_std_logic(i_mode(2 DOWNTO 0)/="000" AND DOWNSCALE); - - i_hdown<=to_std_logic(i_hsize>i_ohsize AND DOWNSCALE); --H downscale - i_vdown<=to_std_logic(i_vsize>i_ovsize AND DOWNSCALE); --V downscale - - ---------------------------------------------------- - i_hsize <=(4096+i_hmax-i_hmin+1) MOD 4096; - i_vmaxmin<=(4096+i_vmax-i_vmin+1) MOD 4096; - - IF i_inter='0' THEN - -- Non interlaced - i_vsize<=i_vmaxmin; - i_half <='0'; - ELSIF i_ovsize<2*i_vmaxmin THEN - -- Interlaced, but downscaling, use only half frames - i_vsize<=i_vmaxmin; - i_half <='1'; - ELSE - -- Interlaced : Double image height - i_vsize<=2*i_vmaxmin; - i_half <='0'; - END IF; - - i_ohsize<=o_hsize; -- - i_ovsize<=o_vsize; -- - - ---------------------------------------------------- - -- Downscaling vertical - i_divstart<='0'; - IF i_de_delay=16 THEN - IF (i_vacc + 2*i_ovsize) < 2*i_vsize THEN - i_vacc<=(i_vacc + 2*i_ovsize) MOD 8192; - i_vnp<='0'; - ELSE - i_vacc<=(i_vacc + 2*i_ovsize - 2*i_vsize + 8192) MOD 8192; - i_vnp<='1'; - END IF; - i_divstart<='1'; - - IF i_vcpt=i_vmin THEN - i_vacc<=(i_vsize - i_ovsize + 8192) MOD 8192; - i_vnp<='1'; -- - END IF; - END IF; - - IF i_vdown='0' THEN - i_vnp<='1'; - END IF; - - -- Downscaling horizontal - IF i_ven='1' THEN - IF i_hacc + 2*i_ohsize < 2*i_hsize THEN - i_hacc<=(i_hacc + 2*i_ohsize) MOD 8192; - i_hnp<='0'; -- Skip. pix. - ELSE - i_hacc<=(i_hacc + 2*i_ohsize - 2*i_hsize + 8192) MOD 8192; - i_hnp<='1'; - END IF; - END IF; - IF i_hdown='0' THEN - i_hnp<='1'; - END IF; - - ---------------------------------------------------- - -- Downscaling interpolation - i_hpixp<=i_ppix; - i_hpix0<=i_hpixp; - i_hpix1<=i_hpix0; - i_hpix2<=i_hpix1; - i_hpix3<=i_hpix2; - i_hpix4<=i_hpix3; - - i_hnp1<=i_hnp; i_hnp2<=i_hnp1; i_hnp3<=i_hnp2; i_hnp4<=i_hnp3; - i_ven1<=i_ven; i_ven2<=i_ven1; i_ven3<=i_ven2; i_ven4<=i_ven3; - i_ven5<=i_ven4; i_ven6<=i_ven5; - - -- C1 : DIV 1. Pipelined 4 bits non-restoring divider - dir_v:=x"000"; - div_v:=to_unsigned(i_hacc * 16,17); - - div_v:=div_v-to_unsigned(i_hsize*16,17); - dir_v(11):=NOT div_v(16); - IF div_v(16)='0' THEN - div_v:=div_v-to_unsigned(i_hsize*8,17); - ELSE - div_v:=div_v+to_unsigned(i_hsize*8,17); - END IF; - dir_v(10):=NOT div_v(16); - i_div<=div_v; - i_dir<=dir_v; - - -- C2 : DIV 2. - div_v:=i_div; - dir_v:=i_dir; - IF div_v(16)='0' THEN - div_v:=div_v-to_unsigned(i_hsize*4,17); - ELSE - div_v:=div_v+to_unsigned(i_hsize*4,17); - END IF; - dir_v(9):=NOT div_v(16); - IF div_v(16)='0' THEN - div_v:=div_v-to_unsigned(i_hsize*2,17); - ELSE - div_v:=div_v+to_unsigned(i_hsize*2,17); - END IF; - dir_v(8):=NOT div_v(16); - i_h_frac<=dir_v; - - -- C4 : Horizontal Bilinear - IF i_bil='0' THEN - frac_v:=near_frac(i_h_frac); - ELSE - frac_v:=bil_frac(i_h_frac); - END IF; - - i_h_bil_t<=bil_calc(frac_v,(i_hpix2,i_hpix2,i_hpix3,i_hpix3)); - i_hpix.r<=bound(i_h_bil_t.r,8+FRAC); - i_hpix.g<=bound(i_h_bil_t.g,8+FRAC); - i_hpix.b<=bound(i_h_bil_t.b,8+FRAC); - - IF i_hdown='0' THEN - i_hpix<=i_hpix4; - END IF; - - -- C5 : Vertical Bilinear - IF i_bil='0' THEN - frac_v:=near_frac(i_v_frac(11 DOWNTO 0)); - ELSE - frac_v:=bil_frac(i_v_frac(11 DOWNTO 0)); - END IF; - - bil_t_v:=bil_calc(frac_v,(i_hpix,i_hpix,i_ldrm,i_ldrm)); - i_pix.r<=bound(bil_t_v.r,8+FRAC); - i_pix.g<=bound(bil_t_v.g,8+FRAC); - i_pix.b<=bound(bil_t_v.b,8+FRAC); - - IF i_vdown='0' THEN - i_pix<=i_hpix; - END IF; - - ---------------------------------------------------- - -- VNP : Vert. downscaling line enable - -- HNP : Horiz. downscaling pix. enable - -- VEN : Enable pixel within displayed window - - IF (i_hnp4='1' AND i_ven6='1') OR i_pushend='1' THEN - i_shift<=shift_ishift(i_shift,i_pix,i_format); - i_dw<=shift_ipack(i_dw,i_acpt,i_shift,i_pix,i_format); - - IF shift_inext(i_acpt,i_format) AND i_vnp='1' THEN - i_push<='1'; - i_pushend<='0'; - END IF; - i_acpt<=(i_acpt+1) MOD 16; - END IF; - - IF i_ven6='1' AND i_ven5='0' AND i_vnp='1' THEN - i_pushend<='1'; - END IF; - i_pushend2<=i_pushend; - - IF i_pushend2='1' AND i_pushend='0' THEN - i_eol<='1'; - END IF; - - IF i_pde='0' AND i_de_pre='1' THEN - i_de_delay<=0; - ELSIF i_de_delay<18 THEN - i_de_delay<=i_de_delay+1; - END IF; - - IF i_de_delay=16 THEN - i_lwad<=0; - i_lrad<=0; - i_vcpt<=i_vcpt+1; - i_hacc<=(i_hsize - i_ohsize + 8192) MOD 8192; - i_hbcpt<=0; - END IF; - IF i_de_delay=17 THEN - i_acpt<=0; - i_wad<=2*BLEN-1; - END IF; - - IF i_pvs='0' AND i_vs_pre='1' THEN - -- Push header - i_pushhead<=to_std_logic(HEADER); - END IF; - - END IF; -- IF i_pce='1' - - ------------------------------------------------------ - -- Push pixels to downscaling line buffer - i_lwr<=i_hnp4 AND i_ven5 AND i_pce; - IF i_lwr='1' THEN - i_lwad<=(i_lwad+1) MOD OHRES; - END IF; - i_ldw<=i_hpix; - - IF i_hnp3='1' AND i_ven4='1' AND i_pce='1' THEN - i_lrad<=(i_lrad+1) MOD OHRES; - END IF; - - ------------------------------------------------------ - -- Write image properties header - i_pushhead2<=i_pushhead; i_pushhead3<=i_pushhead2; - - IF i_pushhead='1' AND i_freeze='0' THEN - i_dw<=i_head(127 DOWNTO 128-N_DW); - i_count<=i_count+1; - i_wr<='1'; - i_wad<=0; - IF N_DW=128 THEN - i_alt<='0'; - i_wreq<=NOT i_freeze; - i_adrs<=(OTHERS =>'0'); - END IF; - END IF; - - IF i_pushhead2='1' AND i_freeze='0' AND N_DW=64 THEN - i_dw<=i_head(N_DW-1 DOWNTO 0); - i_wr<='1'; - i_wad<=1; - i_wreq<=NOT i_freeze; - i_alt<='0'; - i_adrs<=(OTHERS =>'0'); - END IF; - IF i_pushhead3='1' THEN - i_wad<=BLEN-1; - END IF; - - ------------------------------------------------------ - -- Push pixels to DPRAM - IF i_push='1' AND i_freeze='0' THEN - i_wr<='1'; - i_wad<=(i_wad+1) MOD (BLEN*2); - IF (i_wad+1) MOD BLEN=BLEN-1 AND i_hbcpt 12 - IDividers:PROCESS (i_clk,i_reset_na) IS - BEGIN - IF i_reset_na='0' THEN + ----------------------------------------------------------------------------- + i_reset_na<='0' WHEN reset_na='0' ELSE '1' WHEN rising_edge(i_clk); + o_reset_na<='0' WHEN reset_na='0' ELSE '1' WHEN rising_edge(o_clk); + avl_reset_na<='0' WHEN reset_na='0' ELSE '1' WHEN rising_edge(avl_clk); + + ----------------------------------------------------------------------------- + -- Input pixels FIFO and shreg + InAT:PROCESS(i_clk,i_reset_na) IS + CONSTANT Z : unsigned(FRAC-1 DOWNTO 0):=(OTHERS =>'0'); + VARIABLE frac_v : unsigned(FRAC-1 DOWNTO 0); + VARIABLE div_v : unsigned(16 DOWNTO 0); + VARIABLE dir_v : unsigned(11 DOWNTO 0); + VARIABLE bil_t_v : type_bil_t; + BEGIN + IF i_reset_na='0' THEN + i_write<='0'; + + ELSIF rising_edge(i_clk) THEN + i_push<='0'; + i_pushhead<='0'; + i_eol<='0'; -- End Of Line + i_freeze <=freeze; -- + i_iauto<=iauto; -- + i_wreq<='0'; + i_wr<='0'; + + ------------------------------------------------------ + i_head(127 DOWNTO 120)<=x"01"; -- Header type + i_head(119 DOWNTO 112)<="000000" & i_format; -- Header format + i_head(111 DOWNTO 96)<="0000" & to_unsigned(N_BURST,12); -- Header size + i_head(95 DOWNTO 80)<=x"0000"; -- Attributes. TBD + i_head(80)<=i_inter; + i_head(81)<=i_flm; + i_head(82)<=i_hdown; + i_head(83)<=i_vdown; + i_head(84)<=i_mode(3); + i_head(87 DOWNTO 85)<=i_count; + i_head(79 DOWNTO 64)<="0000" & to_unsigned(i_hrsize,12); -- Image width + i_head(63 DOWNTO 48)<="0000" & to_unsigned(i_vrsize,12); -- Image height + i_head(47 DOWNTO 32)<= to_unsigned(N_BURST * i_hburst,16); -- Line Length. Bytes + i_head(31 DOWNTO 16)<="0000" & to_unsigned(i_ohsize,12); + i_head(15 DOWNTO 0) <="0000" & to_unsigned(i_ovsize,12); + + ------------------------------------------------------ + i_ppix<=(i_r,i_g,i_b); + i_pvs<=i_vs; + i_pfl<=i_fl; + i_pde<=i_de; + i_pce<=i_ce; + + ------------------------------------------------------ + IF i_pce='1' THEN + ---------------------------------------------------- + i_vs_pre<=i_pvs; + i_de_pre<=i_pde; + i_fl_pre<=i_pfl; + + ---------------------------------------------------- + -- Detect interlaced video + IF NOT INTER THEN + i_intercnt<=0; + ELSIF i_pfl/=i_fl_pre THEN + i_intercnt<=3; + ELSIF i_pvs='1' AND i_vs_pre='0' AND i_intercnt>0 THEN + i_intercnt<=i_intercnt-1; + END IF; + i_inter<=to_std_logic(i_intercnt>0); + + ---------------------------------------------------- + IF i_pvs='1' AND i_vs_pre='0' THEN + i_sof<='1'; + END IF; + + IF i_pde='1' AND i_de_pre='0' THEN + i_flm<=i_pfl; + END IF; + + IF i_pde='1' AND i_sof='1' THEN + i_sof<='0'; + i_vcpt<=0; + IF i_inter='1' AND i_flm='0' AND i_half='0' AND INTER THEN + i_line<='1'; + i_adrsi<=to_unsigned(N_BURST * i_hburst,32) + + to_unsigned(N_BURST * to_integer( + unsigned'("00") & to_std_logic(HEADER)),32); + ELSE + i_line<='0'; + i_adrsi<=to_unsigned(N_BURST * to_integer( + unsigned'("00") & to_std_logic(HEADER)),32); + END IF; + END IF; + + i_ven<=to_std_logic(i_hcpt>=i_hmin AND i_hcpt<=i_hmax AND + i_vcpt>=i_vmin AND i_vcpt<=i_vmax); + + -- Detects end of frame for triple buffering. + i_endframe0<=i_vs AND (NOT i_inter OR i_flm); + i_endframe1<=i_vs AND (NOT i_inter OR NOT i_flm); + + i_vss<=to_std_logic(i_vcpt>=i_vmin AND i_vcpt<=i_vmax); + + ---------------------------------------------------- + IF i_pde='1' AND i_de_pre='0' THEN + i_vimax<=i_vcpt; + i_hcpt<=0; + ELSE + i_hcpt<=(i_hcpt+1) MOD 4096; + END IF; + + IF i_pde='0' AND i_de_pre='1' THEN + i_himax<=i_hcpt; + END IF; + + IF i_iauto='1' THEN + -- Auto-size + i_hmin<=0; + i_hmax<=i_himax; + i_vmin<=0; + IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN + i_vmax<=i_vimax; + END IF; + ELSE + -- Forced image + i_hmin<=himin; -- + i_hmax<=himax; -- + i_vmin<=vimin; -- + IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN + i_vmax<=vimax; -- + END IF; + END IF; + + IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN + i_vdmax<=i_vimax; + END IF; + i_hdmax<=i_himax; + + IF i_format="00" OR i_format="11" THEN -- 16bpp + i_hburst<=(i_hrsize*2 + N_BURST - 1) / N_BURST; + ELSIF i_format="01" THEN -- 24bpp + i_hburst<=(i_hrsize*3 + N_BURST - 1) / N_BURST; + ELSE -- 32bpp + i_hburst<=(i_hrsize*4 + N_BURST - 1) / N_BURST; + END IF; + ---------------------------------------------------- + i_mode<=mode; -- + i_format<=format; -- + + -- Downscaling : Nearest or bilinear + i_bil<=to_std_logic(i_mode(2 DOWNTO 0)/="000" AND NOT DOWNSCALE_NN); + + i_hdown<=to_std_logic(i_hsize>i_ohsize AND DOWNSCALE); --H downscale + i_vdown<=to_std_logic(i_vsize>i_ovsize AND DOWNSCALE); --V downscale + + ---------------------------------------------------- + i_hsize <=(4096+i_hmax-i_hmin+1) MOD 4096; + i_vmaxmin<=(4096+i_vmax-i_vmin+1) MOD 4096; + + IF i_inter='0' THEN + -- Non interlaced + i_vsize<=i_vmaxmin; + i_half <='0'; + ELSIF i_ovsize<2*i_vmaxmin THEN + -- Interlaced, but downscaling, use only half frames + i_vsize<=i_vmaxmin; + i_half <='1'; + ELSE + -- Interlaced : Double image height + i_vsize<=2*i_vmaxmin; + i_half <='0'; + END IF; + + i_ohsize<=o_hsize; -- + i_ovsize<=o_vsize; -- + + ---------------------------------------------------- + -- Downscaling vertical + i_divstart<='0'; + IF i_de_delay=16 THEN + IF (i_vacc + 2*i_ovsize) < 2*i_vsize THEN + i_vacc<=(i_vacc + 2*i_ovsize) MOD 8192; + i_vnp<='0'; + ELSE + i_vacc<=(i_vacc + 2*i_ovsize - 2*i_vsize + 8192) MOD 8192; + i_vnp<='1'; + END IF; + i_divstart<='1'; + + IF i_vcpt=i_vmin THEN + i_vacc<=(i_vsize - i_ovsize + 8192) MOD 8192; + i_vnp<='1'; -- + END IF; + END IF; + + IF i_vdown='0' THEN + i_vnp<='1'; + END IF; + + -- Downscaling horizontal + IF i_ven='1' THEN + IF i_hacc + 2*i_ohsize < 2*i_hsize THEN + i_hacc<=(i_hacc + 2*i_ohsize) MOD 8192; + i_hnp<='0'; -- Skip. pix. + ELSE + i_hacc<=(i_hacc + 2*i_ohsize - 2*i_hsize + 8192) MOD 8192; + i_hnp<='1'; + END IF; + END IF; + IF i_hdown='0' THEN + i_hnp<='1'; + END IF; + + ---------------------------------------------------- + -- Downscaling interpolation + i_hpixp<=i_ppix; + i_hpix0<=i_hpixp; + i_hpix1<=i_hpix0; + i_hpix2<=i_hpix1; + i_hpix3<=i_hpix2; + i_hpix4<=i_hpix3; + + i_hnp1<=i_hnp; i_hnp2<=i_hnp1; i_hnp3<=i_hnp2; i_hnp4<=i_hnp3; + i_ven1<=i_ven; i_ven2<=i_ven1; i_ven3<=i_ven2; i_ven4<=i_ven3; + i_ven5<=i_ven4; i_ven6<=i_ven5; + + -- C1 : DIV 1. Pipelined 4 bits non-restoring divider + dir_v:=x"000"; + div_v:=to_unsigned(i_hacc * 16,17); + + div_v:=div_v-to_unsigned(i_hsize*16,17); + dir_v(11):=NOT div_v(16); + IF div_v(16)='0' THEN + div_v:=div_v-to_unsigned(i_hsize*8,17); + ELSE + div_v:=div_v+to_unsigned(i_hsize*8,17); + END IF; + dir_v(10):=NOT div_v(16); + i_div<=div_v; + i_dir<=dir_v; + + -- C2 : DIV 2. + div_v:=i_div; + dir_v:=i_dir; + IF div_v(16)='0' THEN + div_v:=div_v-to_unsigned(i_hsize*4,17); + ELSE + div_v:=div_v+to_unsigned(i_hsize*4,17); + END IF; + dir_v(9):=NOT div_v(16); + + IF div_v(16)='0' THEN + div_v:=div_v-to_unsigned(i_hsize*2,17); + ELSE + div_v:=div_v+to_unsigned(i_hsize*2,17); + END IF; + dir_v(8):=NOT div_v(16); + i_h_frac<=dir_v; + + -- C4 : Horizontal Bilinear + IF i_bil='0' THEN + frac_v:=near_frac(i_h_frac); + i_h_bil_t<=near_calc(frac_v,(i_hpix2,i_hpix2,i_hpix3,i_hpix3)); + ELSE + frac_v:=bil_frac(i_h_frac); + i_h_bil_t<=bil_calc(frac_v,(i_hpix2,i_hpix2,i_hpix3,i_hpix3)); + END IF; + + i_hpix.r<=bound(i_h_bil_t.r,8+FRAC); + i_hpix.g<=bound(i_h_bil_t.g,8+FRAC); + i_hpix.b<=bound(i_h_bil_t.b,8+FRAC); + + IF i_hdown='0' THEN + i_hpix<=i_hpix4; + END IF; + + -- C5 : Vertical Bilinear + IF i_bil='0' THEN + frac_v:=near_frac(i_v_frac(11 DOWNTO 0)); + bil_t_v:=near_calc(frac_v,(i_hpix,i_hpix,i_ldrm,i_ldrm)); + ELSE + frac_v:=bil_frac(i_v_frac(11 DOWNTO 0)); + bil_t_v:=bil_calc(frac_v,(i_hpix,i_hpix,i_ldrm,i_ldrm)); + END IF; + + i_pix.r<=bound(bil_t_v.r,8+FRAC); + i_pix.g<=bound(bil_t_v.g,8+FRAC); + i_pix.b<=bound(bil_t_v.b,8+FRAC); + + IF i_vdown='0' THEN + i_pix<=i_hpix; + END IF; + + ---------------------------------------------------- + -- VNP : Vert. downscaling line enable + -- HNP : Horiz. downscaling pix. enable + -- VEN : Enable pixel within displayed window + + IF (i_hnp4='1' AND i_ven6='1') OR i_pushend='1' THEN + i_shift<=shift_ishift(i_shift,i_pix,i_format); + i_dw<=shift_ipack(i_dw,i_acpt,i_shift,i_pix,i_format); + + IF shift_inext(i_acpt,i_format) AND i_vnp='1' THEN + i_push<='1'; + i_pushend<='0'; + END IF; + i_acpt<=(i_acpt+1) MOD 16; + END IF; + + IF i_ven6='1' AND i_ven5='0' AND i_vnp='1' THEN + i_pushend<='1'; + END IF; + i_pushend2<=i_pushend; + + IF i_pushend2='1' AND i_pushend='0' THEN + i_eol<='1'; + END IF; + + IF i_pde='0' AND i_de_pre='1' THEN + i_de_delay<=0; + ELSIF i_de_delay<18 THEN + i_de_delay<=i_de_delay+1; + END IF; + + IF i_de_delay=16 THEN + i_lwad<=0; + i_lrad<=0; + i_vcpt<=i_vcpt+1; + i_hacc<=(i_hsize - i_ohsize + 8192) MOD 8192; + i_hbcpt<=0; + END IF; + IF i_de_delay=17 THEN + i_acpt<=0; + i_wad<=2*BLEN-1; + END IF; + + IF i_pvs='0' AND i_vs_pre='1' THEN + -- Push header + i_pushhead<=to_std_logic(HEADER); + END IF; + + END IF; -- IF i_pce='1' + + ------------------------------------------------------ + -- Push pixels to downscaling line buffer + i_lwr<=i_hnp4 AND i_ven5 AND i_pce; + IF i_lwr='1' THEN + i_lwad<=(i_lwad+1) MOD OHRES; + END IF; + i_ldw<=i_hpix; + + IF i_hnp3='1' AND i_ven4='1' AND i_pce='1' THEN + i_lrad<=(i_lrad+1) MOD OHRES; + END IF; + + ------------------------------------------------------ + -- Write image properties header + i_pushhead2<=i_pushhead; i_pushhead3<=i_pushhead2; + + IF i_pushhead='1' AND i_freeze='0' THEN + i_dw<=i_head(127 DOWNTO 128-N_DW); + i_count<=i_count+1; + i_wr<='1'; + i_wad<=0; + IF N_DW=128 THEN + i_alt<='0'; + i_wreq<=NOT i_freeze; + i_adrs<=(OTHERS =>'0'); + END IF; + END IF; + + IF i_pushhead2='1' AND i_freeze='0' AND N_DW=64 THEN + i_dw<=i_head(N_DW-1 DOWNTO 0); + i_wr<='1'; + i_wad<=1; + i_wreq<=NOT i_freeze; + i_alt<='0'; + i_adrs<=(OTHERS =>'0'); + END IF; + IF i_pushhead3='1' THEN + i_wad<=BLEN-1; + END IF; + + ------------------------------------------------------ + -- Push pixels to DPRAM + IF i_push='1' AND i_freeze='0' THEN + i_wr<='1'; + i_wad<=(i_wad+1) MOD (BLEN*2); + IF (i_wad+1) MOD BLEN=BLEN-1 AND i_hbcpt 12 + IDividers:PROCESS (i_clk,i_reset_na) IS + BEGIN + IF i_reset_na='0' THEN --pragma synthesis_off - i_v_frac<=x"000"; + i_v_frac<=x"000"; --pragma synthesis_on - NULL; - ELSIF rising_edge(i_clk) THEN - i_vdivi<=to_unsigned(2*i_vsize,13); - i_vdivr<=to_unsigned(i_vacc*4096,25); - - ------------------------------------------------------ - IF i_divstart='1' THEN - i_divcpt<=0; - i_divrun<='1'; - - ELSIF i_divrun='1' THEN - ---------------------------------------------------- - IF i_divcpt=6 THEN - i_divrun<='0'; - i_v_frac<=i_vdivr(4 DOWNTO 0) & NOT i_vdivr(24) & "000000"; - ELSE - i_divcpt<=i_divcpt+1; - END IF; - - IF i_vdivr(24)='0' THEN - i_vdivr(24 DOWNTO 12)<=i_vdivr(23 DOWNTO 11) - i_vdivi; - ELSE - i_vdivr(24 DOWNTO 12)<=i_vdivr(23 DOWNTO 11) + i_vdivi; - END IF; - i_vdivr(11 DOWNTO 0)<=i_vdivr(10 DOWNTO 0) & NOT i_vdivr(24); - - ---------------------------------------------------- - END IF; - END IF; - END PROCESS IDividers; + NULL; + ELSIF rising_edge(i_clk) THEN + i_vdivi<=to_unsigned(2*i_vsize,13); + i_vdivr<=to_unsigned(i_vacc*4096,25); - ----------------------------------------------------------------------------- - -- DPRAM Input. Double buffer for RAM bursts. - PROCESS (i_clk) IS - BEGIN - IF rising_edge(i_clk) THEN - IF i_wr='1' THEN - i_dpram(i_wad)<=i_dw; - END IF; - END IF; - END PROCESS; - - avl_dr<=i_dpram(avl_rad_c) WHEN rising_edge(avl_clk); - - -- Line buffer for downscaling with interpolation - DownLine:IF DOWNSCALE GENERATE - ILBUF:PROCESS(i_clk) IS - BEGIN - IF rising_edge(i_clk) THEN - IF i_lwr='1' THEN - i_mem(i_lwad MOD IHRES)<=i_ldw; - END IF; - IF i_pce='1' THEN - i_ldrm<=i_mem(i_lrad MOD IHRES); - END IF; - END IF; - END PROCESS ILBUF; - END GENERATE DownLine; - - ----------------------------------------------------------------------------- - -- AVALON interface - Avaloir:PROCESS(avl_clk,avl_reset_na) IS - VARIABLE adr_v : unsigned(31 DOWNTO 0); - BEGIN - IF avl_reset_na='0' THEN - avl_state<=sIDLE; - avl_write_sr<='0'; - avl_read_sr<='0'; - avl_readdataack<='0'; - avl_readack<='0'; - - ELSIF rising_edge(avl_clk) THEN - ---------------------------------- - avl_write_sync<=i_write; -- - avl_write_sync2<=avl_write_sync; - avl_write_pulse<=avl_write_sync XOR avl_write_sync2; - IF avl_write_pulse='1' THEN - avl_wadrs <=i_wadrs AND (RAMSIZE - 1); -- - avl_wline <=i_wline; -- - avl_walt <=i_walt; -- - END IF; - - ---------------------------------- - avl_read_sync<=o_read; -- - avl_read_sync2<=avl_read_sync; - avl_read_pulse<=avl_read_sync XOR avl_read_sync2; - avl_radrs <=o_adrs AND (RAMSIZE - 1); -- - avl_rline <=o_rline; -- - - -------------------------------------------- - avl_o_vs_sync<=o_vsv(0); -- - avl_o_vs<=avl_o_vs_sync; - - avl_fb_ena<=o_fb_ena; -- - IF avl_fb_ena='0' THEN - IF HEADER THEN - avl_o_offset0<=buf_offset(o_obuf0,RAMBASE,RAMSIZE) + N_BURST; -- - avl_o_offset1<=buf_offset(o_obuf1,RAMBASE,RAMSIZE) + N_BURST; -- - ELSE - avl_o_offset0<=buf_offset(o_obuf0,RAMBASE,RAMSIZE); -- - avl_o_offset1<=buf_offset(o_obuf1,RAMBASE,RAMSIZE); -- - END IF; - ELSIF avl_o_vs_sync='0' AND avl_o_vs='1' THEN - -- Copy framebuffer base address at VS falling edge - avl_o_offset0<=o_fb_base; -- - avl_o_offset1<=o_fb_base; -- - END IF; - - avl_i_offset0<=buf_offset(o_ibuf0,RAMBASE,RAMSIZE); -- - avl_i_offset1<=buf_offset(o_ibuf1,RAMBASE,RAMSIZE); -- - - -------------------------------------------- - avl_dw<=swap(unsigned(avl_readdata)); - avl_read_i<='0'; - avl_write_i<='0'; - - avl_write_sr<=(avl_write_sr OR avl_write_pulse) AND NOT avl_write_clr; - avl_read_sr <=(avl_read_sr OR avl_read_pulse) AND NOT avl_read_clr; - avl_write_clr<='0'; - avl_read_clr <='0'; - - avl_rad<=avl_rad_c; - - -------------------------------------------- - CASE avl_state IS - WHEN sIDLE => - IF avl_write_sr='1' THEN - avl_state<=sWRITE; - avl_write_clr<='1'; - IF avl_walt='0' THEN - avl_rad<=0; - ELSE - avl_rad<=BLEN; - END IF; - IF avl_wline='0' THEN - avl_address<=std_logic_vector( - avl_wadrs(N_AW+NB_LA-1 DOWNTO NB_LA) + - avl_i_offset0(N_AW+NB_LA-1 DOWNTO NB_LA)); - ELSE - avl_address<=std_logic_vector( - avl_wadrs(N_AW+NB_LA-1 DOWNTO NB_LA) + - avl_i_offset1(N_AW+NB_LA-1 DOWNTO NB_LA)); - END IF; - ELSIF avl_read_sr='1' THEN - avl_state<=sREAD; - avl_read_clr<='1'; - END IF; - - WHEN sWRITE => - avl_write_i<='1'; - IF avl_write_i='1' AND avl_waitrequest='0' THEN - IF (avl_rad MOD BLEN)=BLEN-1 THEN - avl_write_i<='0'; - avl_state<=sIDLE; - END IF; - END IF; - - WHEN sREAD => - IF avl_rline='0' THEN - adr_v:=avl_radrs + avl_o_offset0; - ELSE - adr_v:=avl_radrs + avl_o_offset1; - END IF; - avl_address<=std_logic_vector(adr_v(N_AW+NB_LA-1 DOWNTO NB_LA)); - - avl_read_i<='1'; - IF avl_read_i='1' AND avl_waitrequest='0' THEN - avl_state<=sIDLE; - avl_read_i<='0'; - avl_readack<=NOT avl_readack; - END IF; - END CASE; - - -------------------------------------------- - -- Pipelined data read - avl_wr<='0'; - IF avl_readdatavalid='1' THEN - avl_wr<='1'; - avl_wad<=(avl_wad+1) MOD (2*BLEN); - IF (avl_wad MOD BLEN)=BLEN-2 THEN - avl_readdataack<=NOT avl_readdataack; - END IF; - END IF; + ------------------------------------------------------ + IF i_divstart='1' THEN + i_divcpt<=0; + i_divrun<='1'; - IF avl_o_vs_sync='0' AND avl_o_vs='1' THEN - avl_wad<=2*BLEN-1; - END IF; - - -------------------------------------------- - END IF; - END PROCESS Avaloir; - - avl_read<=avl_read_i; - avl_write<=avl_write_i; - avl_writedata<=std_logic_vector(swap(avl_dr)); - avl_burstcount<=std_logic_vector(to_unsigned(BLEN,8)); - avl_byteenable<=(OTHERS =>'1'); - - avl_rad_c<=(avl_rad+1) MOD (2*BLEN) - WHEN avl_write_i='1' AND avl_waitrequest='0' ELSE avl_rad; - - ----------------------------------------------------------------------------- - -- DPRAM Output. Double buffer for RAM bursts. - PROCESS (avl_clk) IS - BEGIN - IF rising_edge(avl_clk) THEN - IF avl_wr='1' THEN - o_dpram(avl_wad)<=avl_dw; - END IF; - END IF; - END PROCESS; - - o_dr<=o_dpram(o_ad3) WHEN rising_edge(o_clk); - - ----------------------------------------------------------------------------- - -- Output Vertical Divider - -- Vfrac = Vacc / Vsize - ODivider:PROCESS (o_clk,o_reset_na) IS - BEGIN - IF o_reset_na='0' THEN + ELSIF i_divrun='1' THEN + ---------------------------------------------------- + IF i_divcpt=6 THEN + i_divrun<='0'; + i_v_frac<=i_vdivr(4 DOWNTO 0) & NOT i_vdivr(24) & "000000"; + ELSE + i_divcpt<=i_divcpt+1; + END IF; + + IF i_vdivr(24)='0' THEN + i_vdivr(24 DOWNTO 12)<=i_vdivr(23 DOWNTO 11) - i_vdivi; + ELSE + i_vdivr(24 DOWNTO 12)<=i_vdivr(23 DOWNTO 11) + i_vdivi; + END IF; + i_vdivr(11 DOWNTO 0)<=i_vdivr(10 DOWNTO 0) & NOT i_vdivr(24); + + ---------------------------------------------------- + END IF; + END IF; + END PROCESS IDividers; + + ----------------------------------------------------------------------------- + -- DPRAM Input. Double buffer for RAM bursts. + PROCESS (i_clk) IS + BEGIN + IF rising_edge(i_clk) THEN + IF i_wr='1' THEN + i_dpram(i_wad)<=i_dw; + END IF; + END IF; + END PROCESS; + + avl_dr<=i_dpram(avl_rad_c) WHEN rising_edge(avl_clk); + + -- Line buffer for downscaling with interpolation + DownLine:IF DOWNSCALE GENERATE + ILBUF:PROCESS(i_clk) IS + BEGIN + IF rising_edge(i_clk) THEN + IF i_lwr='1' THEN + i_mem(i_lwad MOD IHRES)<=i_ldw; + END IF; + IF i_pce='1' THEN + i_ldrm<=i_mem(i_lrad MOD IHRES); + END IF; + END IF; + END PROCESS ILBUF; + END GENERATE DownLine; + + ----------------------------------------------------------------------------- + -- AVALON interface + Avaloir:PROCESS(avl_clk,avl_reset_na) IS + VARIABLE adr_v : unsigned(31 DOWNTO 0); + BEGIN + IF avl_reset_na='0' THEN + avl_state<=sIDLE; + avl_write_sr<='0'; + avl_read_sr<='0'; + avl_readdataack<='0'; + avl_readack<='0'; + + ELSIF rising_edge(avl_clk) THEN + ---------------------------------- + avl_write_sync<=i_write; -- + avl_write_sync2<=avl_write_sync; + avl_write_pulse<=avl_write_sync XOR avl_write_sync2; + IF avl_write_pulse='1' THEN + avl_wadrs <=i_wadrs AND (RAMSIZE - 1); -- + avl_wline <=i_wline; -- + avl_walt <=i_walt; -- + END IF; + + ---------------------------------- + avl_read_sync<=o_read; -- + avl_read_sync2<=avl_read_sync; + avl_read_pulse<=avl_read_sync XOR avl_read_sync2; + avl_radrs <=o_adrs; -- + avl_rline <=o_rline; -- + + -------------------------------------------- + avl_o_vs_sync<=o_vsv(0); -- + avl_o_vs<=avl_o_vs_sync; + + avl_fb_ena<=o_fb_ena; -- + IF avl_fb_ena='0' THEN + IF HEADER THEN + avl_o_offset0<=buf_offset(o_obuf0,RAMBASE,RAMSIZE) + N_BURST; -- + avl_o_offset1<=buf_offset(o_obuf1,RAMBASE,RAMSIZE) + N_BURST; -- + ELSE + avl_o_offset0<=buf_offset(o_obuf0,RAMBASE,RAMSIZE); -- + avl_o_offset1<=buf_offset(o_obuf1,RAMBASE,RAMSIZE); -- + END IF; + ELSIF avl_o_vs_sync='0' AND avl_o_vs='1' THEN + -- Copy framebuffer base address at VS falling edge + avl_o_offset0<=o_fb_base; -- + avl_o_offset1<=o_fb_base; -- + END IF; + + avl_i_offset0<=buf_offset(o_ibuf0,RAMBASE,RAMSIZE); -- + avl_i_offset1<=buf_offset(o_ibuf1,RAMBASE,RAMSIZE); -- + + -------------------------------------------- + avl_dw<=swap(unsigned(avl_readdata)); + avl_read_i<='0'; + avl_write_i<='0'; + + avl_write_sr<=(avl_write_sr OR avl_write_pulse) AND NOT avl_write_clr; + avl_read_sr <=(avl_read_sr OR avl_read_pulse) AND NOT avl_read_clr; + avl_write_clr<='0'; + avl_read_clr <='0'; + + avl_rad<=avl_rad_c; + + -------------------------------------------- + CASE avl_state IS + WHEN sIDLE => + IF avl_write_sr='1' THEN + avl_state<=sWRITE; + avl_write_clr<='1'; + IF avl_walt='0' THEN + avl_rad<=0; + ELSE + avl_rad<=BLEN; + END IF; + IF avl_wline='0' THEN + avl_address<=std_logic_vector( + avl_wadrs(N_AW+NB_LA-1 DOWNTO NB_LA) + + avl_i_offset0(N_AW+NB_LA-1 DOWNTO NB_LA)); + ELSE + avl_address<=std_logic_vector( + avl_wadrs(N_AW+NB_LA-1 DOWNTO NB_LA) + + avl_i_offset1(N_AW+NB_LA-1 DOWNTO NB_LA)); + END IF; + ELSIF avl_read_sr='1' THEN + avl_state<=sREAD; + avl_read_clr<='1'; + END IF; + + WHEN sWRITE => + avl_write_i<='1'; + IF avl_write_i='1' AND avl_waitrequest='0' THEN + IF (avl_rad MOD BLEN)=BLEN-1 THEN + avl_write_i<='0'; + avl_state<=sIDLE; + END IF; + END IF; + + WHEN sREAD => + IF avl_rline='0' THEN + adr_v:=avl_radrs + avl_o_offset0; + ELSE + adr_v:=avl_radrs + avl_o_offset1; + END IF; + avl_address<=std_logic_vector(adr_v(N_AW+NB_LA-1 DOWNTO NB_LA)); + + avl_read_i<='1'; + IF avl_read_i='1' AND avl_waitrequest='0' THEN + avl_state<=sIDLE; + avl_read_i<='0'; + avl_readack<=NOT avl_readack; + END IF; + END CASE; + + -------------------------------------------- + -- Pipelined data read + avl_wr<='0'; + IF avl_readdatavalid='1' THEN + avl_wr<='1'; + avl_wad<=(avl_wad+1) MOD (2*BLEN); + IF (avl_wad MOD BLEN)=BLEN-2 THEN + avl_readdataack<=NOT avl_readdataack; + END IF; + END IF; + + IF avl_o_vs_sync='0' AND avl_o_vs='1' THEN + avl_wad<=2*BLEN-1; + END IF; + + -------------------------------------------- + END IF; + END PROCESS Avaloir; + + avl_read<=avl_read_i; + avl_write<=avl_write_i; + avl_writedata<=std_logic_vector(swap(avl_dr)); + avl_burstcount<=std_logic_vector(to_unsigned(BLEN,8)); + avl_byteenable<=(OTHERS =>'1'); + + avl_rad_c<=(avl_rad+1) MOD (2*BLEN) + WHEN avl_write_i='1' AND avl_waitrequest='0' ELSE avl_rad; + + ----------------------------------------------------------------------------- + -- DPRAM Output. Double buffer for RAM bursts. + PROCESS (avl_clk) IS + BEGIN + IF rising_edge(avl_clk) THEN + IF avl_wr='1' THEN + o_dpram(avl_wad)<=avl_dw; + END IF; + END IF; + END PROCESS; + + o_dr<=o_dpram(o_ad3) WHEN rising_edge(o_clk); + + ----------------------------------------------------------------------------- + -- Output Vertical Divider + -- Vfrac = Vacc / Vsize + ODivider:PROCESS (o_clk,o_reset_na) IS + BEGIN + IF o_reset_na='0' THEN --pragma synthesis_off - o_vfrac<=x"000"; + o_vfrac<=x"000"; --pragma synthesis_on - ELSIF rising_edge(o_clk) THEN - o_vdivi<=to_unsigned(2*o_vsize,13); - o_vdivr<=to_unsigned(o_vacc*4096,25); - ------------------------------------------------------ - IF o_divstart='1' THEN - o_divcpt<=0; - o_divrun<='1'; - - ELSIF o_divrun='1' THEN - ---------------------------------------------------- - IF o_divcpt=12 THEN - o_divrun<='0'; - o_vfrac<=o_vdivr(10 DOWNTO 0) & NOT o_vdivr(24); - ELSE - o_divcpt<=o_divcpt+1; - END IF; - - IF o_vdivr(24)='0' THEN - o_vdivr(24 DOWNTO 12)<=o_vdivr(23 DOWNTO 11) - o_vdivi; - ELSE - o_vdivr(24 DOWNTO 12)<=o_vdivr(23 DOWNTO 11) + o_vdivi; - END IF; - o_vdivr(11 DOWNTO 0)<=o_vdivr(10 DOWNTO 0) & NOT o_vdivr(24); - ---------------------------------------------------- - END IF; - END IF; - END PROCESS ODivider; - - ----------------------------------------------------------------------------- - Scalaire:PROCESS (o_clk,o_reset_na) IS - VARIABLE lev_inc_v,lev_dec_v : std_logic; - VARIABLE prim_v,last_v,bib_v : std_logic; - VARIABLE shift_v : unsigned(0 TO N_DW+15); - VARIABLE hpix_v : type_pix; - VARIABLE hcarry_v,vcarry_v : boolean; - VARIABLE dif_v : natural RANGE 0 TO 8*OHRES-1; - VARIABLE off_v : natural RANGE 0 TO 15; - BEGIN - IF o_reset_na='0' THEN - o_copy<=sWAIT; - o_state<=sDISP; - o_read_pre<='0'; - o_readlev<=0; - o_copylev<=0; - o_hsp<='0'; - - ELSIF rising_edge(o_clk) THEN - ------------------------------------------------------ - o_mode <=mode; -- ? - o_format <="0001" & format; -- ? - - o_run <=run; -- ? - - o_htotal <=htotal; -- ? - o_hsstart<=hsstart; -- ? - o_hsend <=hsend; -- ? - o_hdisp <=hdisp; -- ? - o_hmin <=hmin; -- ? - o_hmax <=hmax; -- ? - - o_vtotal <=vtotal; -- ? - o_vsstart<=vsstart; -- ? - o_vsend <=vsend; -- ? - o_vdisp <=vdisp; -- ? - o_vmin <=vmin; -- ? - o_vmax <=vmax; -- ? - - o_hsize <=o_hmax - o_hmin + 1; - o_vsize <=o_vmax - o_vmin + 1; - - -------------------------------------------- - -- Triple buffering. - -- For intelaced video, half frames are updated independently - -- Input : Toggle buffer at end of input frame - o_inter <=i_inter; -- - o_iendframe0<=i_endframe0; -- - o_iendframe02<=o_iendframe0; - IF o_iendframe0='1' AND o_iendframe02='0' THEN - o_ibuf0<=buf_next(o_ibuf0,o_obuf0); - o_bufup0<='1'; - END IF; - o_iendframe1<=i_endframe1; -- - o_iendframe12<=o_iendframe1; - IF o_iendframe1='1' AND o_iendframe12='0' THEN - o_ibuf1<=buf_next(o_ibuf1,o_obuf1); - o_bufup1<='1'; - END IF; - -- Output : Change framebuffer, and image properties, at VS falling edge - IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup1='1' THEN - o_obuf1<=buf_next(o_obuf1,o_ibuf1); - o_bufup1<='0'; - o_ihsize<=i_hrsize; -- - o_ivsize<=i_vrsize; -- - o_hdown<=i_hdown; -- - o_vdown<=i_vdown; -- - END IF; - -- Framebuffer mode. - IF o_fb_ena='1' THEN - o_ihsize<=o_fb_hsize; - o_ivsize<=o_fb_vsize; - o_format<=o_fb_format; - o_hdown<='0'; - o_vdown<='0'; - END IF; - - o_ihsize_temp <= o_ihsize * to_integer(o_format(2 DOWNTO 0) - 2); - o_ihsize_temp2 <= (o_ihsize_temp + N_BURST - 1); - o_hburst <= o_ihsize_temp2 / N_BURST; - - IF o_fb_ena='1' AND o_fb_stride /= 0 THEN - o_stride<=o_fb_stride; - ELSE - o_stride<=to_unsigned(o_ihsize_temp2,14); - o_stride(NB_BURST-1 DOWNTO 0)<=(OTHERS =>'0'); - END IF; - - IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup0='1' THEN - o_obuf0<=buf_next(o_obuf0,o_ibuf0); - o_bufup0<='0'; - END IF; - - IF o_inter='0' THEN - o_ibuf1<=o_ibuf0; - o_obuf1<=o_obuf0; - END IF; - - -- Triple buffer disabled - IF o_mode(3)='0' THEN - o_obuf0<=0; - o_obuf1<=0; - o_ibuf0<=0; - o_ibuf1<=0; - END IF; - - ------------------------------------------------------ - o_hmode<=o_mode; - IF o_hdown='1' AND DOWNSCALE THEN - -- Force nearest if downscaling : Downscaled framebuffer - o_hmode(2 DOWNTO 0)<="000"; - END IF; - - o_vmode<=o_mode; - IF o_vdown='1' AND DOWNSCALE THEN - -- Force nearest if downscaling : Downscaled framebuffer - o_vmode(2 DOWNTO 0)<="000"; - END IF; - - ------------------------------------------------------ - -- End DRAM READ - o_readack_sync<=avl_readack; -- - o_readack_sync2<=o_readack_sync; - o_readack<=o_readack_sync XOR o_readack_sync2; - - o_readdataack_sync<=avl_readdataack; -- - o_readdataack_sync2<=o_readdataack_sync; - o_readdataack<=o_readdataack_sync XOR o_readdataack_sync2; - - ------------------------------------------------------ - lev_inc_v:='0'; - lev_dec_v:='0'; - - -- acpt : Pixel position within current data word - -- dcpt : Destination image position - - -- Force preload 2 lines at top of screen - IF o_hsv(0)='1' AND o_hsv(1)='0' THEN - IF o_vcpt_pre3=o_vmin THEN - o_fload<=2; - o_bibu<='0'; - END IF; - o_hsp<='1'; - END IF; - - o_vpe<=to_std_logic(o_vcpt_pre=o_vmin); - o_divstart<='0'; - o_adrsa<='0'; - o_adrsb<=o_adrsa; - - o_vacc_ini<=(o_vsize - o_ivsize + 8192) MOD 8192; - o_hacc_ini<=(o_hsize + o_ihsize + 8192) MOD 8192; - - --Alternate phase - --o_vacc_ini<=o_ivsize; - --o_hacc_ini<=(2*o_hsize - o_ihsize + 8192) MOD 8192; - - CASE o_state IS - -------------------------------------------------- - WHEN sDISP => - IF o_hsp='1' THEN - o_state<=sHSYNC; - o_hsp<='0'; - END IF; - - -------------------------------------------------- - WHEN sHSYNC => - dif_v:=(o_vacc_next - 2*o_vsize + 16384) MOD 16384; - IF dif_v>=8192 THEN - o_vacc <=o_vacc_next; - o_vacc_next<=(o_vacc_next + 2*o_ivsize) MOD 8192; - vcarry_v:=false; - ELSE - o_vacc <=dif_v; - o_vacc_next<=(dif_v + 2*o_ivsize + 8192) MOD 8192; - vcarry_v:=true; - END IF; - o_divstart<='1'; - IF o_vcpt_pre2=o_vmin THEN - o_vacc <=o_vacc_ini; - o_vacc_next<=o_vacc_ini + 2*o_ivsize; - o_vacpt<=x"001"; - vcarry_v:=false; - END IF; - - IF vcarry_v THEN - o_vacpt<=o_vacpt+1; - END IF; - o_hbcpt<=0; -- Clear burst counter on line - IF (o_vpe='1' AND vcarry_v) OR o_fload>0 THEN - o_state<=sREAD; - ELSE - o_state<=sDISP; - END IF; - - WHEN sREAD => - -- Read a block - IF o_readlev<2 AND o_adrsb='1' THEN - lev_inc_v:='1'; - o_read_pre<=NOT o_read_pre; - o_state <=sWAITREAD; - o_bibu<=NOT o_bibu; - END IF; - prim_v:=to_std_logic(o_hbcpt=0); - last_v:=to_std_logic(o_hbcpt=o_hburst-1); - bib_v :=o_bibu; - off_v :=pixoffset(o_adrs + o_fb_base(NB_LA-1 DOWNTO 0),o_fb_format); - IF o_fb_ena='0' THEN - off_v:=0; - END IF; - o_adrsa<='1'; - - WHEN sWAITREAD => - IF o_readack='1' THEN - o_hbcpt<=o_hbcpt+1; - IF o_hbcpt=1 THEN - o_fload<=o_fload-1; - END IF; - END IF; - END IF; - - -------------------------------------------------- - END CASE; - - o_read<=o_read_pre AND o_run; - o_rline<=o_vacpt(0); -- Even/Odd line for interlaced video - - o_adrs_pre<=to_integer(o_vacpt) * to_integer(o_stride); - IF o_adrsa='1' THEN - IF o_fload=2 THEN - o_adrs<=to_unsigned(o_hbcpt * N_BURST,32); - o_alt<="1111"; - ELSIF o_fload=1 THEN - o_adrs<=to_unsigned(o_hbcpt * N_BURST,32) + o_stride; - o_alt<="0100"; - ELSE - o_adrs<=to_unsigned(o_adrs_pre + (o_hbcpt * N_BURST),32); - o_alt<=altx(o_vacpt(1 DOWNTO 0) + 1); - END IF; - END IF; - - ------------------------------------------------------ - -- Copy from buffered memory to pixel lines - o_sh<='0'; - CASE o_copy IS - WHEN sWAIT => - o_copyv(0)<='0'; - IF o_copylev>0 AND o_copyv(0)='0' THEN - o_copy<=sCOPY; - IF o_off(0)>0 AND o_primv(0)='1' THEN - o_copy<=sSHIFT; - END IF; - o_altx<=o_alt; - END IF; - o_adturn<='0'; - o_pshift<=o_off(0) -1; - IF o_primv(0)='1' THEN - -- First memcopy of a horizontal line, carriage return ! - o_ihsizem<=o_ihsize + o_off(0) - 2; - o_hacc <=o_hacc_ini; - o_hacc_next<=o_hacc_ini + 2*o_ihsize; - o_hacpt <=x"000"; - o_dcpt<=0; - o_dshi<=2; - o_acpt<=0; - o_first<='1'; - o_last<='0'; - END IF; - - IF o_bibv(0)='0' THEN - o_ad<=0; - ELSE - o_ad<=BLEN; - END IF; - - WHEN sSHIFT => - o_hacpt<=o_hacpt+1; - o_sh<='1'; - o_acpt<=(o_acpt+1) MOD 16; - IF shift_onext(o_acpt,o_format) THEN - o_ad<=(o_ad+1) MOD (2*BLEN); - END IF; - o_pshift<=o_pshift-1; - IF o_pshift=0 THEN - o_copy<=sCOPY; - END IF; - - WHEN sCOPY => - -- dshi : Force shift first two or three pixels of each line - IF o_dshi=0 THEN - dif_v:=(o_hacc_next - 2*o_hsize + (8*OHRES)) MOD (8*OHRES); - IF dif_v>=4*OHRES THEN - o_hacc<=o_hacc_next; - o_hacc_next<=o_hacc_next + 2*o_ihsize; - hcarry_v:=false; - ELSE - o_hacc<=dif_v; - o_hacc_next<=(dif_v + 2*o_ihsize + (4*OHRES)) MOD (4*OHRES); - hcarry_v:=true; - END IF; - o_dcpt<=(o_dcpt+1) MOD 4096; - ELSE - o_dshi<=o_dshi-1; - hcarry_v:=false; - END IF; - IF o_dshi<=1 THEN - o_copyv(0)<='1'; - END IF; - IF hcarry_v THEN - o_hacpt<=o_hacpt+1; - o_last <=to_std_logic(o_hacpt>=o_ihsizem); - END IF; - - IF hcarry_v OR o_dshi>0 THEN - o_sh<='1'; - o_acpt<=(o_acpt+1) MOD 16; - - -- Shift two more pixels to the right before ending line. - o_last1<=o_last; - o_last2<=o_last1; - - IF shift_onext(o_acpt,o_format) THEN - o_ad<=(o_ad+1) MOD (2*BLEN); - END IF; - - IF o_adturn='1' AND (shift_onext((o_acpt+1) MOD 16,o_format)) AND - (((o_ad MOD BLEN=0) AND o_lastv(0)='0') OR o_last2='1') THEN - o_copy<=sWAIT; - lev_dec_v:='1'; - END IF; - - IF o_ad MOD BLEN=4 THEN - o_adturn<='1'; - END IF; - END IF; - END CASE; - - o_acpt1<=o_acpt; o_acpt2<=o_acpt1; o_acpt3<=o_acpt2; o_acpt4<=o_acpt3; - o_ad1<=o_ad; o_ad2<=o_ad1; o_ad3<=o_ad2; - o_sh1<=o_sh; o_sh2<=o_sh1; o_sh3<=o_sh2; o_sh4<=o_sh3; - o_lastt1<=o_last; o_lastt2<=o_lastt1; o_lastt3<=o_lastt2; - - ------------------------------------------------------ - IF o_sh3='1' THEN - shift_v:=shift_opack(o_acpt4,o_shift,o_dr,o_format); - o_shift<=shift_v; - o_hpixs<=shift_opix(shift_v,o_format); - END IF; - - IF o_sh4='1' THEN - hpix_v:=o_hpixs; - IF o_format(4)='1' THEN -- Swap B <-> R - hpix_v:=(r=>o_hpixs.b,g=>o_hpixs.g,b=>o_hpixs.r); - END IF; - IF o_format(2 DOWNTO 0)="011" THEN - -- 8bpp indexed colour mode - hpix_v:=(r=>o_fb_pal_dr(23 DOWNTO 16),g=>o_fb_pal_dr(15 DOWNTO 8), - b=>o_fb_pal_dr(7 DOWNTO 0)); - END IF; - o_hpix0<=hpix_v; - o_hpix1<=o_hpix0; - o_hpix2<=o_hpix1; - o_hpix3<=o_hpix2; - - IF o_first='1' THEN - -- Left edge. Duplicate first pixel - o_hpix1<=hpix_v; - o_hpix2<=hpix_v; - o_first<='0'; - END IF; - IF o_lastt3='1' THEN - -- Right edge. Keep last pixel. - o_hpix0<=o_hpix0; - END IF; - END IF; - - ------------------------------------------------------ - -- lev_inc : read start - -- lev_dec : end of copy - -- READLEV : Number of ongoing Avalon Reads - IF lev_dec_v='0' AND lev_inc_v='1' THEN - o_readlev<=o_readlev+1; - ELSIF lev_dec_v='1' AND lev_inc_v='0' THEN - o_readlev<=o_readlev-1; - END IF; - - -- COPYLEV : Number of ongoing copies to line buffers - IF lev_dec_v='1' AND o_readdataack='0' THEN - o_copylev<=o_copylev-1; - ELSIF lev_dec_v='0' AND o_readdataack='1' THEN - o_copylev<=o_copylev+1; - END IF; - - -- FIFOs - IF lev_dec_v='1' THEN - o_primv(0 TO 1)<=o_primv(1 TO 2); -- First buffer of line - o_lastv(0 TO 1)<=o_lastv(1 TO 2); -- Last buffer of line - o_bibv (0 TO 1)<=o_bibv (1 TO 2); -- Double buffer select - o_off (0 TO 1)<=o_off (1 TO 2); -- Start offset - END IF; - - IF lev_inc_v='1' THEN - IF o_readlev=0 OR (o_readlev=1 AND lev_dec_v='1') THEN - o_primv(0)<=prim_v; - o_lastv(0)<=last_v; - o_bibv (0)<=bib_v; - o_off (0)<=off_v; - ELSIF (o_readlev=1 AND lev_dec_v='0') OR - (o_readlev=2 AND lev_dec_v='1') THEN - o_primv(1)<=prim_v; - o_lastv(1)<=last_v; - o_bibv (1)<=bib_v; - o_off (1)<=off_v; - END IF; - o_primv(2)<=prim_v; - o_lastv(2)<=last_v; - o_bibv (2)<=bib_v; - o_off (2)<=off_v; - END IF; - - ------------------------------------------------------ - END IF; - END PROCESS Scalaire; - - o_h_poly_a<=to_integer(o_hfrac1(11 DOWNTO 12-FRAC)); - o_v_poly_a<=to_integer(o_vfrac(11 DOWNTO 12-FRAC)); - - o_h_poly_dr<=o_h_poly(o_h_poly_a) WHEN rising_edge(o_clk); - o_v_poly_dr<=o_v_poly(o_v_poly_a) WHEN rising_edge(o_clk); - - -- Framebuffer palette - GenPal1:IF PALETTE GENERATE - Tempera1:PROCESS(pal1_clk) IS - BEGIN - IF rising_edge(pal1_clk) THEN - IF pal1_wr='1' THEN - pal1_mem(to_integer(pal1_a))<=pal1_dw; - END IF; - pal1_dr<=pal1_mem(to_integer(pal1_a)); - END IF; - END PROCESS; + ELSIF rising_edge(o_clk) THEN + o_vdivi<=to_unsigned(2*o_vsize,13); + o_vdivr<=to_unsigned(o_vacc*4096,25); + ------------------------------------------------------ + IF o_divstart='1' THEN + o_divcpt<=0; + o_divrun<='1'; - pal_idx <= shift_opack(o_acpt4,o_shift,o_dr,o_format)(0 TO 7); - pal_idx_lsb <= pal_idx(0) WHEN rising_edge(o_clk); - o_fb_pal_dr_x2 <= pal1_mem(to_integer(pal_idx(7 DOWNTO 1))) WHEN rising_edge(o_clk); - END GENERATE GenPal1; - - GenPal2:IF PALETTE and PALETTE2 GENERATE - Tempera2:PROCESS(pal2_clk) IS - BEGIN - IF rising_edge(pal2_clk) THEN - IF pal2_wr='1' THEN - pal2_mem(to_integer(pal2_a))<=pal2_dw; - END IF; - pal2_dr<=pal2_mem(to_integer(pal2_a)); - END IF; - END PROCESS; + ELSIF o_divrun='1' THEN + ---------------------------------------------------- + IF o_divcpt=12 THEN + o_divrun<='0'; + o_vfrac<=o_vdivr(10 DOWNTO 0) & NOT o_vdivr(24); + ELSE + o_divcpt<=o_divcpt+1; + END IF; - o_fb_pal_dr2 <= pal2_mem(to_integer(pal_idx(7 DOWNTO 0))) WHEN rising_edge(o_clk); - o_fb_pal_dr <= o_fb_pal_dr2 when pal_n = '1' else o_fb_pal_dr_x2(47 DOWNTO 24) WHEN pal_idx_lsb = '1' ELSE o_fb_pal_dr_x2(23 DOWNTO 0); - END GENERATE GenPal2; + IF o_vdivr(24)='0' THEN + o_vdivr(24 DOWNTO 12)<=o_vdivr(23 DOWNTO 11) - o_vdivi; + ELSE + o_vdivr(24 DOWNTO 12)<=o_vdivr(23 DOWNTO 11) + o_vdivi; + END IF; + o_vdivr(11 DOWNTO 0)<=o_vdivr(10 DOWNTO 0) & NOT o_vdivr(24); + ---------------------------------------------------- + END IF; + END IF; + END PROCESS ODivider; - GenPal1not2:IF PALETTE and not PALETTE2 GENERATE - o_fb_pal_dr <= o_fb_pal_dr_x2(47 DOWNTO 24) WHEN pal_idx_lsb = '1' ELSE o_fb_pal_dr_x2(23 DOWNTO 0); - END GENERATE GenPal1not2; - - GenNoPal:IF NOT PALETTE GENERATE - o_fb_pal_dr<=x"000000"; - END GENERATE GenNoPal; - - ----------------------------------------------------------------------------- - -- Polyphase ROMs - Polikarpov:PROCESS(poly_clk) IS - BEGIN - IF rising_edge(poly_clk) THEN - IF poly_wr='1' THEN - poly_tdw(8+9*(3-to_integer(poly_a(1 DOWNTO 0))) DOWNTO - 9*(3-to_integer(poly_a(1 DOWNTO 0))))<=poly_dw; - END IF; - - poly_h_wr<=poly_wr AND NOT poly_a(FRAC+2); - poly_v_wr<=poly_wr AND poly_a(FRAC+2); - poly_a2<=poly_a(FRAC+1 DOWNTO 2); - - IF poly_h_wr='1' THEN - o_h_poly(to_integer(poly_a2))<=poly_tdw; - END IF; - IF poly_v_wr='1' THEN - o_v_poly(to_integer(poly_a2))<=poly_tdw; - END IF; - END IF; - END PROCESS Polikarpov; - - ----------------------------------------------------------------------------- - -- Horizontal Scaler - HSCAL:PROCESS(o_clk) IS - VARIABLE div_v : unsigned(18 DOWNTO 0); - VARIABLE dir_v : unsigned(11 DOWNTO 0); - BEGIN - IF rising_edge(o_clk) THEN - -- Pipeline signals - ----------------------------------- - -- Pipelined 6 bits non-restoring divider. Cycle 1 - dir_v:=x"000"; - div_v:=to_unsigned(o_hacc * 64,19); - - div_v:=div_v-to_unsigned(o_hsize*64,19); - dir_v(11):=NOT div_v(18); - IF div_v(18)='0' THEN - div_v:=div_v-to_unsigned(o_hsize*32,19); - ELSE - div_v:=div_v+to_unsigned(o_hsize*32,19); - END IF; - dir_v(10):=NOT div_v(18); - o_div<=div_v; - o_dir<=dir_v; - - -- Cycle 2 - div_v:=o_div; - dir_v:=o_dir; - IF div_v(18)='0' THEN - div_v:=div_v-to_unsigned(o_hsize*16,19); - ELSE - div_v:=div_v+to_unsigned(o_hsize*16,19); - END IF; - dir_v( 9):=NOT div_v(18); + ----------------------------------------------------------------------------- + Scalaire:PROCESS (o_clk,o_reset_na) IS + VARIABLE lev_inc_v,lev_dec_v : std_logic; + VARIABLE prim_v,last_v,bib_v : std_logic; + VARIABLE shift_v : unsigned(0 TO N_DW+15); + VARIABLE hpix_v : type_pix; + VARIABLE hcarry_v,vcarry_v : boolean; + VARIABLE dif_v : natural RANGE 0 TO 8*OHRES-1; + VARIABLE off_v : natural RANGE 0 TO 15; + BEGIN + IF o_reset_na='0' THEN + o_copy<=sWAIT; + o_state<=sDISP; + o_read_pre<='0'; + o_readlev<=0; + o_copylev<=0; + o_hsp<='0'; - IF div_v(18)='0' THEN - div_v:=div_v-to_unsigned(o_hsize*8,19); - ELSE - div_v:=div_v+to_unsigned(o_hsize*8,19); - END IF; - dir_v(8):=NOT div_v(18); - o_div2<=div_v; - o_dir2<=dir_v; - - -- Cycle 3 - div_v:=o_div2; - dir_v:=o_dir2; - IF FRAC>4 THEN - IF div_v(18)='0' THEN - div_v:=div_v-to_unsigned(o_hsize*4,19); - ELSE - div_v:=div_v+to_unsigned(o_hsize*4,19); - END IF; - dir_v(7):=NOT div_v(18); - IF div_v(18)='0' THEN - div_v:=div_v-to_unsigned(o_hsize*2,19); - ELSE - div_v:=div_v+to_unsigned(o_hsize*2,19); - END IF; - dir_v(6):=NOT div_v(18); - END IF; - - ----------------------------------- - o_hfrac<=dir_v; - o_hfrac1<=o_hfrac; o_hfrac2<=o_hfrac1; - o_hfrac3<=o_hfrac2; o_hfrac4<=o_hfrac3; - - o_copyv(1 TO 8)<=o_copyv(0 TO 7); - - o_dcptv(1)<=o_dcpt; - IF o_dcptv(1)>=o_hsize THEN - o_copyv(2)<='0'; - END IF; - o_dcptv(2)<=o_dcptv(1) MOD OHRES; - o_dcptv(3 TO 8)<=o_dcptv(2 TO 7); - - o_hpixq<=(o_hpix3,o_hpix2,o_hpix1,o_hpix0); - - -- NEAREST / BILINEAR / SHARP BILINEAR --------------- - -- C1 : Pre-calc Sharp Bilinear - o_h_sbil_t<=sbil_frac1(o_hfrac1); - - -- C2 : Select - o_h_frac2<=(OTHERS =>'0'); - CASE o_hmode(1 DOWNTO 0) IS - WHEN "00" => -- Nearest - IF MASK(MASK_NEAREST)='1' THEN - o_h_frac2<=near_frac(o_hfrac2); - END IF; - WHEN "01" => -- Bilinear - IF MASK(MASK_BILINEAR)='1' THEN - o_h_frac2<=bil_frac(o_hfrac2); - END IF; - WHEN "10" => -- Sharp Bilinear - IF MASK(MASK_SHARP_BILINEAR)='1' THEN - o_h_frac2<=sbil_frac2(o_hfrac2,o_h_sbil_t); - END IF; - WHEN OTHERS => - NULL; - END CASE; - - -- C3 : Opposite frac - o_h_bil_t<=bil_calc(o_h_frac2,o_hpixq); - - -- C4 : Nearest / Bilinear / Sharp Bilinear - o_h_bil_pix.r<=bound(o_h_bil_t.r,8+FRAC); - o_h_bil_pix.g<=bound(o_h_bil_t.g,8+FRAC); - o_h_bil_pix.b<=bound(o_h_bil_t.b,8+FRAC); - - -- BICUBIC ------------------------------------------- - -- C1 : Bicubic coefficients A,B,C,D - - -- C2 : Bicubic calc T1 = X.D + C - o_h_bic_abcd1<=bic_calc0(o_hfrac2,(o_hpix3,o_hpix2,o_hpix1,o_hpix0)); - o_h_bic_tt1<=bic_calc1(o_hfrac2, - bic_calc0(o_hfrac2,(o_hpix3,o_hpix2,o_hpix1,o_hpix0))); - - -- C3 : Bicubic calc T2 = X.T1 + B - o_h_bic_abcd2<=o_h_bic_abcd1; - o_h_bic_tt2<=bic_calc2(o_hfrac3,o_h_bic_tt1,o_h_bic_abcd1); - - -- C4 : Bicubic final Y = X.T2 + A - o_h_bic_pix<=bic_calc3(o_hfrac4,o_h_bic_tt2,o_h_bic_abcd2); - - -- POLYPHASE ----------------------------------------- - -- C1 : Read memory - - -- C2 : Filter calc - o_h_poly_dr2<=o_h_poly_dr; - - -- C3 : Add - o_h_poly_t<=poly_calc1(o_h_poly_dr2,o_hpixq); - - -- C4 : Bounding - o_h_poly_pix<=poly_calc2(o_h_poly_t); - - -- C5 : Select interpoler ---------------------------- - o_wadl<=o_dcptv(8); - o_wr<=o_altx AND (o_copyv(8) & o_copyv(8) & o_copyv(8) & o_copyv(8)); - o_ldw<=(x"00",x"00",x"00"); - - CASE o_hmode(2 DOWNTO 0) IS - WHEN "000" | "001" | "010" => -- Nearest | Bilinear | Sharp Bilinear - IF MASK(MASK_NEAREST)='1' OR - MASK(MASK_BILINEAR)='1' OR - MASK(MASK_SHARP_BILINEAR)='1' THEN - o_ldw<=o_h_bil_pix; - END IF; - WHEN "011" => -- BiCubic - IF MASK(MASK_BICUBIC)='1' THEN - o_ldw<=o_h_bic_pix; - END IF; - WHEN OTHERS => -- PolyPhase - IF MASK(MASK_POLY)='1' THEN - o_ldw<=o_h_poly_pix; - END IF; - END CASE; - ------------------------------------------------------ - END IF; - END PROCESS HSCAL; - - ----------------------------------------------------------------------------- - -- Line buffers 4 x OHRES x (R+G+B) - OLBUF:PROCESS(o_clk) IS - BEGIN - IF rising_edge(o_clk) THEN - -- WRITES - IF o_wr(0)='1' THEN o_line0(o_wadl)<=o_ldw; END IF; - IF o_wr(1)='1' THEN o_line1(o_wadl)<=o_ldw; END IF; - IF o_wr(2)='1' THEN o_line2(o_wadl)<=o_ldw; END IF; - IF o_wr(3)='1' THEN o_line3(o_wadl)<=o_ldw; END IF; - - -- READS - o_ldr0<=o_line0(o_radl); - o_ldr1<=o_line1(o_radl); - o_ldr2<=o_line2(o_radl); - o_ldr3<=o_line3(o_radl); - END IF; - END PROCESS OLBUF; - - ----------------------------------------------------------------------------- - -- Output video sweep - OSWEEP:PROCESS(o_clk) IS - BEGIN - IF rising_edge(o_clk) THEN - IF o_ce='1' THEN - -- Output pixels count - IF o_hcpt+1=o_vtotal THEN - o_vcpt_pre3<=0; - ELSE - o_vcpt_pre3<=(o_vcpt_pre3+1) MOD 4096; - END IF; - o_vcpt_pre2<=o_vcpt_pre3; - o_vcpt_pre<=o_vcpt_pre2; - o_vcpt<=o_vcpt_pre; - END IF; - - o_end(0)<=to_std_logic(o_vcpt>=o_vdisp); - o_dev(0)<=to_std_logic(o_hcpt=o_hmin AND o_hcpt<=o_hmax AND - o_vcpt>=o_vmin AND o_vcpt<=o_vmax); - o_hsv(0)<=to_std_logic(o_hcpt>=o_hsstart AND o_hcpt=o_hsstart) OR - (o_vcpt>o_vsstart AND o_vcpt=o_vmin AND o_vcpt_pre2<=o_vmax); - o_hsv(1 TO 5)<=o_hsv(0 TO 4); - o_vsv(1 TO 5)<=o_vsv(0 TO 4); - o_dev(1 TO 5)<=o_dev(0 TO 4); - o_pev(1 TO 5)<=o_pev(0 TO 4); - o_end(1 TO 5)<=o_end(0 TO 4); - - IF o_run='0' THEN - o_hsv(2)<='0'; - o_vsv(2)<='0'; - o_dev(2)<='0'; - o_pev(2)<='0'; - o_end(2)<='0'; - END IF; - - END IF; - END IF; - - END PROCESS OSWEEP; - - ----------------------------------------------------------------------------- - -- Vertical Scaler - VSCAL:PROCESS(o_clk) IS - VARIABLE pixq_v : arr_pix(0 TO 3); - BEGIN - IF rising_edge(o_clk) THEN - IF o_ce='1' THEN - -- CYCLE 1 ----------------------------------------- - -- Read mem - o_radl<=(o_hcpt - o_hmin + OHRES) MOD OHRES; - - -- CYCLE 2 ----------------------------------------- - -- Lines reordering - CASE o_vacpt(1 DOWNTO 0) IS - WHEN "10" => pixq_v:=(o_ldr0,o_ldr1,o_ldr2,o_ldr3); - WHEN "11" => pixq_v:=(o_ldr1,o_ldr2,o_ldr3,o_ldr0); - WHEN "00" => pixq_v:=(o_ldr2,o_ldr3,o_ldr0,o_ldr1); - WHEN OTHERS => pixq_v:=(o_ldr3,o_ldr0,o_ldr1,o_ldr2); - END CASE; - - o_vpixq<=pixq_v; - - -- Bottom edge : replicate last line - IF to_integer(o_vacpt)=o_ivsize THEN - o_vpixq(2)<=pixq_v(2); - END IF; - IF to_integer(o_vacpt)>=o_ivsize+1 THEN - o_vpixq(2)<=pixq_v(1); - o_vpixq(1)<=pixq_v(1); - END IF; - - o_vpixq1<=o_vpixq; - - -- NEAREST / BILINEAR / SHARP BILINEAR ------------- - -- C3 : Pre-calc Sharp Bilinear - o_v_sbil_t<=sbil_frac1(o_vfrac); - - -- C4 : Select - o_v_frac<=(OTHERS =>'0'); - CASE o_vmode(1 DOWNTO 0) IS - WHEN "00" => -- Nearest - IF MASK(MASK_NEAREST)='1' THEN - o_v_frac<=near_frac(o_vfrac); - END IF; - WHEN "01" => -- Bilinear - IF MASK(MASK_BILINEAR)='1' THEN - o_v_frac<=bil_frac(o_vfrac); - END IF; - WHEN "10" => -- Sharp Bilinear - IF MASK(MASK_SHARP_BILINEAR)='1' THEN - o_v_frac<=sbil_frac2(o_vfrac,o_v_sbil_t); - END IF; - WHEN OTHERS => NULL; - END CASE; - - o_v_bil_t<=bil_calc(o_v_frac,o_vpixq1); - - -- C6 : Nearest / Bilinear / Sharp Bilinear - o_v_bil_pix.r<=bound(o_v_bil_t.r,8+FRAC); - o_v_bil_pix.g<=bound(o_v_bil_t.g,8+FRAC); - o_v_bil_pix.b<=bound(o_v_bil_t.b,8+FRAC); - - -- BICUBIC ----------------------------------------- - -- C3 : Bicubic coefficients A,B,C,D - - -- C4 : Bicubic calc T1 = X.D + C - o_v_bic_abcd1<=bic_calc0(o_vfrac,o_vpixq); - o_v_bic_tt1<=bic_calc1(o_vfrac,bic_calc0(o_vfrac,o_vpixq)); - - -- C5 : Bicubic calc T2 = X.T1 + B - o_v_bic_abcd2<=o_v_bic_abcd1; - o_v_bic_tt2<=bic_calc2(o_vfrac,o_v_bic_tt1,o_v_bic_abcd1); - - -- C6 : Bicubic final Y = X.T2 + A - o_v_bic_pix<=bic_calc3(o_vfrac,o_v_bic_tt2,o_v_bic_abcd2); - - -- POLYPHASE --------------------------------------- - -- C3 : Read memory - - -- C4 : Filter calc - o_v_poly_dr2<=o_v_poly_dr; - - -- C5 : Add - o_v_poly_t<=poly_calc1(o_v_poly_dr2,o_vpixq1); - - -- C6 : Bounding - o_v_poly_pix<=poly_calc2(o_v_poly_t); - - -- CYCLE 6 ----------------------------------------- - o_hs<=o_hsv(5); - o_vs<=o_vsv(5); - o_de<=o_dev(5); - o_vbl<=o_end(5); - o_r<=x"00"; - o_g<=x"00"; - o_b<=x"00"; - - CASE o_vmode(2 DOWNTO 0) IS - WHEN "000" | "001" | "010" => -- Nearest | Bilinear | Sharp Bilinear - IF MASK(MASK_NEAREST)='1' OR - MASK(MASK_BILINEAR)='1' OR - MASK(MASK_SHARP_BILINEAR)='1' THEN - o_r<=o_v_bil_pix.r; - o_g<=o_v_bil_pix.g; - o_b<=o_v_bil_pix.b; - END IF; - WHEN "011" => -- BiCubic - IF MASK(MASK_BICUBIC)='1' THEN - o_r<=o_v_bic_pix.r; - o_g<=o_v_bic_pix.g; - o_b<=o_v_bic_pix.b; - END IF; - - WHEN OTHERS => -- Polyphase - IF MASK(MASK_POLY)='1' THEN - o_r<=o_v_poly_pix.r; - o_g<=o_v_poly_pix.g; - o_b<=o_v_poly_pix.b; - END IF; - END CASE; - - IF o_pev(5)='0' THEN - o_r<=o_border(23 DOWNTO 16); -- Copy border colour - o_g<=o_border(15 DOWNTO 8); - o_b<=o_border(7 DOWNTO 0); - END IF; - - ---------------------------------------------------- - END IF; - END IF; + ELSIF rising_edge(o_clk) THEN + ------------------------------------------------------ + o_mode <=mode; -- ? + o_format <="0001" & format; -- ? - END PROCESS VSCAL; - - ----------------------------------------------------------------------------- - -- Low Lag syntoniser interface - o_lltune<=(0 => i_vss, - 1 => i_pde, - 2 => i_inter, - 3 => i_flm, - 4 => o_vss, - 5 => i_pce, - 6 => i_clk, - 7 => o_clk, - OTHERS =>'0'); - - ---------------------------------------------------------------------------- + o_run <=run; -- ? + + o_htotal <=htotal; -- ? + o_hsstart<=hsstart; -- ? + o_hsend <=hsend; -- ? + o_hdisp <=hdisp; -- ? + o_hmin <=hmin; -- ? + o_hmax <=hmax; -- ? + + o_vtotal <=vtotal; -- ? + o_vsstart<=vsstart; -- ? + o_vsend <=vsend; -- ? + o_vdisp <=vdisp; -- ? + o_vmin <=vmin; -- ? + o_vmax <=vmax; -- ? + + o_hsize <=o_hmax - o_hmin + 1; + o_vsize <=o_vmax - o_vmin + 1; + + o_vrr <=vrr; + o_vrrmax <= vrrmax; + + -------------------------------------------- + -- Triple buffering. + -- For intelaced video, half frames are updated independently + -- Input : Toggle buffer at end of input frame + o_isync <= '0'; + o_isync2 <= o_isync; + o_freeze <= freeze; + o_inter <=i_inter; -- + o_iendframe0<=i_endframe0; -- + o_iendframe02<=o_iendframe0; + IF o_iendframe0='1' AND o_iendframe02='0' THEN + o_ibuf0<=buf_next(o_ibuf0,o_obuf0,o_freeze); + o_bufup0<='1'; + o_isync <= '1'; + END IF; + o_iendframe1<=i_endframe1; -- + o_iendframe12<=o_iendframe1; + IF o_iendframe1='1' AND o_iendframe12='0' THEN + o_ibuf1<=buf_next(o_ibuf1,o_obuf1,o_freeze); + o_bufup1<='1'; + o_isync <= '1'; + END IF; + + -- Output : Change framebuffer, and image properties, at VS falling edge + IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup0='1' THEN + o_obuf0<=buf_next(o_obuf0,o_ibuf0,o_freeze); + o_bufup0<='0'; + END IF; + IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup1='1' THEN + o_obuf1<=buf_next(o_obuf1,o_ibuf1,o_freeze); + o_bufup1<='0'; + o_ihsize<=i_hrsize; -- + o_ivsize<=i_vrsize; -- + o_hdown<=i_hdown; -- + o_vdown<=i_vdown; -- + + IF (o_newres > 0) then + o_newres <= o_newres- 1; + END IF; + END IF; + + IF (swblack = '1' and o_fb_ena = '0' and (o_ihsize /= i_hrsize or o_ivsize /= i_vrsize)) then + o_newres <= 3; + END IF; + + -- Simultaneous change of input and output framebuffers + IF o_vsv(1)='1' AND o_vsv(0)='0' AND + o_iendframe0='1' AND o_iendframe02='0' THEN + o_bufup0<='0'; + o_obuf0<=o_ibuf0; + END IF; + IF o_vsv(1)='1' AND o_vsv(0)='0' AND + o_iendframe1='1' AND o_iendframe12='0' THEN + o_bufup1<='0'; + o_obuf1<=o_ibuf1; + END IF; + + -- Non-interlaced, use same buffer for even and odd lines + IF o_inter='0' THEN + o_ibuf1<=o_ibuf0; + o_obuf1<=o_obuf0; + END IF; + + -- Triple buffer disabled + IF o_mode(3)='0' THEN + o_obuf0<=0; + o_obuf1<=0; + o_ibuf0<=0; + o_ibuf1<=0; + END IF; + + -- Framebuffer mode. + IF o_fb_ena='1' THEN + o_ihsize<=o_fb_hsize; + o_ivsize<=o_fb_vsize; + o_format<=o_fb_format; + o_hdown<='0'; + o_vdown<='0'; + END IF; + + -- 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp + CASE o_format(2 DOWNTO 0) IS + WHEN "011" => o_ihsize_temp <= o_ihsize; + WHEN "100" => o_ihsize_temp <= o_ihsize * 2; + WHEN "110" => o_ihsize_temp <= o_ihsize * 4; + WHEN OTHERS => o_ihsize_temp <= o_ihsize * 3; + END CASE; + + o_ihsize_temp2 <= (o_ihsize_temp + N_BURST - 1); + o_hburst <= o_ihsize_temp2 / N_BURST; + + IF o_fb_ena='1' AND o_fb_stride /= 0 THEN + o_stride<=o_fb_stride; + ELSE + o_stride<=to_unsigned(o_ihsize_temp2,14); + o_stride(NB_BURST-1 DOWNTO 0)<=(OTHERS =>'0'); + END IF; + ------------------------------------------------------ + o_hmode<=o_mode; + IF o_hdown='1' AND DOWNSCALE THEN + -- Force nearest if downscaling : Downscaled framebuffer + o_hmode(2 DOWNTO 0)<="000"; + END IF; + + o_vmode<=o_mode; + IF o_vdown='1' AND DOWNSCALE THEN + -- Force nearest if downscaling : Downscaled framebuffer + o_vmode(2 DOWNTO 0)<="000"; + END IF; + + ------------------------------------------------------ + -- End DRAM READ + o_readack_sync<=avl_readack; -- + o_readack_sync2<=o_readack_sync; + o_readack<=o_readack_sync XOR o_readack_sync2; + + o_readdataack_sync<=avl_readdataack; -- + o_readdataack_sync2<=o_readdataack_sync; + o_readdataack<=o_readdataack_sync XOR o_readdataack_sync2; + + ------------------------------------------------------ + lev_inc_v:='0'; + lev_dec_v:='0'; + + -- acpt : Pixel position within current data word + -- dcpt : Destination image position + + -- Force preload 2 lines at top of screen + IF o_hsv(0)='1' AND o_hsv(1)='0' THEN + IF o_vcpt_pre3=o_vmin THEN + o_fload<=2; + o_bibu<='0'; + END IF; + o_hsp<='1'; + END IF; + + o_vpe<=to_std_logic(o_vcpt_pre=o_vmin); + o_divstart<='0'; + o_adrsa<='0'; + o_adrsb<=o_adrsa; + + o_vacc_ini<=(o_vsize - o_ivsize + 8192) MOD 8192; + o_hacc_ini<=(o_hsize + o_ihsize + 8192) MOD 8192; + + --Alternate phase + --o_vacc_ini<=o_ivsize; + --o_hacc_ini<=(2*o_hsize - o_ihsize + 8192) MOD 8192; + + CASE o_state IS + -------------------------------------------------- + WHEN sDISP => + IF o_hsp='1' THEN + o_state<=sHSYNC; + o_hsp<='0'; + END IF; + o_prim<=true; + o_vcarrym<=false; + + -------------------------------------------------- + WHEN sHSYNC => + dif_v :=(o_vacc_next - 2*o_vsize + 16384) MOD 16384; + IF o_prim THEN + IF dif_v>=8192 THEN + o_vacc <=o_vacc_next; + ELSE + o_vacc <=dif_v; + END IF; + END IF; + IF dif_v>=8192 THEN + o_vacc_next<=(o_vacc_next + 2*o_ivsize) MOD 8192; + vcarry_v:=false; + ELSE + o_vacc_next<=dif_v; + vcarry_v:=true; + END IF; + + IF o_vcpt_pre2=o_vmin THEN + o_vacc <=o_vacc_ini; + o_vacc_next<=o_vacc_ini + 2*o_ivsize; + o_vacpt <=x"001"; + o_vacptl<="01"; + vcarry_v:=false; + END IF; + + IF vcarry_v THEN + o_vacpt<=o_vacpt+1; + END IF; + IF vcarry_v AND o_prim THEN + o_vacptl<=o_vacptl+1; + END IF; + o_vcarrym <= o_vcarrym OR vcarry_v; + o_prim <= false; + o_hbcpt<=0; -- Clear burst counter on line + o_divstart<=to_std_logic(NOT vcarry_v); + IF NOT vcarry_v OR o_fload>0 THEN + IF (o_vpe='1' AND o_vcarrym) OR o_fload>0 THEN + o_state<=sREAD; + ELSE + o_state<=sDISP; + END IF; + END IF; + + WHEN sREAD => + -- Read a block + IF o_readlev<2 AND o_adrsb='1' THEN + lev_inc_v:='1'; + o_read_pre<=NOT o_read_pre; + o_state <=sWAITREAD; + o_bibu<=NOT o_bibu; + END IF; + prim_v:=to_std_logic(o_hbcpt=0); + last_v:=to_std_logic(o_hbcpt=o_hburst-1); + bib_v :=o_bibu; + off_v :=pixoffset(o_adrs + o_fb_base(NB_LA-1 DOWNTO 0),o_fb_format); + IF o_fb_ena='0' THEN + off_v:=0; + END IF; + o_adrsa<='1'; + + WHEN sWAITREAD => + IF o_readack='1' THEN + o_hbcpt<=o_hbcpt+1; + IF o_hbcpt=1 THEN + o_fload<=o_fload-1; + END IF; + END IF; + END IF; + + -------------------------------------------------- + END CASE; + + o_read<=o_read_pre AND o_run; + o_rline<=o_vacpt(0); -- Even/Odd line for interlaced video + + o_adrs_pre<=to_integer(o_vacpt) * to_integer(o_stride); + IF o_adrsa='1' THEN + IF o_fload=2 THEN + o_adrs<=to_unsigned(o_hbcpt * N_BURST,32); + o_alt<="1111"; + ELSIF o_fload=1 THEN + o_adrs<=to_unsigned(o_hbcpt * N_BURST,32) + o_stride; + o_alt<="0100"; + ELSE + o_adrs<=to_unsigned(o_adrs_pre + (o_hbcpt * N_BURST),32); + o_alt<=altx(o_vacptl + 1); + END IF; + END IF; + + ------------------------------------------------------ + -- Copy from buffered memory to pixel lines + o_sh<='0'; + CASE o_copy IS + WHEN sWAIT => + o_copyv(0)<='0'; + IF o_copylev>0 AND o_copyv(0)='0' THEN + o_copy<=sCOPY; + IF o_off(0)>0 AND o_primv(0)='1' THEN + o_copy<=sSHIFT; + END IF; + o_altx<=o_alt; + END IF; + o_adturn<='0'; + o_pshift<=o_off(0) -1; + IF o_primv(0)='1' THEN + -- First memcopy of a horizontal line, carriage return ! + o_ihsizem<=o_ihsize + o_off(0) - 2; + o_hacc <=o_hacc_ini; + o_hacc_next<=o_hacc_ini + 2*o_ihsize; + o_hacpt <=x"000"; + o_dcpt<=0; + o_dshi<=2; + o_acpt<=0; + o_first<='1'; + o_last<='0'; + END IF; + + IF o_bibv(0)='0' THEN + o_ad<=0; + ELSE + o_ad<=BLEN; + END IF; + + WHEN sSHIFT => + o_hacpt<=o_hacpt+1; + o_sh<='1'; + o_acpt<=(o_acpt+1) MOD 16; + IF shift_onext(o_acpt,o_format) THEN + o_ad<=(o_ad+1) MOD (2*BLEN); + END IF; + o_pshift<=o_pshift-1; + IF o_pshift=0 THEN + o_copy<=sCOPY; + END IF; + + WHEN sCOPY => + -- dshi : Force shift first two or three pixels of each line + IF o_dshi=0 THEN + dif_v:=(o_hacc_next - 2*o_hsize + (8*OHRES)) MOD (8*OHRES); + IF dif_v>=4*OHRES THEN + o_hacc<=o_hacc_next; + o_hacc_next<=o_hacc_next + 2*o_ihsize; + hcarry_v:=false; + ELSE + o_hacc<=dif_v; + o_hacc_next<=(dif_v + 2*o_ihsize + (4*OHRES)) MOD (4*OHRES); + hcarry_v:=true; + END IF; + o_dcpt<=(o_dcpt+1) MOD 4096; + ELSE + o_dshi<=o_dshi-1; + hcarry_v:=false; + END IF; + IF o_dshi<=1 THEN + o_copyv(0)<='1'; + END IF; + IF hcarry_v THEN + o_hacpt<=o_hacpt+1; + o_last <=to_std_logic(o_hacpt>=o_ihsizem); + END IF; + + IF hcarry_v OR o_dshi>0 THEN + o_sh<='1'; + o_acpt<=(o_acpt+1) MOD 16; + + -- Shift two more pixels to the right before ending line. + o_last1<=o_last; + o_last2<=o_last1; + + IF shift_onext(o_acpt,o_format) THEN + o_ad<=(o_ad+1) MOD (2*BLEN); + END IF; + + IF o_adturn='1' AND (shift_onext((o_acpt+1) MOD 16,o_format)) AND + (((o_ad MOD BLEN=0) AND o_lastv(0)='0') OR o_last2='1') THEN + o_copy<=sWAIT; + lev_dec_v:='1'; + END IF; + + IF o_ad MOD BLEN=4 THEN + o_adturn<='1'; + END IF; + END IF; + END CASE; + + o_acpt1<=o_acpt; o_acpt2<=o_acpt1; o_acpt3<=o_acpt2; o_acpt4<=o_acpt3; + o_ad1<=o_ad; o_ad2<=o_ad1; o_ad3<=o_ad2; + o_sh1<=o_sh; o_sh2<=o_sh1; o_sh3<=o_sh2; o_sh4<=o_sh3; + o_lastt1<=o_last; o_lastt2<=o_lastt1; + o_lastt3<=o_lastt2; o_lastt4<=o_lastt3; + + ------------------------------------------------------ + IF o_sh3='1' THEN + shift_v:=shift_opack(o_acpt4,o_shift,o_dr,o_format); + o_shift<=shift_v; + o_hpixs<=shift_opix(shift_v,o_format); + END IF; + + IF o_sh4='1' THEN + hpix_v:=o_hpixs; + IF o_format(4)='1' THEN -- Swap B <-> R + hpix_v:=(r=>o_hpixs.b,g=>o_hpixs.g,b=>o_hpixs.r); + END IF; + IF o_format(2 DOWNTO 0)="011" THEN + -- 8bpp indexed colour mode + hpix_v:=(r=>o_fb_pal_dr(23 DOWNTO 16),g=>o_fb_pal_dr(15 DOWNTO 8), + b=>o_fb_pal_dr(7 DOWNTO 0)); + END IF; + IF (o_newres > 0) then + hpix_v := (others => (others => '0')); + END IF; + o_hpix0<=hpix_v; + o_hpix1<=o_hpix0; + o_hpix2<=o_hpix1; + o_hpix3<=o_hpix2; + + IF o_first='1' THEN + -- Left edge. Duplicate first pixel + o_hpix1<=hpix_v; + o_hpix2<=hpix_v; + o_first<='0'; + END IF; + IF o_lastt4='1' THEN + -- Right edge. Keep last pixel. + o_hpix0<=o_hpix0; + END IF; + END IF; + + ------------------------------------------------------ + -- lev_inc : read start + -- lev_dec : end of copy + -- READLEV : Number of ongoing Avalon Reads + IF lev_dec_v='0' AND lev_inc_v='1' THEN + o_readlev<=o_readlev+1; + ELSIF lev_dec_v='1' AND lev_inc_v='0' THEN + o_readlev<=o_readlev-1; + END IF; + + -- COPYLEV : Number of ongoing copies to line buffers + IF lev_dec_v='1' AND o_readdataack='0' THEN + o_copylev<=o_copylev-1; + ELSIF lev_dec_v='0' AND o_readdataack='1' THEN + o_copylev<=o_copylev+1; + END IF; + + -- FIFOs + IF lev_dec_v='1' THEN + o_primv(0 TO 1)<=o_primv(1 TO 2); -- First buffer of line + o_lastv(0 TO 1)<=o_lastv(1 TO 2); -- Last buffer of line + o_bibv (0 TO 1)<=o_bibv (1 TO 2); -- Double buffer select + o_off (0 TO 1)<=o_off (1 TO 2); -- Start offset + END IF; + + IF lev_inc_v='1' THEN + IF o_readlev=0 OR (o_readlev=1 AND lev_dec_v='1') THEN + o_primv(0)<=prim_v; + o_lastv(0)<=last_v; + o_bibv (0)<=bib_v; + o_off (0)<=off_v; + ELSIF (o_readlev=1 AND lev_dec_v='0') OR + (o_readlev=2 AND lev_dec_v='1') THEN + o_primv(1)<=prim_v; + o_lastv(1)<=last_v; + o_bibv (1)<=bib_v; + o_off (1)<=off_v; + END IF; + o_primv(2)<=prim_v; + o_lastv(2)<=last_v; + o_bibv (2)<=bib_v; + o_off (2)<=off_v; + END IF; + + ------------------------------------------------------ + END IF; + END PROCESS Scalaire; + + -- Fetch polyphase coefficients + PolyFetch:PROCESS (o_clk) IS + VARIABLE hfrac3_v, vfrac_v : unsigned(FRAC-1 DOWNTO 0); + BEGIN + IF rising_edge(o_clk) THEN + hfrac3_v:=o_hfrac(3)(11 DOWNTO 12-FRAC); + vfrac_v:=o_vfrac(11 DOWNTO 12-FRAC); + + o_v_poly_use_adaptive <= to_std_logic((o_vmode(2 DOWNTO 0)/="000") AND (o_v_poly_adaptive = '1')); + o_h_poly_use_adaptive <= to_std_logic((o_hmode(2 DOWNTO 0)/="000") AND (o_h_poly_adaptive = '1')); + o_v_poly_addr<=to_integer(o_vfrac(11 DOWNTO 12-FRAC)); + + -- C3 / HC3 / VC4 + IF o_vmode(2 DOWNTO 0)/="000" THEN + o_v_poly_phase_a<=poly_unpack(o_v_poly_mem(o_v_poly_addr)); + ELSE + o_v_poly_phase_a<=poly_nn(vfrac_v); + END IF; + + IF o_hmode(2 DOWNTO 0)/="000" THEN + o_h_poly_phase_a<=poly_unpack(o_h_poly_mem(to_integer(hfrac3_v))); + ELSE + o_h_poly_phase_a<=poly_nn(hfrac3_v); + END IF; + + IF o_v_poly_use_adaptive='1' THEN + o_poly_lum<=poly_lum(o_v_lum_pix); + o_a_poly_addr<=o_v_poly_addr; + ELSIF o_h_poly_use_adaptive='1' THEN + o_poly_lum<=poly_lum(o_h_lum_pix); + o_a_poly_addr<=to_integer(hfrac3_v); + END IF; + + -- C4 / HC4 / VC5 + o_poly_phase_b<=poly_unpack(o_a_poly_mem(o_a_poly_addr)); + + IF o_v_poly_use_adaptive='1' THEN + o_poly_phase_a<=o_v_poly_phase_a; + ELSIF o_h_poly_use_adaptive = '1' THEN + o_poly_phase_a<=o_h_poly_phase_a; + END IF; + + o_h_poly_phase_a2<=o_h_poly_phase_a; + o_v_poly_phase_a2<=o_v_poly_phase_a; + o_poly_lum1<=o_poly_lum; + + -- C5 / HC5 / VC6 + o_poly_lerp_ta<=signed(to_unsigned(256,10) - resize(o_poly_lum1,10)); + o_poly_lerp_tb<=signed(resize(o_poly_lum1,10)); + + o_poly_phase_b2<=o_poly_phase_b; + o_poly_phase_a2<=o_poly_phase_a; + + o_h_poly_phase_a3<=o_h_poly_phase_a2; + o_v_poly_phase_a3<=o_v_poly_phase_a2; + + -- C6 / HC6 / VC7 + o_poly_phase<=poly_lerp(o_poly_phase_a2, o_poly_phase_b2, o_poly_lerp_ta, o_poly_lerp_tb); + o_h_poly_phase_a4<=o_h_poly_phase_a3; + o_v_poly_phase_a4<=o_v_poly_phase_a3; + + -- C7 / HC7 / VC8 + o_h_poly_phase_a5<=o_h_poly_phase_a4; + o_v_poly_phase_a5<=o_v_poly_phase_a4; + o_poly_phase1<=o_poly_phase; + + -- C8 / HC8 / VC9 + o_v_poly_phase<=poly_cvt(o_v_poly_phase_a5); + o_h_poly_phase<=poly_cvt(o_h_poly_phase_a5); + + IF o_v_poly_use_adaptive = '1' THEN + o_v_poly_phase<=o_poly_phase1; + ELSIF o_h_poly_use_adaptive = '1' THEN + o_h_poly_phase<=o_poly_phase1; + END IF; + + END IF; + END PROCESS PolyFetch; + + + -- Framebuffer palette + GenPal1:IF PALETTE GENERATE + Tempera1:PROCESS(pal1_clk) IS + BEGIN + IF rising_edge(pal1_clk) THEN + IF pal1_wr='1' THEN + pal1_mem(to_integer(pal1_a))<=pal1_dw; + END IF; + pal1_dr<=pal1_mem(to_integer(pal1_a)); + END IF; + END PROCESS; + + pal_idx <= shift_opack(o_acpt4,o_shift,o_dr,o_format)(0 TO 7); + pal_idx_lsb <= pal_idx(0) WHEN rising_edge(o_clk); + o_fb_pal_dr_x2 <= pal1_mem(to_integer(pal_idx(7 DOWNTO 1))) WHEN rising_edge(o_clk); + END GENERATE GenPal1; + + GenPal2:IF PALETTE and PALETTE2 GENERATE + Tempera2:PROCESS(pal2_clk) IS + BEGIN + IF rising_edge(pal2_clk) THEN + IF pal2_wr='1' THEN + pal2_mem(to_integer(pal2_a))<=pal2_dw; + END IF; + pal2_dr<=pal2_mem(to_integer(pal2_a)); + END IF; + END PROCESS; + + o_fb_pal_dr2 <= pal2_mem(to_integer(pal_idx(7 DOWNTO 0))) WHEN rising_edge(o_clk); + o_fb_pal_dr <= o_fb_pal_dr2 when pal_n = '1' else o_fb_pal_dr_x2(47 DOWNTO 24) WHEN pal_idx_lsb = '1' ELSE o_fb_pal_dr_x2(23 DOWNTO 0); + END GENERATE GenPal2; + + GenPal1not2:IF PALETTE and not PALETTE2 GENERATE + o_fb_pal_dr <= o_fb_pal_dr_x2(47 DOWNTO 24) WHEN pal_idx_lsb = '1' ELSE o_fb_pal_dr_x2(23 DOWNTO 0); + END GENERATE GenPal1not2; + + GenNoPal:IF NOT PALETTE GENERATE + o_fb_pal_dr<=x"000000"; + END GENERATE GenNoPal; + + ----------------------------------------------------------------------------- + -- Polyphase ROMs + Polikarpov:PROCESS(poly_clk) IS + BEGIN + IF rising_edge(poly_clk) THEN + IF poly_wr='1' THEN + poly_tdw(9+10*(3-to_integer(poly_a(1 DOWNTO 0))) DOWNTO + 10*(3-to_integer(poly_a(1 DOWNTO 0))))<=poly_dw; + END IF; + + poly_wr_mode(0)<=poly_wr AND NOT poly_a(FRAC+2); + poly_wr_mode(1)<=poly_wr AND poly_a(FRAC+2); + poly_wr_mode(2)<=poly_wr AND poly_a(FRAC+3) AND to_std_logic(ADAPTIVE); + poly_a2<=poly_a(FRAC+1 DOWNTO 2); + + CASE poly_wr_mode IS + WHEN "001" => -- horiz + o_h_poly_mem(to_integer(poly_a2))<=poly_tdw; + o_h_poly_adaptive<='0'; + WHEN "010" => -- vert + o_v_poly_mem(to_integer(poly_a2))<=poly_tdw; + o_v_poly_adaptive<='0'; + WHEN "101" => -- horiz adaptive + o_a_poly_mem(to_integer(poly_a2))<=poly_tdw; + o_h_poly_adaptive<='1'; + WHEN "110" => -- vert adaptive + o_a_poly_mem(to_integer(poly_a2))<=poly_tdw; + o_v_poly_adaptive<='1'; + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS Polikarpov; + + ----------------------------------------------------------------------------- + -- Horizontal Scaler + HSCAL:PROCESS(o_clk) IS + VARIABLE div_v : unsigned(20 DOWNTO 0); + VARIABLE dir_v : unsigned(11 DOWNTO 0); + BEGIN + IF rising_edge(o_clk) THEN + -- Pipeline signals + ----------------------------------- + -- Pipelined 8 bits non-restoring divider. Cycle 1 + dir_v:=x"000"; + div_v:=to_unsigned(o_hacc * 256,21); + + div_v:=div_v-to_unsigned(o_hsize*256,21); + dir_v(11):=NOT div_v(20); + IF div_v(20)='0' THEN + div_v:=div_v-to_unsigned(o_hsize*128,21); + ELSE + div_v:=div_v+to_unsigned(o_hsize*128,21); + END IF; + dir_v(10):=NOT div_v(20); + + o_div(0)<=div_v; + o_dir(0)<=dir_v; + + -- Cycle 2 + div_v:=o_div(0); + dir_v:=o_dir(0); + IF div_v(20)='0' THEN + div_v:=div_v-to_unsigned(o_hsize*64,21); + ELSE + div_v:=div_v+to_unsigned(o_hsize*64,21); + END IF; + dir_v( 9):=NOT div_v(20); + + IF div_v(20)='0' THEN + div_v:=div_v-to_unsigned(o_hsize*32,21); + ELSE + div_v:=div_v+to_unsigned(o_hsize*32,21); + END IF; + dir_v( 8):=NOT div_v(20); + + o_div(1)<=div_v; + o_dir(1)<=dir_v; + + -- Cycle 3 + div_v:=o_div(1); + dir_v:=o_dir(1); + IF FRAC>4 THEN + IF div_v(20)='0' THEN + div_v:=div_v-to_unsigned(o_hsize*16,21); + ELSE + div_v:=div_v+to_unsigned(o_hsize*16,21); + END IF; + dir_v(7):=NOT div_v(20); + + IF div_v(20)='0' THEN + div_v:=div_v-to_unsigned(o_hsize*8,21); + ELSE + div_v:=div_v+to_unsigned(o_hsize*8,21); + END IF; + dir_v(6):=NOT div_v(20); + END IF; + o_div(2)<=div_v; + o_dir(2)<=dir_v; + + div_v:=o_div(2); + dir_v:=o_dir(2); + IF FRAC>6 THEN + IF div_v(20)='0' THEN + div_v:=div_v-to_unsigned(o_hsize*4,21); + ELSE + div_v:=div_v+to_unsigned(o_hsize*4,21); + END IF; + dir_v(5):=NOT div_v(20); + + IF div_v(20)='0' THEN + div_v:=div_v-to_unsigned(o_hsize*2,21); + ELSE + div_v:=div_v+to_unsigned(o_hsize*2,21); + END IF; + dir_v(4):=NOT div_v(20); + END IF; + + ----------------------------------- + o_hfrac(1)<=dir_v; + o_hfrac(2 TO 9) <= o_hfrac(1 TO 8); + + o_copyv(1 TO 14)<=o_copyv(0 TO 13); + + o_dcptv(1)<=o_dcpt; + IF o_dcptv(1)>=o_hsize THEN + o_copyv(2)<='0'; + END IF; + o_dcptv(2)<=o_dcptv(1) MOD OHRES; + o_dcptv(3 TO 14)<=o_dcptv(2 TO 13); + + -- C2 + o_hpixq(2)<=(o_hpix3,o_hpix2,o_hpix1,o_hpix0); + o_hpixq(3 TO 8)<=o_hpixq(2 TO 7); + + -- BILINEAR / SHARP BILINEAR --------------- + -- C7 : Pre-calc Sharp Bilinear + o_h_sbil_t<=sbil_frac1(o_hfrac(6)); + + -- C8 : Select + o_h_bil_frac<=(OTHERS =>'0'); + IF o_hmode(0)='1' THEN -- Bilinear + IF MASK(MASK_BILINEAR)='1' THEN + o_h_bil_frac<=bil_frac(o_hfrac(7)); + END IF; + ELSE -- Sharp Bilinear + IF MASK(MASK_SHARP_BILINEAR)='1' THEN + o_h_bil_frac<=sbil_frac2(o_hfrac(7),o_h_sbil_t); + END IF; + END IF; + + -- C9 : Opposite frac + o_h_bil_t<=bil_calc(o_h_bil_frac,o_hpixq(8)); + + -- C10 : Bilinear / Sharp Bilinear + o_h_bil_pix.r<=bound(o_h_bil_t.r,8+FRAC); + o_h_bil_pix.g<=bound(o_h_bil_t.g,8+FRAC); + o_h_bil_pix.b<=bound(o_h_bil_t.b,8+FRAC); + + -- BICUBIC ------------------------------------------- + -- C8 : Bicubic coefficients A,B,C,D + -- C8 : Bicubic calc T1 = X.D + C + o_h_bic_abcd1<=bic_calc0(o_hfrac(7),o_hpixq(6)); + o_h_bic_tt1<=bic_calc1(o_hfrac(7), + bic_calc0(o_hfrac(7),o_hpixq(6))); + + -- C9 : Bicubic calc T2 = X.T1 + B + o_h_bic_abcd2<=o_h_bic_abcd1; + o_h_bic_tt2<=bic_calc2(o_hfrac(8),o_h_bic_tt1,o_h_bic_abcd1); + + -- C10 : Bicubic final Y = X.T2 + A + o_h_bic_pix<=bic_calc3(o_hfrac(9),o_h_bic_tt2,o_h_bic_abcd2); + + -- POLYPHASE ----------------------------------------- + -- C2 + IF o_hfrac(2)(o_hfrac(2)'left)='0' THEN + o_h_lum_pix<=o_hpix2; + ELSE + o_h_lum_pix<=o_hpix1; + END IF; + + -- C3-C8 in PolyFetch + + -- C9 : Apply Polyphase + o_h_poly_t<=poly_calc(o_h_poly_phase,o_hpixq(8)); + + -- C10 : Sum and bound + o_h_poly_pix<=poly_final(o_h_poly_t); + + -- C11 : Select interpoler ---------------------------- + o_wadl<=o_dcptv(14); + o_wr<=o_altx AND (o_copyv(14) & o_copyv(14) & o_copyv(14) & o_copyv(14)); + o_ldw<=(x"00",x"00",x"00"); + + CASE o_hmode(2 DOWNTO 0) IS + WHEN "000" => -- Nearest + IF MASK(MASK_NEAREST)='1' THEN + o_ldw<=o_h_poly_pix; + END IF; + WHEN "001" | "010" => -- Bilinear | Sharp Bilinear + IF MASK(MASK_BILINEAR)='1' OR + MASK(MASK_SHARP_BILINEAR)='1' THEN + o_ldw<=o_h_bil_pix; + END IF; + WHEN "011" => -- BiCubic + IF MASK(MASK_BICUBIC)='1' THEN + o_ldw<=o_h_bic_pix; + END IF; + WHEN OTHERS => -- PolyPhase + IF MASK(MASK_POLY)='1' THEN + o_ldw<=o_h_poly_pix; + END IF; + END CASE; + ------------------------------------------------------ + END IF; + END PROCESS HSCAL; + + ----------------------------------------------------------------------------- + -- Line buffers 4 x OHRES x (R+G+B) + OLBUF:PROCESS(o_clk) IS + BEGIN + IF rising_edge(o_clk) THEN + -- WRITES + IF o_wr(0)='1' THEN o_line0(o_wadl)<=o_ldw; END IF; + IF o_wr(1)='1' THEN o_line1(o_wadl)<=o_ldw; END IF; + IF o_wr(2)='1' THEN o_line2(o_wadl)<=o_ldw; END IF; + IF o_wr(3)='1' THEN o_line3(o_wadl)<=o_ldw; END IF; + + -- READS + o_ldr0<=o_line0(o_radl0); + o_ldr1<=o_line1(o_radl1); + o_ldr2<=o_line2(o_radl2); + o_ldr3<=o_line3(o_radl3); + END IF; + END PROCESS OLBUF; + + ----------------------------------------------------------------------------- + -- Output video sweep + OSWEEP:PROCESS(o_clk) IS + BEGIN + IF rising_edge(o_clk) THEN + + IF o_ce='1' THEN + -- Output pixels count + IF o_hcpt+1=o_vtotal THEN + o_vcpt_pre3<=0; + ELSIF o_vrr_sync2 THEN + o_vcpt_pre3<=o_vsstart; + o_sync<=false; + ELSE + o_vcpt_pre3<=(o_vcpt_pre3+1) MOD 4096; + END IF; + + o_vcpt_pre2<=o_vcpt_pre3; + o_vcpt_pre<=o_vcpt_pre2; + o_vcpt<=o_vcpt_pre; + END IF; + + o_end(0)<=to_std_logic(o_vcpt>=o_vdisp); + o_dev(0)<=to_std_logic(o_hcpt=o_hmin AND o_hcpt<=o_hmax AND + o_vcpt>=o_vmin AND o_vcpt<=o_vmax); + o_hsv(0)<=to_std_logic(o_hcpt>=o_hsstart AND o_hcpt=o_hsstart) OR + (o_vcpt>o_vsstart AND o_vcpt=o_vmin AND o_vcpt_pre2<=o_vmax); + o_hsv(1 TO 11)<=o_hsv(0 TO 10); + o_vsv(1 TO 11)<=o_vsv(0 TO 10); + o_dev(1 TO 11)<=o_dev(0 TO 10); + o_pev(1 TO 11)<=o_pev(0 TO 10); + o_end(1 TO 11)<=o_end(0 TO 10); + + IF o_run='0' THEN + o_hsv(2)<='0'; + o_vsv(2)<='0'; + o_dev(2)<='0'; + o_pev(2)<='0'; + o_end(2)<='0'; + END IF; + END IF; + + o_vcpt_sync2<=o_vcpt_sync; + o_vrr_min<=(o_vcpt_sync2=o_vdisp AND o_vcpt2 o_radl1<=r2_v; + WHEN "11" => o_radl2<=r2_v; + WHEN "00" => o_radl3<=r2_v; + WHEN OTHERS => o_radl0<=r2_v; + END CASE; + ELSE + CASE o_vacptl IS + WHEN "10" => o_radl2<=r2_v; + WHEN "11" => o_radl3<=r2_v; + WHEN "00" => o_radl0<=r2_v; + WHEN OTHERS => o_radl1<=r2_v; + END CASE; + END IF; + + -- CYCLE 2 ----------------------------------------- + -- Lines reordering + CASE o_vacptl IS + WHEN "10" => pixq_v:=(o_ldr0,o_ldr1,o_ldr2,o_ldr3); + WHEN "11" => pixq_v:=(o_ldr1,o_ldr2,o_ldr3,o_ldr0); + WHEN "00" => pixq_v:=(o_ldr2,o_ldr3,o_ldr0,o_ldr1); + WHEN OTHERS => pixq_v:=(o_ldr3,o_ldr0,o_ldr1,o_ldr2); + END CASE; + + IF fracnn_v = '0' THEN + o_vpix_outer<=(pixq_v(0), pixq_v(2), pixq_v(3)); + o_vpix_inner(0)<=pixq_v(1); + ELSE + o_vpix_outer<=(pixq_v(0), pixq_v(1), pixq_v(3)); + o_vpix_inner(0)<=pixq_v(2); + END IF; + + -- CYCLE 3-7 + o_vpix_inner(1 TO 5)<=o_vpix_inner(0 TO 4); + + -- CYCLE 8 + IF to_integer(o_vacpt)>o_ivsize THEN + IF fracnn_v = '0' THEN + o_vpixq_pre<=(o_vpix_outer(0), o_vpix_inner(5), o_vpix_inner(5), o_vpix_inner(5)); + ELSE + o_vpixq_pre<=(o_vpix_outer(0), o_vpix_outer(1), o_vpix_outer(1), o_vpix_outer(1)); + END IF; + ELSIF to_integer(o_vacpt)=o_ivsize THEN + IF fracnn_v = '0' THEN + o_vpixq_pre<=(o_vpix_outer(0), o_vpix_inner(5), o_vpix_outer(1), o_vpix_outer(1)); + ELSE + o_vpixq_pre<=(o_vpix_outer(0), o_vpix_outer(1), o_vpix_inner(5), o_vpix_inner(5)); + END IF; + ELSE + IF fracnn_v = '0' THEN + o_vpixq_pre<=(o_vpix_outer(0), o_vpix_inner(5), o_vpix_outer(1), o_vpix_outer(2)); + ELSE + o_vpixq_pre<=(o_vpix_outer(0), o_vpix_outer(1), o_vpix_inner(5), o_vpix_outer(2)); + END IF; + END IF; + + -- CYCLE 9 + o_vpixq<=o_vpixq_pre; + + -- BILINEAR / SHARP BILINEAR ----------------------- + -- C8 : Pre-calc Sharp Bilinear + o_v_sbil_t<=sbil_frac1(o_vfrac); + + -- C9 : Select + o_v_bil_frac<=(OTHERS =>'0'); + IF o_vmode(0)='1' THEN -- Bilinear + IF MASK(MASK_BILINEAR)='1' THEN + o_v_bil_frac<=bil_frac(o_vfrac); + END IF; + ELSE -- Sharp Bilinear + IF MASK(MASK_SHARP_BILINEAR)='1' THEN + o_v_bil_frac<=sbil_frac2(o_vfrac,o_v_sbil_t); + END IF; + END IF; + + -- C10 : + o_v_bil_t<=bil_calc(o_v_bil_frac,o_vpixq); + + -- C11 : Nearest / Bilinear / Sharp Bilinear + o_v_bil_pix.r<=bound(o_v_bil_t.r,8+FRAC); + o_v_bil_pix.g<=bound(o_v_bil_t.g,8+FRAC); + o_v_bil_pix.b<=bound(o_v_bil_t.b,8+FRAC); + + -- BICUBIC ----------------------------------------- + -- C9 : Bicubic coefficients A,B,C,D + -- C9 : Bicubic calc T1 = X.D + C + o_v_bic_abcd1<=bic_calc0(o_vfrac,o_vpixq); + o_v_bic_tt1<=bic_calc1(o_vfrac,bic_calc0(o_vfrac,o_vpixq)); + + -- C10 : Bicubic calc T2 = X.T1 + B + o_v_bic_abcd2<=o_v_bic_abcd1; + o_v_bic_tt2<=bic_calc2(o_vfrac,o_v_bic_tt1,o_v_bic_abcd1); + + -- C11 : Bicubic final Y = X.T2 + A + o_v_bic_pix<=bic_calc3(o_vfrac,o_v_bic_tt2,o_v_bic_abcd2); + + -- POLYPHASE --------------------------------------- + -- C3 : Setup luminance + o_v_lum_pix<=o_vpix_inner(0); + + -- C4-C9 in PolyFetch + + -- C10 : Apply polyphase + o_v_poly_t<=poly_calc(o_v_poly_phase,o_vpixq); + + -- C11 : Bound + o_v_poly_pix<=poly_final(o_v_poly_t); + + -- CYCLE 12 ----------------------------------------- + o_hs<=o_hsv(11); + o_vs<=o_vsv(11); + o_de<=o_dev(11); + o_vbl<=o_end(11); + o_r<=x"00"; + o_g<=x"00"; + o_b<=x"00"; + o_brd<= not o_pev(11); + + CASE o_vmode(2 DOWNTO 0) IS + WHEN "000" => -- Nearest + IF MASK(MASK_NEAREST)='1' THEN + o_r<=o_v_poly_pix.r; + o_g<=o_v_poly_pix.g; + o_b<=o_v_poly_pix.b; + END IF; + WHEN "001" | "010" => -- Bilinear | Sharp Bilinear + IF MASK(MASK_BILINEAR)='1' OR + MASK(MASK_SHARP_BILINEAR)='1' THEN + o_r<=o_v_bil_pix.r; + o_g<=o_v_bil_pix.g; + o_b<=o_v_bil_pix.b; + END IF; + WHEN "011" => -- BiCubic + IF MASK(MASK_BICUBIC)='1' THEN + o_r<=o_v_bic_pix.r; + o_g<=o_v_bic_pix.g; + o_b<=o_v_bic_pix.b; + END IF; + + WHEN OTHERS => -- Polyphase + IF MASK(MASK_POLY)='1' THEN + o_r<=o_v_poly_pix.r; + o_g<=o_v_poly_pix.g; + o_b<=o_v_poly_pix.b; + END IF; + END CASE; + + IF o_pev(11)='0' THEN + o_r<=o_border(23 DOWNTO 16); -- Copy border colour + o_g<=o_border(15 DOWNTO 8); + o_b<=o_border(7 DOWNTO 0); + END IF; + + ---------------------------------------------------- + END IF; + END IF; + END PROCESS VSCAL; + + ----------------------------------------------------------------------------- + -- Low Lag syntoniser interface + o_lltune<=(0 => i_vss, + 1 => i_pde, + 2 => i_inter, + 3 => i_flm, + 4 => o_vss, + 5 => i_pce, + 6 => i_clk, + 7 => o_clk, + OTHERS =>'0'); + + ---------------------------------------------------------------------------- END ARCHITECTURE rtl; diff --git a/sys/build_id.tcl b/sys/build_id.tcl index bb2dc67..b43b9d9 100644 --- a/sys/build_id.tcl +++ b/sys/build_id.tcl @@ -1,73 +1,73 @@ - -# Build TimeStamp Verilog Module -# Jeff Wiencrot - 8/1/2011 -# Sorgelig - 02/11/2019 -proc generateBuildID_Verilog {} { - - # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate "`define BUILD_DATE \"[clock format [ clock seconds ] -format %y%m%d]\"" - - # Create a Verilog file for output - set outputFileName "build_id.v" - - set fileData "" - if { [file exists $outputFileName]} { - set outputFile [open $outputFileName "r"] - set fileData [read $outputFile] - close $outputFile - } - - if {$buildDate ne $fileData} { - set outputFile [open $outputFileName "w"] - puts -nonewline $outputFile $buildDate - close $outputFile - # Send confirmation message to the Messages window - post_message "Generated: [pwd]/$outputFileName: $buildDate" - } -} - -# Build CDF file -# Sorgelig - 17/2/2018 -proc generateCDF {revision device outpath} { - - set outputFileName "jtag.cdf" - set outputFile [open $outputFileName "w"] - - puts $outputFile "JedecChain;" - puts $outputFile " FileRevision(JESD32A);" - puts $outputFile " DefaultMfr(6E);" - puts $outputFile "" - puts $outputFile " P ActionCode(Ign)" - puts $outputFile " Device PartName(SOCVHPS) MfrSpec(OpMask(0));" - puts $outputFile " P ActionCode(Cfg)" - puts $outputFile " Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));" - puts $outputFile "ChainEnd;" - puts $outputFile "" - puts $outputFile "AlteraBegin;" - puts $outputFile " ChainType(JTAG);" - puts $outputFile "AlteraEnd;" -} - -set project_name [lindex $quartus(args) 1] -set revision [lindex $quartus(args) 2] - -if {[project_exists $project_name]} { - if {[string equal "" $revision]} { - project_open $project_name -revision [get_current_revision $project_name] - } else { - project_open $project_name -revision $revision - } -} else { - post_message -type error "Project $project_name does not exist" - exit -} - -set device [get_global_assignment -name DEVICE] -set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY] - -if [is_project_open] { - project_close -} - -generateBuildID_Verilog -generateCDF $revision $device $outpath + +# Build TimeStamp Verilog Module +# Jeff Wiencrot - 8/1/2011 +# Sorgelig - 02/11/2019 +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate "`define BUILD_DATE \"[clock format [ clock seconds ] -format %y%m%d]\"" + + # Create a Verilog file for output + set outputFileName "build_id.v" + + set fileData "" + if { [file exists $outputFileName]} { + set outputFile [open $outputFileName "r"] + set fileData [read $outputFile] + close $outputFile + } + + if {$buildDate ne $fileData} { + set outputFile [open $outputFileName "w"] + puts -nonewline $outputFile $buildDate + close $outputFile + # Send confirmation message to the Messages window + post_message "Generated: [pwd]/$outputFileName: $buildDate" + } +} + +# Build CDF file +# Sorgelig - 17/2/2018 +proc generateCDF {revision device outpath} { + + set outputFileName "jtag.cdf" + set outputFile [open $outputFileName "w"] + + puts $outputFile "JedecChain;" + puts $outputFile " FileRevision(JESD32A);" + puts $outputFile " DefaultMfr(6E);" + puts $outputFile "" + puts $outputFile " P ActionCode(Ign)" + puts $outputFile " Device PartName(SOCVHPS) MfrSpec(OpMask(0));" + puts $outputFile " P ActionCode(Cfg)" + puts $outputFile " Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));" + puts $outputFile "ChainEnd;" + puts $outputFile "" + puts $outputFile "AlteraBegin;" + puts $outputFile " ChainType(JTAG);" + puts $outputFile "AlteraEnd;" +} + +set project_name [lindex $quartus(args) 1] +set revision [lindex $quartus(args) 2] + +if {[project_exists $project_name]} { + if {[string equal "" $revision]} { + project_open $project_name -revision [get_current_revision $project_name] + } else { + project_open $project_name -revision $revision + } +} else { + post_message -type error "Project $project_name does not exist" + exit +} + +set device [get_global_assignment -name DEVICE] +set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY] + +if [is_project_open] { + project_close +} + +generateBuildID_Verilog +generateCDF $revision $device $outpath diff --git a/sys/ddr_svc.sv b/sys/ddr_svc.sv index abcd4fa..ed24d4e 100644 --- a/sys/ddr_svc.sv +++ b/sys/ddr_svc.sv @@ -1,108 +1,108 @@ -// -// Copyright (c) 2020 Alexey Melnikov -// -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// ------------------------------------------ -// - -// 16-bit version - -module ddr_svc -( - input clk, - - input ram_waitrequest, - output [7:0] ram_burstcnt, - output [28:0] ram_addr, - input [63:0] ram_readdata, - input ram_read_ready, - output reg ram_read, - output [63:0] ram_writedata, - output [7:0] ram_byteenable, - output reg ram_write, - - output [7:0] ram_bcnt, - - input [31:3] ch0_addr, - input [7:0] ch0_burst, - output [63:0] ch0_data, - input ch0_req, - output ch0_ready, - - input [31:3] ch1_addr, - input [7:0] ch1_burst, - output [63:0] ch1_data, - input ch1_req, - output ch1_ready -); - -assign ram_burstcnt = ram_burst; -assign ram_byteenable = 8'hFF; -assign ram_addr = ram_address; -assign ram_writedata = 0; - -assign ch0_data = ram_q[0]; -assign ch1_data = ram_q[1]; -assign ch0_ready = ready[0]; -assign ch1_ready = ready[1]; - -reg [7:0] ram_burst; -reg [63:0] ram_q[2]; -reg [31:3] ram_address; -reg [1:0] ack = 0; -reg [1:0] ready; -reg state = 0; -reg ch = 0; - -always @(posedge clk) begin - ready <= 0; - - if(!ram_waitrequest) begin - ram_read <= 0; - ram_write <= 0; - - case(state) - 0: if(ch0_req != ack[0]) begin - ack[0] <= ch0_req; - ram_address <= ch0_addr; - ram_burst <= ch0_burst; - ram_read <= 1; - ch <= 0; - ram_bcnt <= 8'hFF; - state <= 1; - end - else if(ch1_req != ack[1]) begin - ack[1] <= ch1_req; - ram_address <= ch1_addr; - ram_burst <= ch1_burst; - ram_read <= 1; - ch <= 1; - ram_bcnt <= 8'hFF; - state <= 1; - end - 1: begin - if(ram_read_ready) begin - ram_bcnt <= ram_bcnt + 1'd1; - ram_q[ch] <= ram_readdata; - ready[ch] <= 1; - if ((ram_bcnt+2'd2) == ram_burst) state <= 0; - end - end - endcase - end -end - -endmodule +// +// Copyright (c) 2020 Alexey Melnikov +// +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// ------------------------------------------ +// + +// 16-bit version + +module ddr_svc +( + input clk, + + input ram_waitrequest, + output [7:0] ram_burstcnt, + output [28:0] ram_addr, + input [63:0] ram_readdata, + input ram_read_ready, + output reg ram_read, + output [63:0] ram_writedata, + output [7:0] ram_byteenable, + output reg ram_write, + + output [7:0] ram_bcnt, + + input [31:3] ch0_addr, + input [7:0] ch0_burst, + output [63:0] ch0_data, + input ch0_req, + output ch0_ready, + + input [31:3] ch1_addr, + input [7:0] ch1_burst, + output [63:0] ch1_data, + input ch1_req, + output ch1_ready +); + +assign ram_burstcnt = ram_burst; +assign ram_byteenable = 8'hFF; +assign ram_addr = ram_address; +assign ram_writedata = 0; + +assign ch0_data = ram_q[0]; +assign ch1_data = ram_q[1]; +assign ch0_ready = ready[0]; +assign ch1_ready = ready[1]; + +reg [7:0] ram_burst; +reg [63:0] ram_q[2]; +reg [31:3] ram_address; +reg [1:0] ack = 0; +reg [1:0] ready; +reg state = 0; +reg ch = 0; + +always @(posedge clk) begin + ready <= 0; + + if(!ram_waitrequest) begin + ram_read <= 0; + ram_write <= 0; + + case(state) + 0: if(ch0_req != ack[0]) begin + ack[0] <= ch0_req; + ram_address <= ch0_addr; + ram_burst <= ch0_burst; + ram_read <= 1; + ch <= 0; + ram_bcnt <= 8'hFF; + state <= 1; + end + else if(ch1_req != ack[1]) begin + ack[1] <= ch1_req; + ram_address <= ch1_addr; + ram_burst <= ch1_burst; + ram_read <= 1; + ch <= 1; + ram_bcnt <= 8'hFF; + state <= 1; + end + 1: begin + if(ram_read_ready) begin + ram_bcnt <= ram_bcnt + 1'd1; + ram_q[ch] <= ram_readdata; + ready[ch] <= 1; + if ((ram_bcnt+2'd2) == ram_burst) state <= 0; + end + end + endcase + end +end + +endmodule diff --git a/sys/f2sdram_safe_terminator.sv b/sys/f2sdram_safe_terminator.sv new file mode 100644 index 0000000..3586365 --- /dev/null +++ b/sys/f2sdram_safe_terminator.sv @@ -0,0 +1,250 @@ +// ============================================================================ +// +// f2sdram_safe_terminator for MiSTer platform +// +// ============================================================================ +// Copyright (c) 2021 bellwood420 +// +// Background: +// +// Terminating a transaction of burst writing(/reading) in its midstream +// seems to cause an illegal state to f2sdram interface. +// +// Forced reset request that occurs when loading other core is inevitable. +// +// So if it happens exactly within the transaction period, +// unexpected issues with accessing to f2sdram interface will be caused +// in next loaded core. +// +// It seems that only way to reset broken f2sdram interface is to reset +// whole SDRAM Controller Subsystem from HPS via permodrst register +// in Reset Manager. +// But it cannot be done safely while Linux is running. +// It is usually done when cold or warm reset is issued in HPS. +// +// Main_MiSTer is issuing reset for FPGA <> HPS bridges +// via brgmodrst register in Reset Manager when loading rbf. +// But it has no effect on f2sdram interface. +// f2sdram interface seems to belong to SDRAM Controller Subsystem +// rather than FPGA-to-HPS bridge. +// +// Main_MiSTer is also trying to issuing reset for f2sdram ports +// via fpgaportrst register in SDRAM Controller Subsystem when loading rbf. +// But according to the Intel's document, fpgaportrst register can be +// used to stretch the port reset. +// It seems that it cannot be used to assert the port reset. +// +// According to the Intel's document, there seems to be a reset port on +// Avalon-MM slave interface, but it cannot be found in Qsys generated HDL. +// +// To conclude, the only thing FPGA can do is not to break the transaction. +// ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +// +// Purpose: +// To prevent the issue, this module completes ongoing transaction +// on behalf of user logic, when reset is asserted. +// +// Usage: +// Insert this module into the bus line between +// f2sdram (Avalon-MM slave) and user logic (Avalon-MM master). +// +// Notice: +// Asynchronous reset request is not supported. +// Please feed reset request synchronized to clock. +// +module f2sdram_safe_terminator #( + parameter DATA_WIDTH = 64, + parameter BURSTCOUNT_WIDTH = 8 +) ( + // clk should be the same as one provided to f2sdram port + // clk should not be stop when reset is asserted + input clk, + // rst_req_sync should be synchronized to clk + // Asynchronous reset request is not supported + input rst_req_sync, + + // Master port: connecting to Alavon-MM slave(f2sdram) + input waitrequest_master, + output [BURSTCOUNT_WIDTH-1:0] burstcount_master, + output [ADDRESS_WITDH-1:0] address_master, + input [DATA_WIDTH-1:0] readdata_master, + input readdatavalid_master, + output read_master, + output [DATA_WIDTH-1:0] writedata_master, + output [BYTEENABLE_WIDTH-1:0] byteenable_master, + output write_master, + + // Slave port: connecting to Alavon-MM master(user logic) + output waitrequest_slave, + input [BURSTCOUNT_WIDTH-1:0] burstcount_slave, + input [ADDRESS_WITDH-1:0] address_slave, + output [DATA_WIDTH-1:0] readdata_slave, + output readdatavalid_slave, + input read_slave, + input [DATA_WIDTH-1:0] writedata_slave, + input [BYTEENABLE_WIDTH-1:0] byteenable_slave, + input write_slave +); + +localparam BYTEENABLE_WIDTH = DATA_WIDTH/8; +localparam ADDRESS_WITDH = 32-$clog2(BYTEENABLE_WIDTH); + +/* +* Capture init reset deaseert +*/ +reg init_reset_deasserted = 1'b0; + +always_ff @(posedge clk) begin + if (!rst_req_sync) begin + init_reset_deasserted <= 1'b1; + end +end + +/* +* Lock stage +*/ +reg lock_stage = 1'b0; + +always_ff @(posedge clk) begin + if (rst_req_sync) begin + // Reset assert + if (init_reset_deasserted) begin + lock_stage <= 1'b1; + end + end + else begin + // Reset deassert + lock_stage <= 1'b0; + end +end + +/* +* Write burst transaction observer +*/ +reg state_write = 1'b0; +wire next_state_write; + +wire burst_write_start = !state_write && next_state_write; +wire valid_write_data = state_write && !waitrequest_master; +wire burst_write_end = state_write && (write_burstcounter == write_burstcount_latch - 1'd1); +wire valid_non_burst_write = !state_write && write_slave && (burstcount_slave == 1) && !waitrequest_master; + +reg [BURSTCOUNT_WIDTH-1:0] write_burstcounter = 0; +reg [BURSTCOUNT_WIDTH-1:0] write_burstcount_latch = 0; +reg [ADDRESS_WITDH-1:0] write_address_latch = 0; + +always_ff @(posedge clk) begin + state_write <= next_state_write; + + if (burst_write_start) begin + write_burstcounter <= waitrequest_master ? 1'd0 : 1'd1; + write_burstcount_latch <= burstcount_slave; + write_address_latch <= address_slave; + end + else if (valid_write_data) begin + write_burstcounter <= write_burstcounter + 1'd1; + end +end + +always_comb begin + if (!state_write) begin + if (valid_non_burst_write) + next_state_write = 1'b0; + else if (write_slave) + next_state_write = 1'b1; + else + next_state_write = 1'b0; + end + else begin + if (burst_write_end) + next_state_write = 1'b0; + else + next_state_write = 1'b1; + end +end + +reg [BURSTCOUNT_WIDTH-1:0] write_terminate_counter = 0; +reg [BURSTCOUNT_WIDTH-1:0] burstcount_latch = 0; +reg [ADDRESS_WITDH-1:0] address_latch = 0; + +reg terminating = 0; +reg read_terminating = 0; +reg write_terminating = 0; + +wire on_write_transaction = state_write && next_state_write; +wire on_start_write_transaction = !state_write && next_state_write; + +always_ff @(posedge clk) begin + if (rst_req_sync) begin + // Reset assert + if (init_reset_deasserted) begin + if (!lock_stage) begin + // Even not knowing reading is in progress or not, + // if it is in progress, it will finish at some point, and no need to do anything. + // Assume that reading is in progress when we are not on write transaction. + burstcount_latch <= burstcount_slave; + address_latch <= address_slave; + terminating <= 1; + + if (on_write_transaction) begin + write_terminating <= 1; + burstcount_latch <= write_burstcount_latch; + address_latch <= write_address_latch; + write_terminate_counter <= waitrequest_master ? write_burstcounter : write_burstcounter + 1'd1; + end + else if (on_start_write_transaction) begin + if (!valid_non_burst_write) begin + write_terminating <= 1; + write_terminate_counter <= waitrequest_master ? 1'd0 : 1'd1; + end + end + else if (read_slave && waitrequest_master) begin + // Need to keep read signal, burstcount and address until waitrequest_master deasserted + read_terminating <= 1; + end + end + else if (!waitrequest_master) begin + read_terminating <= 0; + end + end + end + else begin + // Reset deassert + if (!write_terminating) terminating <= 0; + read_terminating <= 0; + end + + if (write_terminating) begin + // Continue write transaction until the end + if (!waitrequest_master) write_terminate_counter <= write_terminate_counter + 1'd1; + if (write_terminate_counter == burstcount_latch - 1'd1) write_terminating <= 0; + end +end + +/* +* Bus mux depending on the stage. +*/ +always_comb begin + if (terminating) begin + burstcount_master = burstcount_latch; + address_master = address_latch; + read_master = read_terminating; + write_master = write_terminating; + byteenable_master = 0; + end + else begin + burstcount_master = burstcount_slave; + address_master = address_slave; + read_master = read_slave; + byteenable_master = byteenable_slave; + write_master = write_slave; + end +end + +// Just passing master <-> slave +assign writedata_master = writedata_slave; +assign readdata_slave = readdata_master; +assign readdatavalid_slave = readdatavalid_master; +assign waitrequest_slave = waitrequest_master; + +endmodule diff --git a/sys/gamma_corr.sv b/sys/gamma_corr.sv index 7fd9368..321b83f 100644 --- a/sys/gamma_corr.sv +++ b/sys/gamma_corr.sv @@ -32,8 +32,10 @@ always @(posedge clk_vid) begin reg [7:0] R_gamma, G_gamma; reg hs,vs,hb,vb; reg [1:0] ctr = 0; + reg old_ce; - if(ce_pix) begin + old_ce <= ce_pix; + if(~old_ce & ce_pix) begin {R_in,G_in,B_in} <= RGB_in; hs <= HSync; vs <= VSync; hb <= HBlank; vb <= VBlank; diff --git a/sys/hdmi_config.sv b/sys/hdmi_config.sv deleted file mode 100644 index 775a560..0000000 --- a/sys/hdmi_config.sv +++ /dev/null @@ -1,239 +0,0 @@ - -module hdmi_config -( - // Host Side - input iCLK, - input iRST_N, - - input dvi_mode, - input audio_96k, - input [1:0] limited, - input ypbpr, - - output reg done, - - // I2C Side - output I2C_SCL, - inout I2C_SDA -); - -// Internal Registers/Wires -reg mI2C_GO = 0; -wire mI2C_END; -wire mI2C_ACK; -reg [15:0] LUT_DATA; -reg [7:0] LUT_INDEX = 0; - -i2c #(50_000_000, 20_000) i2c_av -( - .CLK(iCLK), - - .I2C_SCL(I2C_SCL), // I2C CLOCK - .I2C_SDA(I2C_SDA), // I2C DATA - - .I2C_ADDR('h39), // 0x39 is the Slave Address of the ADV7513 chip! - .I2C_WLEN(1), - .I2C_WDATA1(init_data[LUT_INDEX][15:8]), // SUB_ADDR - .I2C_WDATA2(init_data[LUT_INDEX][7:0]), // DATA - .START(mI2C_GO), // START transfer - .READ(0), - .END(mI2C_END), // END transfer - .ACK(mI2C_ACK) // ACK -); - -////////////////////// Config Control //////////////////////////// -always@(posedge iCLK or negedge iRST_N) begin - reg [1:0] mSetup_ST = 0; - - if(!iRST_N) begin - LUT_INDEX <= 0; - mSetup_ST <= 0; - mI2C_GO <= 0; - done <= 0; - end else begin - if(init_data[LUT_INDEX] != 16'hFFFF) begin - case(mSetup_ST) - 0: begin - mI2C_GO <= 1; - mSetup_ST <= 1; - end - 1: if(~mI2C_END) mSetup_ST <= 2; - 2: begin - mI2C_GO <= 0; - if(mI2C_END) begin - mSetup_ST <= 0; - if(!mI2C_ACK) LUT_INDEX <= LUT_INDEX + 8'd1; - end - end - endcase - end - else done <= 1; - end -end - -//////////////////////////////////////////////////////////////////// -///////////////////// Config Data LUT ////////////////////////// - -wire [15:0] init_data[82] = -'{ - 16'h9803, // ADI required Write. - - {8'hD6, 8'b1100_0000}, // [7:6] HPD Control... - // 00 = HPD is from both HPD pin or CDC HPD - // 01 = HPD is from CDC HPD - // 10 = HPD is from HPD pin - // 11 = HPD is always high - - 16'h4110, // Power Down control - 16'h9A70, // ADI required Write. - 16'h9C30, // ADI required Write. - {8'h9D, 8'b0110_0001}, // [7:4] must be b0110!. - // [3:2] b00 = Input clock not divided. b01 = Clk divided by 2. b10 = Clk divided by 4. b11 = invalid! - // [1:0] must be b01! - 16'hA2A4, // ADI required Write. - 16'hA3A4, // ADI required Write. - 16'hE0D0, // ADI required Write. - - - 16'h35_40, - 16'h36_D9, - 16'h37_0A, - 16'h38_00, - 16'h39_2D, - 16'h3A_00, - - {8'h16, 8'b0011_1000}, // Output Format 444 [7]=0. - // [6] must be 0! - // Colour Depth for Input Video data [5:4] b11 = 8-bit. - // Input Style [3:2] b10 = Style 1 (ignored when using 444 input). - // DDR Input Edge falling [1]=0 (not using DDR atm). - // Output Colour Space RGB [0]=0. - - {8'h17, 8'b01100010}, // Aspect ratio 16:9 [1]=1, 4:3 [1]=0 - - {8'h18, ypbpr ? 8'h88 : limited[0] ? 8'h8D : limited[1] ? 8'h8E : 8'h00}, // CSC Scaling Factors and Coefficients for RGB Full->Limited. - {8'h19, ypbpr ? 8'h2E : limited[0] ? 8'hBC : 8'hFE}, // Taken from table in ADV7513 Programming Guide. - {8'h1A, ypbpr ? 8'h18 : 8'h00}, // CSC Channel A. - {8'h1B, ypbpr ? 8'h93 : 8'h00}, - {8'h1C, ypbpr ? 8'h1F : 8'h00}, - {8'h1D, ypbpr ? 8'h3F : 8'h00}, - {8'h1E, ypbpr ? 8'h08 : 8'h01}, - {8'h1F, 8'h00}, - - {8'h20, ypbpr ? 8'h03 : 8'h00}, // CSC Channel B. - {8'h21, ypbpr ? 8'h67 : 8'h00}, - {8'h22, ypbpr ? 8'h0B : limited[0] ? 8'h0D : 8'h0E}, - {8'h23, ypbpr ? 8'h71 : limited[0] ? 8'hBC : 8'hFE}, - {8'h24, ypbpr ? 8'h01 : 8'h00}, - {8'h25, ypbpr ? 8'h28 : 8'h00}, - {8'h26, ypbpr ? 8'h00 : 8'h01}, - {8'h27, 8'h00}, - - {8'h28, ypbpr ? 8'h1E : 8'h00}, // CSC Channel C. - {8'h29, ypbpr ? 8'h21 : 8'h00}, - {8'h2A, ypbpr ? 8'h19 : 8'h00}, - {8'h2B, ypbpr ? 8'hB2 : 8'h00}, - {8'h2C, ypbpr ? 8'h08 : limited[0] ? 8'h0D : 8'h0E}, - {8'h2D, ypbpr ? 8'h2D : limited[0] ? 8'hBC : 8'hFE}, - {8'h2E, ypbpr ? 8'h08 : 8'h01}, - {8'h2F, 8'h00}, - - {8'h3B, 8'b0000_0000}, // Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx. - - 16'h4000, // General Control Packet Enable - - {8'h48, 8'b0000_1000}, // [6]=0 Normal bus order! - // [5] DDR Alignment. - // [4:3] b01 Data right justified (for YCbCr 422 input modes). - - 16'h49A8, // ADI required Write. - 16'h4C00, // ADI required Write. - - {8'h55, 8'b0001_0000}, // [7] must be 0!. Set RGB444 in AVinfo Frame [6:5], Set active format [4]. - // AVI InfoFrame Valid [4]. - // Bar Info [3:2] b00 Bars invalid. b01 Bars vertical. b10 Bars horizontal. b11 Bars both. - // Scan Info [1:0] b00 (No data). b01 TV. b10 PC. b11 None. - - {8'h57, 1'b0, // [7] IT Content. 0 - No. 1 - Yes (type set in register h59). - 3'b000, // [6:4] Color space (ignored for RGB) - (ypbpr | limited) ? 2'b01 : 2'b10, // [3:2] RGB Quantization range - 2'b00}, // [1:0] Non-Uniform Scaled: 00 - None. 01 - Horiz. 10 - Vert. 11 - Both. - - 16'h7301, - - {8'h94, 8'b1000_0000}, // [7]=1 HPD Interrupt ENabled. - - 16'h9902, // ADI required Write. - 16'h9B18, // ADI required Write. - - 16'h9F00, // ADI required Write. - - {8'hA1, 8'b0000_0000}, // [6]=1 Monitor Sense Power Down DISabled. - - 16'hA408, // ADI required Write. - 16'hA504, // ADI required Write. - 16'hA600, // ADI required Write. - 16'hA700, // ADI required Write. - 16'hA800, // ADI required Write. - 16'hA900, // ADI required Write. - 16'hAA00, // ADI required Write. - 16'hAB40, // ADI required Write. - - {8'hAF, 6'b0000_01,~dvi_mode,1'b0}, // [7]=0 HDCP Disabled. - // [6:5] must be b00! - // [4]=0 Current frame is unencrypted - // [3:2] must be b01! - // [1]=1 HDMI Mode. - // [0] must be b0! - - 16'hB900, // ADI required Write. - - {8'hBA, 8'b0110_0000}, // [7:5] Input Clock delay... - // b000 = -1.2ns. - // b001 = -0.8ns. - // b010 = -0.4ns. - // b011 = No delay. - // b100 = 0.4ns. - // b101 = 0.8ns. - // b110 = 1.2ns. - // b111 = 1.6ns. - - 16'hBB00, // ADI required Write. - - 16'hDE9C, // ADI required Write. - 16'hE460, // ADI required Write. - 16'hFA7D, // Nbr of times to search for good phase - - - // (Audio stuff on Programming Guide, Page 66)... - - {8'h0A, 8'b0000_0000}, // [6:4] Audio Select. b000 = I2S. - // [3:2] Audio Mode. (HBR stuff, leave at 00!). - - {8'h0B, 8'b0000_1110}, // - - {8'h0C, 8'b0000_0100}, // [7] 0 = Use sampling rate from I2S stream. 1 = Use samp rate from I2C Register. - // [6] 0 = Use Channel Status bits from stream. 1 = Use Channel Status bits from I2C register. - // [2] 1 = I2S0 Enable. - // [1:0] I2S Format: 00 = Standard. 01 = Right Justified. 10 = Left Justified. 11 = AES. - - {8'h0D, 8'b0001_0000}, // [4:0] I2S Bit (Word) Width for Right-Justified. - {8'h14, 8'b0000_0010}, // [3:0] Audio Word Length. b0010 = 16 bits. - {8'h15, audio_96k, 7'b010_0000}, // I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz. - // Input ID [3:1] b000 (0) = 24-bit RGB 444 or YCrCb 444 with Separate Syncs. - - // Audio Clock Config - 16'h0100, // - audio_96k ? 16'h0230 : 16'h0218, // Set N Value 12288/6144 - 16'h0300, // - - 16'h0701, // - 16'h0822, // Set CTS Value 74250 - 16'h090A, // - - 16'hFFFF // END -}; - -//////////////////////////////////////////////////////////////////// - -endmodule \ No newline at end of file diff --git a/sys/hps_io.v b/sys/hps_io.sv similarity index 74% rename from sys/hps_io.v rename to sys/hps_io.sv index 23ade3f..92cdf77 100644 --- a/sys/hps_io.v +++ b/sys/hps_io.sv @@ -24,14 +24,13 @@ // Use buffer to access SD card. It's time-critical part. // // WIDE=1 for 16 bit file I/O -// VDNUM 1-4 -module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0) +// VDNUM 1..10 +// BLKSZ 0..7: 0 = 128, 1 = 256, 2 = 512(default), .. 7 = 16384 +// +module hps_io #(parameter CONF_STR, CONF_STR_BRAM=0, PS2DIV=0, WIDE=0, VDNUM=1, BLKSZ=2, PS2WE=0, STRLEN=$size(CONF_STR)>>3) ( input clk_sys, - inout [45:0] HPS_BUS, - - // parameter STRLEN and the actual length of conf_str have to match - input [(8*STRLEN)-1:0] conf_str, + inout [48:0] HPS_BUS, // buttons up to 32 output reg [31:0] joystick_0, @@ -40,14 +39,28 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0) output reg [31:0] joystick_3, output reg [31:0] joystick_4, output reg [31:0] joystick_5, - + // analog -127..+127, Y: [15:8], X: [7:0] - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output reg [15:0] joystick_analog_2, - output reg [15:0] joystick_analog_3, - output reg [15:0] joystick_analog_4, - output reg [15:0] joystick_analog_5, + output reg [15:0] joystick_l_analog_0, + output reg [15:0] joystick_l_analog_1, + output reg [15:0] joystick_l_analog_2, + output reg [15:0] joystick_l_analog_3, + output reg [15:0] joystick_l_analog_4, + output reg [15:0] joystick_l_analog_5, + + output reg [15:0] joystick_r_analog_0, + output reg [15:0] joystick_r_analog_1, + output reg [15:0] joystick_r_analog_2, + output reg [15:0] joystick_r_analog_3, + output reg [15:0] joystick_r_analog_4, + output reg [15:0] joystick_r_analog_5, + + input [15:0] joystick_0_rumble, // 15:8 - 'large' rumble motor magnitude, 7:0 'small' rumble motor magnitude + input [15:0] joystick_1_rumble, + input [15:0] joystick_2_rumble, + input [15:0] joystick_3_rumble, + input [15:0] joystick_4_rumble, + input [15:0] joystick_5_rumble, // paddle 0..255 output reg [7:0] paddle_0, @@ -65,69 +78,6 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0) output reg [8:0] spinner_4, output reg [8:0] spinner_5, - output [1:0] buttons, - output forced_scandoubler, - output direct_video, - - output reg [63:0] status, - input [63:0] status_in, - input status_set, - input [15:0] status_menumask, - - input info_req, - input [7:0] info, - - //toggle to force notify of video mode change - input new_vmode, - - // SD config - output reg [VD:0] img_mounted, // signaling that new image has been mounted - output reg img_readonly, // mounted as read only. valid only for active bit in img_mounted - output reg [63:0] img_size, // size of image in bytes. valid only for active bit in img_mounted - - // SD block level access - input [31:0] sd_lba, - input [VD:0] sd_rd, // only single sd_rd can be active at any given time - input [VD:0] sd_wr, // only single sd_wr can be active at any given time - output reg sd_ack, - - // do not use in new projects. - // CID and CSD are fake except CSD image size field. - input sd_conf, - output reg sd_ack_conf, - - // SD byte level access. Signals for 2-PORT altsyncram. - output reg [AW:0] sd_buff_addr, - output reg [DW:0] sd_buff_dout, - input [DW:0] sd_buff_din, - output reg sd_buff_wr, - input [15:0] sd_req_type, - - // ARM -> FPGA download - output reg ioctl_download = 0, // signal indicating an active download - output reg [15:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr, - output reg [26:0] ioctl_addr, // in WIDE mode address will be incremented by 2 - output reg [DW:0] ioctl_dout, - output reg ioctl_upload = 0, // signal indicating an active upload - input [DW:0] ioctl_din, - output reg ioctl_rd, - output reg [31:0] ioctl_file_ext, - input ioctl_wait, - - // [15]: 0 - unset, 1 - set. [1:0]: 0 - none, 1 - 32MB, 2 - 64MB, 3 - 128MB - // [14]: debug mode: [8]: 1 - phase up, 0 - phase down. [7:0]: amount of shift. - output reg [15:0] sdram_sz, - - // RTC MSM6242B layout - output reg [64:0] RTC, - - // Seconds since 1970-01-01 00:00:00 - output reg [32:0] TIMESTAMP, - - // UART flags - input [15:0] uart_mode, - // ps2 keyboard emulation output ps2_kbd_clk_out, output ps2_kbd_data_out, @@ -151,8 +101,70 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0) output reg [24:0] ps2_mouse = 0, output reg [15:0] ps2_mouse_ext = 0, // 15:8 - reserved(additional buttons), 7:0 - wheel movements + output [1:0] buttons, + output forced_scandoubler, + output direct_video, + input video_rotated, + + //toggle to force notify of video mode change + input new_vmode, + inout [21:0] gamma_bus, + output reg [127:0] status, + input [127:0] status_in, + input status_set, + input [15:0] status_menumask, + + input info_req, + input [7:0] info, + + // SD config + output reg [VD:0] img_mounted, // signaling that new image has been mounted + output reg img_readonly, // mounted as read only. valid only for active bit in img_mounted + output reg [63:0] img_size, // size of image in bytes. valid only for active bit in img_mounted + + // SD block level access + input [31:0] sd_lba[VDNUM], + input [5:0] sd_blk_cnt[VDNUM], // number of blocks-1, total size ((sd_blk_cnt+1)*(1<<(BLKSZ+7))) must be <= 16384! + input [VD:0] sd_rd, + input [VD:0] sd_wr, + output reg [VD:0] sd_ack, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [AW:0] sd_buff_addr, + output reg [DW:0] sd_buff_dout, + input [DW:0] sd_buff_din[VDNUM], + output reg sd_buff_wr, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [15:0] ioctl_index, // menu index used to upload the file + output reg ioctl_wr, + output reg [26:0] ioctl_addr, // in WIDE mode address will be incremented by 2 + output reg [DW:0] ioctl_dout, + output reg ioctl_upload = 0, // signal indicating an active upload + input ioctl_upload_req, // request to save (must be supported on HPS side for specific core) + input [7:0] ioctl_upload_index, + input [DW:0] ioctl_din, + output reg ioctl_rd, + output reg [31:0] ioctl_file_ext, + input ioctl_wait, + + // [15]: 0 - unset, 1 - set. [1:0]: 0 - none, 1 - 32MB, 2 - 64MB, 3 - 128MB + // [14]: debug mode: [8]: 1 - phase up, 0 - phase down. [7:0]: amount of shift. + output reg [15:0] sdram_sz, + + // RTC MSM6242B layout + output reg [64:0] RTC, + + // Seconds since 1970-01-01 00:00:00 + output reg [32:0] TIMESTAMP, + + // UART flags + output reg [7:0] uart_mode, + output reg [31:0] uart_speed, + // for core-specific extensions inout [35:0] EXT_BUS ); @@ -160,10 +172,8 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0) assign EXT_BUS[31:16] = HPS_BUS[31:16]; assign EXT_BUS[35:33] = HPS_BUS[35:33]; -localparam MAX_W = $clog2((512 > (STRLEN+1)) ? 512 : (STRLEN+1))-1; - localparam DW = (WIDE) ? 15 : 7; -localparam AW = (WIDE) ? 7 : 8; +localparam AW = (WIDE) ? 12 : 13; localparam VD = VDNUM-1; wire io_strobe= HPS_BUS[33]; @@ -186,22 +196,18 @@ assign forced_scandoubler = cfg[4]; //cfg[5] - ypbpr handled in sys_top assign direct_video = cfg[10]; -// command byte read by the io controller -wire [15:0] sd_cmd = -{ - 2'b00, - (VDNUM>=4) ? sd_wr[3] : 1'b0, - (VDNUM>=3) ? sd_wr[2] : 1'b0, - (VDNUM>=2) ? sd_wr[1] : 1'b0, +reg [3:0] sdn; +reg [3:0] sd_rrb = 0; +always_comb begin + int n, i; - (VDNUM>=4) ? sd_rd[3] : 1'b0, - (VDNUM>=3) ? sd_rd[2] : 1'b0, - (VDNUM>=2) ? sd_rd[1] : 1'b0, - - 4'h5, sd_conf, 1'b1, - sd_wr[0], - sd_rd[0] -}; + sdn = 0; + for(i = VDNUM - 1; i >= 0; i = i - 1) begin + n = i + sd_rrb; + if(n >= VDNUM) n = n - VDNUM; + if(sd_wr[n] | sd_rd[n]) sdn = n[3:0]; + end +end ///////////////////////////////////////////////////////// @@ -218,13 +224,26 @@ video_calc video_calc .vs_hdmi(HPS_BUS[44]), .f1(HPS_BUS[45]), .new_vmode(new_vmode), + .video_rotated(video_rotated), - .par_num(byte_cnt[3:0]), + .par_num(byte_cnt[4:0]), .dout(vc_dout) ); ///////////////////////////////////////////////////////// +localparam MAX_W = $clog2((64 > (STRLEN+2)) ? 64 : (STRLEN+2))-1; + +wire [7:0] conf_byte; +generate + if(CONF_STR_BRAM) begin + confstr_rom #(CONF_STR, STRLEN) confstr_rom(.*, .conf_addr(byte_cnt - 1'd1)); + end + else begin + assign conf_byte = CONF_STR[{(STRLEN - byte_cnt),3'b000} +:8]; + end +endgenerate + assign gamma_bus[20:0] = {clk_sys, gamma_en, gamma_wr, gamma_wr_addr, gamma_value}; reg gamma_en; reg gamma_wr; @@ -236,6 +255,8 @@ wire pressed = (ps2_key_raw[15:8] != 8'hf0); wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0)); reg [MAX_W:0] byte_cnt; +reg [3:0] sdn_ack; +wire [15:0] disk = 16'd1 << io_din[11:8]; always@(posedge clk_sys) begin : uio_block reg [15:0] cmd; @@ -244,10 +265,15 @@ always@(posedge clk_sys) begin : uio_block reg [3:0] pdsp_idx; reg ps2skip = 0; reg [3:0] stflg = 0; - reg [63:0] status_req; + reg[127:0] status_req; reg old_status_set = 0; + reg old_upload_req = 0; + reg upload_req = 0; reg old_info = 0; reg [7:0] info_n = 0; + reg [15:0] tmp1; + reg [7:0] tmp2; + reg [3:0] sdn_r; old_status_set <= status_set; if(~old_status_set & status_set) begin @@ -255,6 +281,9 @@ always@(posedge clk_sys) begin : uio_block status_req <= status_in; end + old_upload_req <= ioctl_upload_req; + if(~old_upload_req & ioctl_upload_req) upload_req <= 1; + old_info <= info_req; if(~old_info & info_req) info_n <= info; @@ -279,7 +308,6 @@ always@(posedge clk_sys) begin : uio_block cmd <= 0; byte_cnt <= 0; sd_ack <= 0; - sd_ack_conf <= 0; io_dout <= 0; ps2skip <= 0; img_mounted <= 0; @@ -292,23 +320,35 @@ always@(posedge clk_sys) begin : uio_block if(byte_cnt == 0) begin cmd <= io_din; - case(io_din) - 'h19: sd_ack_conf <= 1; - 'h17, - 'h18: sd_ack <= 1; - 'h29: io_dout <= {4'hA, stflg}; - 'h2B: io_dout <= 1; - 'h2F: io_dout <= 1; - 'h32: io_dout <= gamma_bus[21]; - 'h36: begin io_dout <= info_n; info_n <= 0; end - 'h39: io_dout <= 1; + casex(io_din) + 'h16: begin io_dout <= {1'b1, sd_blk_cnt[sdn], BLKSZ[2:0], sdn, sd_wr[sdn], sd_rd[sdn]}; sdn_r <= sdn; end + 'h0X17, + 'h0X18: begin sd_ack <= disk[VD:0]; sdn_ack <= io_din[11:8]; end + 'h29: io_dout <= {4'hA, stflg}; +`ifdef MISTER_DISABLE_ADAPTIVE + 'h2B: io_dout <= {HPS_BUS[48:46],4'b0110}; +`else + 'h2B: io_dout <= {HPS_BUS[48:46],4'b0111}; +`endif + 'h2F: io_dout <= 1; + 'h32: io_dout <= gamma_bus[21]; + 'h36: begin io_dout <= info_n; info_n <= 0; end + 'h39: io_dout <= 1; + 'h3C: if(upload_req) begin io_dout <= {ioctl_upload_index, 8'd1}; upload_req <= 0; end + 'h3E: io_dout <= 1; // shadow mask + 'h003F: io_dout <= joystick_0_rumble; + 'h013F: io_dout <= joystick_1_rumble; + 'h023F: io_dout <= joystick_2_rumble; + 'h033F: io_dout <= joystick_3_rumble; + 'h043F: io_dout <= joystick_4_rumble; + 'h053F: io_dout <= joystick_5_rumble; endcase sd_buff_addr <= 0; if(io_din == 5) ps2_key_raw <= 0; end else begin - case(cmd) + casex(cmd) // buttons and switches 'h01: cfg <= io_din; 'h02: if(byte_cnt==1) joystick_0[15:0] <= io_din; else joystick_0[31:16] <= io_din; @@ -350,47 +390,41 @@ always@(posedge clk_sys) begin : uio_block end // reading config string, returning a byte from string - 'h14: if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8]; + 'h14: if(byte_cnt <= STRLEN) io_dout[7:0] <= conf_byte; // reading sd card status - 'h16: if(!byte_cnt[MAX_W:3]) begin - case(byte_cnt[2:0]) - 1: io_dout <= sd_cmd; - 2: io_dout <= sd_lba[15:0]; - 3: io_dout <= sd_lba[31:16]; - 4: io_dout <= sd_req_type; + 'h16: if(!byte_cnt[MAX_W:2]) begin + case(byte_cnt[1:0]) + 1: sd_rrb <= (sd_rrb == VD) ? 4'd0 : (sd_rrb + 1'd1); + 2: io_dout <= sd_lba[sdn_r][15:0]; + 3: io_dout <= sd_lba[sdn_r][31:16]; endcase end - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 'h19, // send sector IO -> FPGA // flag that download begins - 'h17: begin + 'h0X17: begin sd_buff_dout <= io_din[DW:0]; b_wr <= 1; end // reading sd card write data - 'h18: begin + 'h0X18: begin if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - io_dout <= sd_buff_din; + io_dout <= sd_buff_din[sdn_ack]; end - // joystick analog + // joystick left analog 'h1a: if(!byte_cnt[MAX_W:2]) begin case(byte_cnt[1:0]) 1: {pdsp_idx,stick_idx} <= io_din[7:0]; // first byte is joystick index 2: case(stick_idx) - 0: joystick_analog_0 <= io_din; - 1: joystick_analog_1 <= io_din; - 2: joystick_analog_2 <= io_din; - 3: joystick_analog_3 <= io_din; - 4: joystick_analog_4 <= io_din; - 5: joystick_analog_5 <= io_din; + 0: joystick_l_analog_0 <= io_din; + 1: joystick_l_analog_1 <= io_din; + 2: joystick_l_analog_2 <= io_din; + 3: joystick_l_analog_3 <= io_din; + 4: joystick_l_analog_4 <= io_din; + 5: joystick_l_analog_5 <= io_din; 15: case(pdsp_idx) 0: paddle_0 <= io_din[7:0]; 1: paddle_1 <= io_din[7:0]; @@ -409,6 +443,21 @@ always@(posedge clk_sys) begin : uio_block endcase end + // joystick right analog + 'h3d: if(!byte_cnt[MAX_W:2]) begin + case(byte_cnt[1:0]) + 1: stick_idx <= io_din[3:0]; // first byte is joystick index + 2: case(stick_idx) + 0: joystick_r_analog_0 <= io_din; + 1: joystick_r_analog_1 <= io_din; + 2: joystick_r_analog_2 <= io_din; + 3: joystick_r_analog_3 <= io_din; + 4: joystick_r_analog_4 <= io_din; + 5: joystick_r_analog_5 <= io_din; + endcase + endcase + end + // notify image selection 'h1c: begin img_mounted <= io_din[VD:0] ? io_din[VD:0] : 1'b1; @@ -418,13 +467,17 @@ always@(posedge clk_sys) begin : uio_block // send image info 'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din; - // status, 64bit version - 'h1e: if(!byte_cnt[MAX_W:3]) begin - case(byte_cnt[2:0]) - 1: status[15:00] <= io_din; - 2: status[31:16] <= io_din; - 3: status[47:32] <= io_din; - 4: status[63:48] <= io_din; + // status, 128bit version + 'h1e: if(!byte_cnt[MAX_W:4]) begin + case(byte_cnt[3:0]) + 1: status[15:00] <= io_din; + 2: status[31:16] <= io_din; + 3: status[47:32] <= io_din; + 4: status[63:48] <= io_din; + 5: status[79:64] <= io_din; + 6: status[95:80] <= io_din; + 7: status[111:96] <= io_din; + 8: status[127:112] <= io_din; endcase end @@ -448,27 +501,28 @@ always@(posedge clk_sys) begin : uio_block 'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din; //Video res. - 'h23: if(!byte_cnt[MAX_W:4]) io_dout <= vc_dout; + 'h23: if(!byte_cnt[MAX_W:5]) io_dout <= vc_dout; //RTC 'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din; - //UART flags - 'h28: io_dout <= uart_mode; - //status set - 'h29: if(!byte_cnt[MAX_W:3]) begin - case(byte_cnt[2:0]) + 'h29: if(!byte_cnt[MAX_W:4]) begin + case(byte_cnt[3:0]) 1: io_dout <= status_req[15:00]; 2: io_dout <= status_req[31:16]; 3: io_dout <= status_req[47:32]; 4: io_dout <= status_req[63:48]; + 5: io_dout <= status_req[79:64]; + 6: io_dout <= status_req[95:80]; + 7: io_dout <= status_req[111:96]; + 8: io_dout <= status_req[127:112]; endcase end //menu mask 'h2E: if(byte_cnt == 1) io_dout <= status_menumask; - + //sdram size set 'h31: if(byte_cnt == 1) sdram_sz <= io_din; @@ -479,6 +533,15 @@ always@(posedge clk_sys) begin : uio_block {gamma_wr, gamma_value} <= {1'b1,io_din[7:0]}; if (byte_cnt[1:0] == 3) byte_cnt <= 1; end + + // UART + 'h3b: if(!byte_cnt[MAX_W:2]) begin + case(byte_cnt[1:0]) + 1: tmp2 <= io_din[7:0]; + 2: tmp1 <= io_din; + 3: {uart_speed, uart_mode} <= {io_din, tmp1, tmp2}; + endcase + end endcase end end @@ -566,7 +629,7 @@ always@(posedge clk_sys) begin : fio_block reg has_cmd; reg [26:0] addr; reg wr; - + ioctl_rd <= 0; ioctl_wr <= wr; wr <= 0; @@ -599,7 +662,7 @@ always@(posedge clk_sys) begin : fio_block FIO_FILE_TX: begin cnt <= cnt + 1'd1; - case(cnt) + case(cnt) 0: if(io_din[7:0] == 8'hAA) begin ioctl_addr <= 0; ioctl_upload <= 1; @@ -806,14 +869,15 @@ module video_calc input vs_hdmi, input f1, input new_vmode, + input video_rotated, - input [3:0] par_num, + input [4:0] par_num, output reg [15:0] dout ); always @(posedge clk_sys) begin case(par_num) - 1: dout <= {|vid_int, vid_nres}; + 1: dout <= {video_rotated, |vid_int, vid_nres}; 2: dout <= vid_hcnt[15:0]; 3: dout <= vid_hcnt[31:16]; 4: dout <= vid_vcnt[15:0]; @@ -826,29 +890,58 @@ always @(posedge clk_sys) begin 11: dout <= vid_pix[31:16]; 12: dout <= vid_vtime_hdmi[15:0]; 13: dout <= vid_vtime_hdmi[31:16]; + 14: dout <= vid_ccnt[15:0]; + 15: dout <= vid_ccnt[31:16]; + 16: dout <= vid_pixrep; + 17: dout <= vid_de_h; + 18: dout <= vid_de_v; default dout <= 0; endcase end reg [31:0] vid_hcnt = 0; reg [31:0] vid_vcnt = 0; +reg [31:0] vid_ccnt = 0; reg [7:0] vid_nres = 0; reg [1:0] vid_int = 0; +reg [7:0] vid_pixrep; +reg [15:0] vid_de_h; +reg [7:0] vid_de_v; always @(posedge clk_vid) begin integer hcnt; integer vcnt; - reg old_vs= 0, old_de = 0, old_vmode = 0; + integer ccnt; + reg [7:0] pcnt; + reg [7:0] de_v; + reg [15:0] de_h; + reg old_vs = 0, old_hs = 0, old_hs_vclk = 0, old_de = 0, old_de_vclk = 0, old_de1 = 0, old_vmode = 0; reg [3:0] resto = 0; reg calch = 0; + if(calch & de) ccnt <= ccnt + 1; + pcnt <= pcnt + 1'd1; + + old_hs_vclk <= hs; + de_h <= de_h + 1'd1; + if(old_hs_vclk & ~hs) de_h <= 1; + + old_de_vclk <= de; + if(calch & ~old_de_vclk & de) vid_de_h <= de_h; + if(ce_pix) begin old_vs <= vs; + old_hs <= hs; old_de <= de; + old_de1 <= old_de; + pcnt <= 1; if(~vs & ~old_de & de) vcnt <= vcnt + 1; if(calch & de) hcnt <= hcnt + 1; if(old_de & ~de) calch <= 0; + if(~old_de1 & old_de) vid_pixrep <= pcnt; + if(old_hs & ~hs) de_v <= de_v + 1'd1; + if(calch & ~old_de & de) vid_de_v <= de_v; if(old_vs & ~vs) begin vid_int <= {vid_int[0],f1}; @@ -862,10 +955,13 @@ always @(posedge clk_vid) begin if(&resto) vid_nres <= vid_nres + 1'd1; vid_hcnt <= hcnt; vid_vcnt <= vcnt; + vid_ccnt <= ccnt; end vcnt <= 0; hcnt <= 0; + ccnt <= 0; calch <= 1; + de_v <= 0; end end end @@ -927,3 +1023,23 @@ always @(posedge clk_100) begin end endmodule + +module confstr_rom #(parameter CONF_STR, STRLEN) +( + input clk_sys, + input [$clog2(STRLEN+1)-1:0] conf_addr, + output reg [7:0] conf_byte +); + +reg [7:0] rom[STRLEN]; + +initial begin + if( CONF_STR=="" ) + $readmemh("cfgstr.hex",rom); + else + for(int i = 0; i < STRLEN; i++) rom[i] = CONF_STR[((STRLEN-i)*8)-1 -:8]; +end + +always @ (posedge clk_sys) conf_byte <= rom[conf_addr]; + +endmodule diff --git a/sys/i2c.v b/sys/i2c.v index 01076c6..6da6a14 100644 --- a/sys/i2c.v +++ b/sys/i2c.v @@ -1,96 +1,103 @@ - -module i2c -( - input CLK, - - input START, - input READ, - input [6:0] I2C_ADDR, - input I2C_WLEN, // 0 - one byte, 1 - two bytes - input [7:0] I2C_WDATA1, - input [7:0] I2C_WDATA2, - output [7:0] I2C_RDATA, - output reg END = 1, - output reg ACK = 0, - - //I2C bus - output I2C_SCL, - inout I2C_SDA -); - - -// Clock Setting -parameter CLK_Freq = 50_000_000; // 50 MHz -parameter I2C_Freq = 400_000; // 400 KHz - -localparam I2C_FreqX2 = I2C_Freq*2; - -reg I2C_CLOCK; -reg [31:0] cnt; -wire [31:0] cnt_next = cnt + I2C_FreqX2; - -always @(posedge CLK) begin - cnt <= cnt_next; - if(cnt_next >= CLK_Freq) begin - cnt <= cnt_next - CLK_Freq; - I2C_CLOCK <= ~I2C_CLOCK; - end -end - -assign I2C_SCL = SCLK | I2C_CLOCK; -assign I2C_SDA = SDO[3] ? 1'bz : 1'b0; - -reg SCLK = 1; -reg [3:0] SDO = 4'b1111; -reg [0:7] rdata; - -assign I2C_RDATA = rdata; - -always @(posedge CLK) begin - reg old_clk; - reg old_st; - reg rd,len; - - reg [5:0] SD_COUNTER = 'b111111; - reg [0:31] SD; - - old_clk <= I2C_CLOCK; - old_st <= START; - - // delay to make sure SDA changed while SCL is stabilized at low - if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO[0] <= SD[SD_COUNTER[4:0]]; - SDO[3:1] <= SDO[2:0]; - - if(~old_st && START) begin - SCLK <= 1; - SDO <= 4'b1111; - ACK <= 0; - END <= 0; - rd <= READ; - len <= I2C_WLEN; - if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b0, 3'b011, 9'b111111111}; - else SD <= {2'b10, I2C_ADDR, 1'b0, 1'b1, I2C_WDATA1, 1'b1, I2C_WDATA2, 4'b1011}; - SD_COUNTER <= 0; - end else begin - if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin - SD_COUNTER <= SD_COUNTER + 6'd1; - case(SD_COUNTER) - 01: SCLK <= 0; - 10: ACK <= ACK | I2C_SDA; - 19: if(~rd) begin - ACK <= ACK | I2C_SDA; - if(~len) SD_COUNTER <= 29; - end - 20: if(rd) SCLK <= 1; - 23: if(rd) END <= 1; - 28: if(~rd) ACK <= ACK | I2C_SDA; - 29: if(~rd) SCLK <= 1; - 32: if(~rd) END <= 1; - endcase - - if(SD_COUNTER >= 11 && SD_COUNTER <= 18) rdata[SD_COUNTER[4:0]-11] <= I2C_SDA; - end - end -end - -endmodule + +module i2c +( + input CLK, + + input START, + input READ, + input [6:0] I2C_ADDR, + input I2C_WLEN, // 0 - one byte, 1 - two bytes + input [7:0] I2C_WDATA1, + input [7:0] I2C_WDATA2, + output [7:0] I2C_RDATA, + output reg END = 1, + output reg ACK = 0, + + //I2C bus + output I2C_SCL, + inout I2C_SDA +); + + +// Clock Setting +parameter CLK_Freq = 50_000_000; // 50 MHz +parameter I2C_Freq = 400_000; // 400 KHz + +localparam I2C_FreqX2 = I2C_Freq*2; + +reg I2C_CLOCK; +reg [31:0] cnt; +wire [31:0] cnt_next = cnt + I2C_FreqX2; + +always @(posedge CLK) begin + cnt <= cnt_next; + if(cnt_next >= CLK_Freq) begin + cnt <= cnt_next - CLK_Freq; + I2C_CLOCK <= ~I2C_CLOCK; + end +end + +assign I2C_SCL = (SCLK | I2C_CLOCK) ? 1'bZ : 1'b0; +assign I2C_SDA = SDO[3] ? 1'bz : 1'b0; + +reg SCLK; +reg [3:0] SDO; +reg [0:7] rdata; + +reg [5:0] SD_COUNTER; +reg [0:31] SD; + +initial begin + SD_COUNTER = 'b111111; + SD = 'hFFFF; + SCLK = 1; + SDO = 4'b1111; +end + +assign I2C_RDATA = rdata; + +always @(posedge CLK) begin + reg old_clk; + reg old_st; + reg rd,len; + + old_clk <= I2C_CLOCK; + old_st <= START; + + // delay to make sure SDA changed while SCL is stabilized at low + if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO[0] <= SD[SD_COUNTER[4:0]]; + SDO[3:1] <= SDO[2:0]; + + if(~old_st && START) begin + SCLK <= 1; + SDO <= 4'b1111; + ACK <= 0; + END <= 0; + rd <= READ; + len <= I2C_WLEN; + if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b1, 3'b011, 9'b111111111}; + else SD <= {2'b10, I2C_ADDR, 1'b0, 1'b1, I2C_WDATA1, 1'b1, I2C_WDATA2, 4'b1011}; + SD_COUNTER <= 0; + end else begin + if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin + SD_COUNTER <= SD_COUNTER + 6'd1; + case(SD_COUNTER) + 01: SCLK <= 0; + 10: ACK <= ACK | I2C_SDA; + 19: if(~rd) begin + ACK <= ACK | I2C_SDA; + if(~len) SD_COUNTER <= 29; + end + 20: if(rd) SCLK <= 1; + 23: if(rd) END <= 1; + 28: if(~rd) ACK <= ACK | I2C_SDA; + 29: if(~rd) SCLK <= 1; + 32: if(~rd) END <= 1; + endcase + + if(SD_COUNTER >= 11 && SD_COUNTER <= 18) rdata[SD_COUNTER[4:0]-11] <= I2C_SDA; + end + end +end + +endmodule diff --git a/sys/iir_filter.v b/sys/iir_filter.v index a5336e9..b8bcf4f 100644 --- a/sys/iir_filter.v +++ b/sys/iir_filter.v @@ -1,213 +1,213 @@ - -// 3-tap IIR filter for 2 channels. -// Copyright (C) 2020 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. -// -// You should have received a copy of the GNU General Public License along -// with this program; if not, write to the Free Software Foundation, Inc., -// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - -// -// Can be converted to 2-tap (coeff_x2 = 0, coeff_y2 = 0) or 1-tap (coeff_x1,2 = 0, coeff_y1,2 = 0) -// -module IIR_filter -#( - parameter use_params = 1, // set to 1 to use following parameters, 0 for input port variables. - parameter stereo = 1, // 0 for mono (input_l) - - parameter coeff_x = 0.00000774701983513660, // Base gain value for X. Float. Range: 0.0 ... 0.999(9) - parameter coeff_x0 = 3, // Gain scale factor for X0. Integer. Range -7 ... +7 - parameter coeff_x1 = 3, // Gain scale factor for X1. Integer. Range -7 ... +7 - parameter coeff_x2 = 1, // Gain scale factor for X2. Integer. Range -7 ... +7 - parameter coeff_y0 = -2.96438150626551080000, // Coefficient for Y0. Float. Range -3.999(9) ... 3.999(9) - parameter coeff_y1 = 2.92939452735121100000, // Coefficient for Y1. Float. Range -3.999(9) ... 3.999(9) - parameter coeff_y2 = -0.96500747158831091000 // Coefficient for Y2. Float. Range -3.999(9) ... 3.999(9) -) -( - input clk, - input reset, - - input ce, // must be double of calculated rate for stereo! - input sample_ce, // desired output sample rate - - input [39:0] cx, - input [7:0] cx0, - input [7:0] cx1, - input [7:0] cx2, - input [23:0] cy0, - input [23:0] cy1, - input [23:0] cy2, - - input [15:0] input_l, input_r, // signed samples - output [15:0] output_l, output_r // signed samples -); - -localparam [39:0] pcoeff_x = coeff_x * 40'h8000000000; -localparam [31:0] pcoeff_y0 = coeff_y0 * 24'h200000; -localparam [31:0] pcoeff_y1 = coeff_y1 * 24'h200000; -localparam [31:0] pcoeff_y2 = coeff_y2 * 24'h200000; - -wire [39:0] vcoeff = use_params ? pcoeff_x : cx; -wire [23:0] vcoeff_y0 = use_params ? pcoeff_y0[23:0] : cy0; -wire [23:0] vcoeff_y1 = use_params ? pcoeff_y1[23:0] : cy1; -wire [23:0] vcoeff_y2 = use_params ? pcoeff_y2[23:0] : cy2; - -wire [59:0] inp_mul = $signed(inp) * $signed(vcoeff); - -wire [39:0] x = inp_mul[59:20]; -wire [39:0] y = x + tap0; - -wire [39:0] tap0; -iir_filter_tap iir_tap_0 -( - .clk(clk), - .reset(reset), - .ce(ce), - .ch(ch), - .cx(use_params ? coeff_x0[7:0] : cx0), - .cy(vcoeff_y0), - .x(x), - .y(y), - .z(tap1), - .tap(tap0) -); - -wire [39:0] tap1; -iir_filter_tap iir_tap_1 -( - .clk(clk), - .reset(reset), - .ce(ce), - .ch(ch), - .cx(use_params ? coeff_x1[7:0] : cx1), - .cy(vcoeff_y1), - .x(x), - .y(y), - .z(tap2), - .tap(tap1) -); - -wire [39:0] tap2; -iir_filter_tap iir_tap_2 -( - .clk(clk), - .reset(reset), - .ce(ce), - .ch(ch), - .cx(use_params ? coeff_x2[7:0] : cx2), - .cy(vcoeff_y2), - .x(x), - .y(y), - .z(0), - .tap(tap2) -); - -wire [15:0] y_clamp = (~y[39] & |y[38:35]) ? 16'h7FFF : (y[39] & ~&y[38:35]) ? 16'h8000 : y[35:20]; - -reg ch = 0; -reg [15:0] out_l, out_r, out_m; -reg [15:0] inp, inp_m; -always @(posedge clk) if (ce) begin - if(!stereo) begin - ch <= 0; - inp <= input_l; - out_l <= y_clamp; - out_r <= y_clamp; - end - else begin - ch <= ~ch; - if(ch) begin - out_m <= y_clamp; - inp <= inp_m; - end - else begin - out_l <= out_m; - out_r <= y_clamp; - inp <= input_l; - inp_m <= input_r; - end - end -end - -reg [31:0] out; -always @(posedge clk) if (sample_ce) out <= {out_l, out_r}; - -assign {output_l, output_r} = out; - -endmodule - -module iir_filter_tap -( - input clk, - input reset, - - input ce, - input ch, - - input [7:0] cx, - input [23:0] cy, - - input [39:0] x, - input [39:0] y, - input [39:0] z, - output [39:0] tap -); - -wire signed [60:0] y_mul = $signed(y[36:0]) * $signed(cy); - -function [39:0] x_mul; - input [39:0] x; -begin - x_mul = 0; - if(cx[0]) x_mul = x_mul + {{4{x[39]}}, x[39:4]}; - if(cx[1]) x_mul = x_mul + {{3{x[39]}}, x[39:3]}; - if(cx[2]) x_mul = x_mul + {{2{x[39]}}, x[39:2]}; - if(cx[7]) x_mul = ~x_mul; //cheap NEG -end -endfunction - -(* ramstyle = "logic" *) reg [39:0] intreg[2]; -always @(posedge clk, posedge reset) begin - if(reset) {intreg[0],intreg[1]} <= 80'd0; - else if(ce) intreg[ch] <= x_mul(x) - y_mul[60:21] + z; -end - -assign tap = intreg[ch]; - -endmodule - -// simplified IIR 1-tap. -module DC_blocker -( - input clk, - input ce, // 48/96 KHz - input mute, - - input sample_rate, - input [15:0] din, - output [15:0] dout -); - -wire [39:0] x = {din[15], din, 23'd0}; -wire [39:0] x0 = x - (sample_rate ? {{11{x[39]}}, x[39:11]} : {{10{x[39]}}, x[39:10]}); -wire [39:0] y1 = y - (sample_rate ? {{10{y[39]}}, y[39:10]} : {{09{y[39]}}, y[39:09]}); -wire [39:0] y0 = x0 - x1 + y1; - -reg [39:0] x1, y; -always @(posedge clk) if(ce) begin - x1 <= x0; - y <= ^y0[39:38] ? {{2{y0[39]}},{38{y0[38]}}} : y0; -end - -assign dout = mute ? 16'd0 : y[38:23]; - -endmodule + +// 3-tap IIR filter for 2 channels. +// Copyright (C) 2020 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +// +// Can be converted to 2-tap (coeff_x2 = 0, coeff_y2 = 0) or 1-tap (coeff_x1,2 = 0, coeff_y1,2 = 0) +// +module IIR_filter +#( + parameter use_params = 1, // set to 1 to use following parameters, 0 for input port variables. + parameter stereo = 1, // 0 for mono (input_l) + + parameter coeff_x = 0.00000774701983513660, // Base gain value for X. Float. Range: 0.0 ... 0.999(9) + parameter coeff_x0 = 3, // Gain scale factor for X0. Integer. Range -7 ... +7 + parameter coeff_x1 = 3, // Gain scale factor for X1. Integer. Range -7 ... +7 + parameter coeff_x2 = 1, // Gain scale factor for X2. Integer. Range -7 ... +7 + parameter coeff_y0 = -2.96438150626551080000, // Coefficient for Y0. Float. Range -3.999(9) ... 3.999(9) + parameter coeff_y1 = 2.92939452735121100000, // Coefficient for Y1. Float. Range -3.999(9) ... 3.999(9) + parameter coeff_y2 = -0.96500747158831091000 // Coefficient for Y2. Float. Range -3.999(9) ... 3.999(9) +) +( + input clk, + input reset, + + input ce, // must be double of calculated rate for stereo! + input sample_ce, // desired output sample rate + + input [39:0] cx, + input [7:0] cx0, + input [7:0] cx1, + input [7:0] cx2, + input [23:0] cy0, + input [23:0] cy1, + input [23:0] cy2, + + input [15:0] input_l, input_r, // signed samples + output [15:0] output_l, output_r // signed samples +); + +localparam [39:0] pcoeff_x = coeff_x * 40'h8000000000; +localparam [31:0] pcoeff_y0 = coeff_y0 * 24'h200000; +localparam [31:0] pcoeff_y1 = coeff_y1 * 24'h200000; +localparam [31:0] pcoeff_y2 = coeff_y2 * 24'h200000; + +wire [39:0] vcoeff = use_params ? pcoeff_x : cx; +wire [23:0] vcoeff_y0 = use_params ? pcoeff_y0[23:0] : cy0; +wire [23:0] vcoeff_y1 = use_params ? pcoeff_y1[23:0] : cy1; +wire [23:0] vcoeff_y2 = use_params ? pcoeff_y2[23:0] : cy2; + +wire [59:0] inp_mul = $signed(inp) * $signed(vcoeff); + +wire [39:0] x = inp_mul[59:20]; +wire [39:0] y = x + tap0; + +wire [39:0] tap0; +iir_filter_tap iir_tap_0 +( + .clk(clk), + .reset(reset), + .ce(ce), + .ch(ch), + .cx(use_params ? coeff_x0[7:0] : cx0), + .cy(vcoeff_y0), + .x(x), + .y(y), + .z(tap1), + .tap(tap0) +); + +wire [39:0] tap1; +iir_filter_tap iir_tap_1 +( + .clk(clk), + .reset(reset), + .ce(ce), + .ch(ch), + .cx(use_params ? coeff_x1[7:0] : cx1), + .cy(vcoeff_y1), + .x(x), + .y(y), + .z(tap2), + .tap(tap1) +); + +wire [39:0] tap2; +iir_filter_tap iir_tap_2 +( + .clk(clk), + .reset(reset), + .ce(ce), + .ch(ch), + .cx(use_params ? coeff_x2[7:0] : cx2), + .cy(vcoeff_y2), + .x(x), + .y(y), + .z(0), + .tap(tap2) +); + +wire [15:0] y_clamp = (~y[39] & |y[38:35]) ? 16'h7FFF : (y[39] & ~&y[38:35]) ? 16'h8000 : y[35:20]; + +reg ch = 0; +reg [15:0] out_l, out_r, out_m; +reg [15:0] inp, inp_m; +always @(posedge clk) if (ce) begin + if(!stereo) begin + ch <= 0; + inp <= input_l; + out_l <= y_clamp; + out_r <= y_clamp; + end + else begin + ch <= ~ch; + if(ch) begin + out_m <= y_clamp; + inp <= inp_m; + end + else begin + out_l <= out_m; + out_r <= y_clamp; + inp <= input_l; + inp_m <= input_r; + end + end +end + +reg [31:0] out; +always @(posedge clk) if (sample_ce) out <= {out_l, out_r}; + +assign {output_l, output_r} = out; + +endmodule + +module iir_filter_tap +( + input clk, + input reset, + + input ce, + input ch, + + input [7:0] cx, + input [23:0] cy, + + input [39:0] x, + input [39:0] y, + input [39:0] z, + output [39:0] tap +); + +wire signed [60:0] y_mul = $signed(y[36:0]) * $signed(cy); + +function [39:0] x_mul; + input [39:0] x; +begin + x_mul = 0; + if(cx[0]) x_mul = x_mul + {{4{x[39]}}, x[39:4]}; + if(cx[1]) x_mul = x_mul + {{3{x[39]}}, x[39:3]}; + if(cx[2]) x_mul = x_mul + {{2{x[39]}}, x[39:2]}; + if(cx[7]) x_mul = ~x_mul; //cheap NEG +end +endfunction + +(* ramstyle = "logic" *) reg [39:0] intreg[2]; +always @(posedge clk, posedge reset) begin + if(reset) {intreg[0],intreg[1]} <= 80'd0; + else if(ce) intreg[ch] <= x_mul(x) - y_mul[60:21] + z; +end + +assign tap = intreg[ch]; + +endmodule + +// simplified IIR 1-tap. +module DC_blocker +( + input clk, + input ce, // 48/96 KHz + input mute, + + input sample_rate, + input [15:0] din, + output [15:0] dout +); + +wire [39:0] x = {din[15], din, 23'd0}; +wire [39:0] x0 = x - (sample_rate ? {{11{x[39]}}, x[39:11]} : {{10{x[39]}}, x[39:10]}); +wire [39:0] y1 = y - (sample_rate ? {{10{y[39]}}, y[39:10]} : {{09{y[39]}}, y[39:09]}); +wire [39:0] y0 = x0 - x1 + y1; + +reg [39:0] x1, y; +always @(posedge clk) if(ce) begin + x1 <= x0; + y <= ^y0[39:38] ? {{2{y0[39]}},{38{y0[38]}}} : y0; +end + +assign dout = mute ? 16'd0 : y[38:23]; + +endmodule diff --git a/sys/ltc2308.sv b/sys/ltc2308.sv index 33134fd..4d3ccc1 100644 --- a/sys/ltc2308.sv +++ b/sys/ltc2308.sv @@ -102,19 +102,19 @@ end endmodule -module ltc2308_tape #(parameter HIST_LOW = 16, HIST_HIGH = 64, ADC_RATE = 48000, CLK_RATE = 50000000) +module ltc2308_tape #(parameter HIST_LOW = 16, HIST_HIGH = 64, ADC_RATE = 48000, CLK_RATE = 50000000, NUM_CH = 1) ( - input reset, - input clk, + input reset, + input clk, - inout [3:0] ADC_BUS, - output reg dout, - output active + inout [3:0] ADC_BUS, + output reg dout, + output active, + output adc_sync, + output [(NUM_CH*12)-1:0] adc_data ); -wire [11:0] adc_data; -wire adc_sync; -ltc2308 #(1, ADC_RATE, CLK_RATE) adc +ltc2308 #(NUM_CH, ADC_RATE, CLK_RATE) adc ( .reset(reset), .clk(clk), @@ -133,8 +133,8 @@ always @(posedge clk) begin data1 <= data2; data2 <= data3; data3 <= data4; - data4 <= adc_data; - + data4 <= adc_data[11:0]; + sum <= data1+data2+data3+data4; if(sum[13:2]CLK_RATE) begin onesec <= 0; diff --git a/sys/math.sv b/sys/math.sv new file mode 100644 index 0000000..e7c0144 --- /dev/null +++ b/sys/math.sv @@ -0,0 +1,109 @@ + +// result = num/div +module sys_udiv +#( + parameter NB_NUM, + parameter NB_DIV +) +( + input clk, + input start, + output busy, + + input [NB_NUM-1:0] num, + input [NB_DIV-1:0] div, + output reg [NB_NUM-1:0] result, + output reg [NB_DIV-1:0] remainder +); + +reg run; +assign busy = run; + +always @(posedge clk) begin + reg [5:0] cpt; + reg [NB_NUM+NB_DIV+1:0] rem; + + if (start) begin + cpt <= 0; + run <= 1; + rem <= num; + end + else if (run) begin + cpt <= cpt + 1'd1; + run <= (cpt != NB_NUM + 1'd1); + remainder <= rem[NB_NUM+NB_DIV:NB_NUM+1]; + if (!rem[NB_DIV + NB_NUM + 1'd1]) + rem <= {rem[NB_DIV+NB_NUM:0] - (div << NB_NUM),1'b0}; + else + rem <= {rem[NB_DIV+NB_NUM:0] + (div << NB_NUM),1'b0}; + result <= {result[NB_NUM-2:0], !rem[NB_DIV + NB_NUM + 1'd1]}; + end +end + +endmodule + +// result = mul1*mul2 +module sys_umul +#( + parameter NB_MUL1, + parameter NB_MUL2 +) +( + input clk, + input start, + output busy, + + input [NB_MUL1-1:0] mul1, + input [NB_MUL2-1:0] mul2, + output reg [NB_MUL1+NB_MUL2-1:0] result +); + +reg run; +assign busy = run; + +always @(posedge clk) begin + reg [NB_MUL1+NB_MUL2-1:0] add; + reg [NB_MUL2-1:0] map; + + if (start) begin + run <= 1; + result <= 0; + add <= mul1; + map <= mul2; + end + else if (run) begin + if(!map) run <= 0; + if(map[0]) result <= result + add; + add <= add << 1; + map <= map >> 1; + end +end + +endmodule + +// result = (mul1*mul2)/div +module sys_umuldiv +#( + parameter NB_MUL1, + parameter NB_MUL2, + parameter NB_DIV +) +( + input clk, + input start, + output busy, + + input [NB_MUL1-1:0] mul1, + input [NB_MUL2-1:0] mul2, + input [NB_DIV-1:0] div, + output [NB_MUL1+NB_MUL2-1:0] result, + output [NB_DIV-1:0] remainder +); + +wire mul_run; +wire [NB_MUL1+NB_MUL2-1:0] mul_res; +sys_umul #(NB_MUL1,NB_MUL2) umul(clk,start,mul_run,mul1,mul2,mul_res); + +sys_udiv #(NB_MUL1+NB_MUL2,NB_DIV) udiv(clk,start|mul_run,busy,mul_res,div,result,remainder); + +endmodule diff --git a/sys/mcp23009.sv b/sys/mcp23009.sv index 40cbf5e..82eaf37 100644 --- a/sys/mcp23009.sv +++ b/sys/mcp23009.sv @@ -8,10 +8,12 @@ module mcp23009 output reg [2:0] btn, input [2:0] led, - output reg sd_cd, + output reg flg_sd_cd, + output reg flg_present, + output reg flg_mode, - output scl, - inout sda + output scl, + inout sda ); @@ -50,7 +52,9 @@ always@(posedge clk) begin idx <= 0; btn <= 0; rw <= 0; - sd_cd <= 1; + flg_sd_cd <= 1; + flg_present <= 0; + flg_mode <= 1; end else begin if(~&init_data[idx]) begin @@ -84,7 +88,10 @@ always@(posedge clk) begin state <= 0; rw <= 0; if(!error) begin - if(rw) {sd_cd, btn} <= {dout[7], dout[5:3]}; + if(rw) begin + {flg_sd_cd, flg_mode, btn} <= {dout[7:3]}; + flg_present <= 1; + end rw <= ~rw; end end diff --git a/sys/mt32pi.sv b/sys/mt32pi.sv new file mode 100644 index 0000000..6704807 --- /dev/null +++ b/sys/mt32pi.sv @@ -0,0 +1,283 @@ +// +// Communication module to MT32-pi (external MIDI emulator on RPi) +// (C) 2020 Sorgelig, Kitrinx +// +// https://github.com/dwhinham/mt32-pi +// + +module mt32pi +( + input CLK_AUDIO, + + input CLK_VIDEO, + input CE_PIXEL, + input VGA_VS, + input VGA_DE, + + input [6:0] USER_IN, + output [6:0] USER_OUT, + + input reset, + input midi_tx, + output midi_rx, + + output reg [15:0] mt32_i2s_r, + output reg [15:0] mt32_i2s_l, + + output reg mt32_available, + + input mt32_mode_req, + input [1:0] mt32_rom_req, + input [7:0] mt32_sf_req, + + output reg [7:0] mt32_mode, + output reg [7:0] mt32_rom, + output reg [7:0] mt32_sf, + output reg mt32_newmode, + + output reg mt32_lcd_en, + output reg mt32_lcd_pix, + output reg mt32_lcd_update +); + +// +// Pin | USB Name | Signal +// ----+----------+-------------- +// 0 | D+ | I/O I2C_SDA / RX (midi in) +// 1 | D- | O TX (midi out) +// 2 | TX- | I I2S_WS (1 == right) +// 3 | GND_d | I I2C_SCL +// 4 | RX+ | I I2S_BCLK +// 5 | RX- | I I2S_DAT +// 6 | TX+ | - none +// + +assign USER_OUT[0] = sda_out; +assign USER_OUT[1] = midi_tx; +assign USER_OUT[6:2] = '1; + + +// +// crossed/straight cable selection +// + +generate + genvar i; + for(i = 0; i<2; i++) begin : clk_rate + wire clk_in = i ? USER_IN[6] : USER_IN[4]; + reg [4:0] cnt; + always @(posedge CLK_AUDIO) begin : clkr + reg clk_sr, clk, old_clk; + reg [4:0] cnt_tmp; + + clk_sr <= clk_in; + if (clk_sr == clk_in) clk <= clk_sr; + + if(~&cnt_tmp) cnt_tmp <= cnt_tmp + 1'd1; + else cnt <= '1; + + old_clk <= clk; + if(~old_clk & clk) begin + cnt <= cnt_tmp; + cnt_tmp <= 0; + end + end + end + + reg crossed; + always @(posedge CLK_AUDIO) crossed <= (clk_rate[0].cnt <= clk_rate[1].cnt); +endgenerate + +wire i2s_ws = crossed ? USER_IN[2] : USER_IN[5]; +wire i2s_data = crossed ? USER_IN[5] : USER_IN[2]; +wire i2s_bclk = crossed ? USER_IN[4] : USER_IN[6]; +assign midi_rx = ~mt32_available ? USER_IN[0] : crossed ? USER_IN[6] : USER_IN[4]; + + +// +// i2s receiver +// + +always @(posedge CLK_AUDIO) begin : i2s_proc + reg [15:0] i2s_buf = 0; + reg [4:0] i2s_cnt = 0; + reg clk_sr; + reg i2s_clk = 0; + reg old_clk, old_ws; + reg i2s_next = 0; + + // Debounce clock + clk_sr <= i2s_bclk; + if (clk_sr == i2s_bclk) i2s_clk <= clk_sr; + + // Latch data and ws on rising edge + old_clk <= i2s_clk; + if (i2s_clk && ~old_clk) begin + + if (~i2s_cnt[4]) begin + i2s_cnt <= i2s_cnt + 1'd1; + i2s_buf[~i2s_cnt[3:0]] <= i2s_data; + end + + // Word Select will change 1 clock before the new word starts + old_ws <= i2s_ws; + if (old_ws != i2s_ws) i2s_next <= 1; + end + + if (i2s_next) begin + i2s_next <= 0; + i2s_cnt <= 0; + i2s_buf <= 0; + + if (i2s_ws) mt32_i2s_l <= i2s_buf; + else mt32_i2s_r <= i2s_buf; + end + + if (reset) begin + i2s_buf <= 0; + mt32_i2s_l <= 0; + mt32_i2s_r <= 0; + end +end + + +// +// i2c slave +// + +reg sda_out; +reg [7:0] lcd_data[1024]; +reg lcd_sz; + +reg reset_r = 0; +wire [7:0] mode_req = reset_r ? 8'hA0 : mt32_mode_req ? 8'hA2 : 8'hA1; +wire [7:0] rom_req = {6'd0, mt32_rom_req}; + +always @(posedge CLK_AUDIO) begin : i2c_slave + reg sda_sr, scl_sr; + reg old_sda, old_scl; + reg sda, scl; + reg [7:0] tmp; + reg [3:0] cnt = 0; + reg [10:0] bcnt = 0; + reg ack; + reg i2c_rw; + reg disp, dispdata; + reg [2:0] div; + reg old_reset; + + old_reset <= reset; + if(old_reset & ~reset) sda_out <= 1; + + div <= div + 1'd1; + if(!div) begin + sda_sr <= USER_IN[0]; + if(sda_sr == USER_IN[0]) sda <= sda_sr; + old_sda <= sda; + + scl_sr <= USER_IN[3]; + if(scl_sr == USER_IN[3]) scl <= scl_sr; + old_scl <= scl; + + //start + if(old_scl & scl & old_sda & ~sda) begin + cnt <= 9; + bcnt <= 0; + ack <= 0; + i2c_rw <= 0; + disp <= 0; + dispdata <= 0; + end + + //stop + if(old_scl & scl & ~old_sda & sda) begin + cnt <= 0; + if(dispdata) begin + lcd_sz <= ~bcnt[9]; + mt32_lcd_update <= ~mt32_lcd_update; + end + end + + //data latch + if(~old_scl && scl && cnt) begin + tmp <= {tmp[6:0], sda}; + cnt <= cnt - 1'd1; + end + + if(!cnt) sda_out <= 1; + + //data set + if(old_scl && ~scl) begin + sda_out <= 1; + if(cnt == 1) begin + if(!bcnt) begin + if(tmp[7:1] == 'h45 || tmp[7:1] == 'h3c) begin + disp <= (tmp[7:1] == 'h3c); + sda_out <= 0; + mt32_available <= 1; + ack <= 1; + i2c_rw <= tmp[0]; + bcnt <= bcnt + 1'd1; + cnt <= 10; + end + else begin + // wrong address, stop + cnt <= 0; + end + end + else if(ack) begin + if(~i2c_rw) begin + if(disp) begin + if(bcnt == 1) dispdata <= (tmp[7:6] == 2'b01); + else if(dispdata) lcd_data[bcnt[9:0] - 2'd2] <= tmp; + end + else begin + if(bcnt == 1) mt32_mode <= tmp; + if(bcnt == 2) mt32_rom <= tmp; + if(bcnt == 3) mt32_sf <= tmp; + if(bcnt == 3) mt32_newmode <= ~mt32_newmode; + end + end + if(~&bcnt) bcnt <= bcnt + 1'd1; + sda_out <= 0; + cnt <= 10; + end + end + else if(i2c_rw && ack && cnt && ~disp) begin + if(bcnt == 1) sda_out <= mode_req[cnt[2:0] - 2'd2]; + if(bcnt == 2) sda_out <= rom_req[cnt[2:0] - 2'd2]; + if(bcnt == 3) sda_out <= mt32_sf_req[cnt[2:0] - 2'd2]; + if(bcnt == 3) reset_r <= 0; + end + end + end + + if(reset) begin + reset_r <= 1; + mt32_available <= 0; + end +end + +always @(posedge CLK_VIDEO) begin + reg old_de, old_vs; + reg [7:0] hcnt; + reg [6:0] vcnt; + reg [7:0] sh; + + if(CE_PIXEL) begin + old_de <= VGA_DE; + old_vs <= VGA_VS; + + if(~&hcnt) hcnt <= hcnt + 1'd1; + sh <= (sh << 1) | (~old_de & VGA_DE); + if(sh[7]) hcnt <= 0; + + if(old_de & ~VGA_DE & ~&vcnt) vcnt <= vcnt + 1'd1; + if(~old_vs & VGA_VS) vcnt <= 0; + + mt32_lcd_en <= mt32_available & ~hcnt[7] && (lcd_sz ? !vcnt[6] : !vcnt[6:5]); + mt32_lcd_pix <= lcd_data[{vcnt[5:3],hcnt[6:0]}][vcnt[2:0]]; + end +end + +endmodule diff --git a/sys/osd.v b/sys/osd.v index a4fbdde..c354f6f 100644 --- a/sys/osd.v +++ b/sys/osd.v @@ -72,7 +72,7 @@ always@(posedge clk_sys) begin // command 0x40: OSDCMDENABLE, OSDCMDDISABLE if(io_din[7:4] == 4) begin if(!io_din[0]) {osd_status,highres} <= 0; - else {osd_status,info} <= {~io_din[2],io_din[2]}; + else {osd_status,info} <= {~io_din[2] & ~io_din[3],io_din[2]}; bcnt <= 0; end // command 0x20: OSDCMDWRITE @@ -131,7 +131,7 @@ wire [21:0] osd_h_hdr = (info || rot) ? osd_h : (osd_h + OSD_HDR); // pipeline the comparisons a bit always @(posedge clk_video) if(ce_pix) begin - v_cnt_h <= v_cnt < osd_t; + v_cnt_h <= v_cnt <= osd_t; v_cnt_1 <= v_cnt < 320; v_cnt_2 <= v_cnt < 640; v_cnt_3 <= v_cnt < 960; diff --git a/sys/pll_audio.v b/sys/pll_audio.v index e96b248..185a94c 100644 --- a/sys/pll_audio.v +++ b/sys/pll_audio.v @@ -1,252 +1,252 @@ -// megafunction wizard: %Altera PLL v17.0% -// GENERATION: XML -// pll_audio.v - -// Generated using ACDS version 17.0 602 - -`timescale 1 ps / 1 ps -module pll_audio ( - input wire refclk, // refclk.clk - input wire rst, // reset.reset - output wire outclk_0 // outclk0.clk - ); - - pll_audio_0002 pll_audio_inst ( - .refclk (refclk), // refclk.clk - .rst (rst), // reset.reset - .outclk_0 (outclk_0), // outclk0.clk - .locked () // (terminated) - ); - -endmodule -// Retrieval info: -// -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// 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@@ -`timescale 1ns/10ps -module pll_audio_0002( - - // interface 'refclk' - input wire refclk, - - // interface 'reset' - input wire rst, - - // interface 'outclk0' - output wire outclk_0, - - // interface 'locked' - output wire locked -); - - altera_pll #( - .fractional_vco_multiplier("true"), - .reference_clock_frequency("50.0 MHz"), - .operation_mode("direct"), - .number_of_clocks(1), - .output_clock_frequency0("24.576000 MHz"), - .phase_shift0("0 ps"), - .duty_cycle0(50), - .output_clock_frequency1("0 MHz"), - .phase_shift1("0 ps"), - .duty_cycle1(50), - .output_clock_frequency2("0 MHz"), - .phase_shift2("0 ps"), - .duty_cycle2(50), - .output_clock_frequency3("0 MHz"), - .phase_shift3("0 ps"), - .duty_cycle3(50), - .output_clock_frequency4("0 MHz"), - .phase_shift4("0 ps"), - .duty_cycle4(50), - .output_clock_frequency5("0 MHz"), - .phase_shift5("0 ps"), - .duty_cycle5(50), - .output_clock_frequency6("0 MHz"), - .phase_shift6("0 ps"), - .duty_cycle6(50), - .output_clock_frequency7("0 MHz"), - .phase_shift7("0 ps"), - .duty_cycle7(50), - .output_clock_frequency8("0 MHz"), - .phase_shift8("0 ps"), - .duty_cycle8(50), - .output_clock_frequency9("0 MHz"), - .phase_shift9("0 ps"), - .duty_cycle9(50), - .output_clock_frequency10("0 MHz"), - .phase_shift10("0 ps"), - .duty_cycle10(50), - .output_clock_frequency11("0 MHz"), - .phase_shift11("0 ps"), - .duty_cycle11(50), - .output_clock_frequency12("0 MHz"), - .phase_shift12("0 ps"), - .duty_cycle12(50), - .output_clock_frequency13("0 MHz"), - .phase_shift13("0 ps"), - .duty_cycle13(50), - .output_clock_frequency14("0 MHz"), - .phase_shift14("0 ps"), - .duty_cycle14(50), - .output_clock_frequency15("0 MHz"), - .phase_shift15("0 ps"), - .duty_cycle15(50), - .output_clock_frequency16("0 MHz"), - .phase_shift16("0 ps"), - .duty_cycle16(50), - .output_clock_frequency17("0 MHz"), - .phase_shift17("0 ps"), - .duty_cycle17(50), - .pll_type("General"), - .pll_subtype("General") - ) altera_pll_i ( - .rst (rst), - .outclk ({outclk_0}), - .locked (locked), - .fboutclk ( ), - .fbclk (1'b0), - .refclk (refclk) - ); -endmodule - +`timescale 1ns/10ps +module pll_audio_0002( + + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'locked' + output wire locked +); + + altera_pll #( + .fractional_vco_multiplier("true"), + .reference_clock_frequency("50.0 MHz"), + .operation_mode("direct"), + .number_of_clocks(1), + .output_clock_frequency0("24.576000 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("0 MHz"), + .phase_shift1("0 ps"), + .duty_cycle1(50), + .output_clock_frequency2("0 MHz"), + .phase_shift2("0 ps"), + .duty_cycle2(50), + .output_clock_frequency3("0 MHz"), + .phase_shift3("0 ps"), + .duty_cycle3(50), + .output_clock_frequency4("0 MHz"), + .phase_shift4("0 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("General"), + .pll_subtype("General") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_0}), + .locked (locked), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk) + ); +endmodule + diff --git a/sys/pll_cfg.qip b/sys/pll_cfg.qip index c3394be..0b560f9 100644 --- a/sys/pll_cfg.qip +++ b/sys/pll_cfg.qip @@ -1,44 +1,5 @@ -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_VERSION "17.0" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_ENV "mwpim" -set_global_assignment -library "pll_cfg" -name MISC_FILE [file join $::quartus(qip_path) "pll_cfg.cmp"] -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_QSYS_MODE "UNKNOWN" set_global_assignment -name SYNTHESIS_ONLY_QIP ON -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_NAME "cGxsX2hkbWlfY2Zn" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw==" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA==" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ==" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA==" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA==" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA==" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA==" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo" -set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A=" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc=" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA==" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw==" - -set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg.v"] +set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg.v"] +set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg_hdmi.v"] set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_top.v"] set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_core.v"] - -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_VERSION "17.0" -set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_ENV "mwpim" diff --git a/sys/pll_cfg/altera_pll_reconfig_core.v b/sys/pll_cfg/altera_pll_reconfig_core.v index d06a746..a9e2b8c 100644 --- a/sys/pll_cfg/altera_pll_reconfig_core.v +++ b/sys/pll_cfg/altera_pll_reconfig_core.v @@ -11,2174 +11,2174 @@ // agreement for further details. -`timescale 1ps/1ps - -module altera_pll_reconfig_core -#( - parameter reconf_width = 64, - parameter device_family = "Stratix V", - // MIF Streaming parameters - parameter RECONFIG_ADDR_WIDTH = 6, - parameter RECONFIG_DATA_WIDTH = 32, - parameter ROM_ADDR_WIDTH = 9, - parameter ROM_DATA_WIDTH = 32, - parameter ROM_NUM_WORDS = 512 -) ( - - //input - input wire mgmt_clk, - input wire mgmt_reset, - - - //conduits - output wire [reconf_width-1:0] reconfig_to_pll, - input wire [reconf_width-1:0] reconfig_from_pll, - - // user data (avalon-MM slave interface) - output wire [31:0] mgmt_readdata, - output wire mgmt_waitrequest, - input wire [5:0] mgmt_address, - input wire mgmt_read, - input wire mgmt_write, - input wire [31:0] mgmt_writedata, - - //other - output wire mif_start_out, - output reg [ROM_ADDR_WIDTH-1:0] mif_base_addr -); - localparam mode_WR = 1'b0; - localparam mode_POLL = 1'b1; - localparam MODE_REG = 6'b000000; - localparam STATUS_REG = 6'b000001; - localparam START_REG = 6'b000010; - localparam N_REG = 6'b000011; - localparam M_REG = 6'b000100; - localparam C_COUNTERS_REG = 6'b000101; - localparam DPS_REG = 6'b000110; - localparam DSM_REG = 6'b000111; - localparam BWCTRL_REG = 6'b001000; - localparam CP_CURRENT_REG = 6'b001001; - localparam ANY_DPRIO = 6'b100000; - localparam CNT_BASE = 5'b001010; - localparam VCO_REG = 6'b011100; - localparam MIF_REG = 6'b011111; - - //C Counters - localparam number_of_counters = 5'd18; - localparam CNT_0 = 1'd0, CNT_1 = 5'd1, CNT_2 = 5'd2, - CNT_3 = 5'd3, CNT_4 = 5'd4, CNT_5 = 5'd5, - CNT_6 = 5'd6, CNT_7 = 5'd7, CNT_8 = 5'd8, - CNT_9 = 5'd9, CNT_10 = 5'd10, CNT_11 = 5'd11, - CNT_12 = 5'd12, CNT_13 = 5'd13, CNT_14 = 5'd14, - CNT_15 = 5'd15, CNT_16 = 5'd16, CNT_17 = 5'd17; - //C counter addresses - localparam C_CNT_0_DIV_ADDR = 5'h00; - localparam C_CNT_0_DIV_ADDR_DPRIO_1 = 5'h11; - localparam C_CNT_0_3_BYPASS_EN_ADDR = 5'h15; - localparam C_CNT_0_3_ODD_DIV_EN_ADDR = 5'h17; - localparam C_CNT_4_17_BYPASS_EN_ADDR = 5'h14; - localparam C_CNT_4_17_ODD_DIV_EN_ADDR = 5'h16; - //N counter addresses - localparam N_CNT_DIV_ADDR = 5'h13; - localparam N_CNT_BYPASS_EN_ADDR = 5'h15; - localparam N_CNT_ODD_DIV_EN_ADDR = 5'h17; - //M counter addresses - localparam M_CNT_DIV_ADDR = 5'h12; - localparam M_CNT_BYPASS_EN_ADDR = 5'h15; - localparam M_CNT_ODD_DIV_EN_ADDR = 5'h17; - - //DSM address - localparam DSM_K_FRACTIONAL_DIVISION_ADDR_0 = 5'h18; - localparam DSM_K_FRACTIONAL_DIVISION_ADDR_1 = 5'h19; - localparam DSM_K_READY_ADDR = 5'h17; - localparam DSM_K_DITHER_ADDR = 5'h17; - localparam DSM_OUT_SEL_ADDR = 6'h30; - - //Other DSM params - localparam DSM_K_READY_BIT_INDEX = 4'd11; - //BWCTRL address - //Bit 0-3 of addr - localparam BWCTRL_ADDR = 6'h30; - //CP_CURRENT address - //Bit 0-2 of addr - localparam CP_CURRENT_ADDR = 6'h31; - - // VCODIV address - localparam VCO_ADDR = 5'h17; - - localparam DPRIO_IDLE = 3'd0, ONE = 3'd1, TWO = 3'd2, THREE = 3'd3, FOUR = 3'd4, - FIVE = 3'd5, SIX = 3'd6, SEVEN = 3'd7, EIGHT = 4'd8, NINE = 4'd9, TEN = 4'd10, - ELEVEN = 4'd11, TWELVE = 4'd12, THIRTEEN = 4'd13, FOURTEEN = 4'd14, DPRIO_DONE = 4'd15; - localparam IDLE = 2'b00, WAIT_ON_LOCK = 2'b01, LOCKED = 2'b10; - - wire clk; - wire reset; - wire gnd; - - wire [5: 0] slave_address; - wire slave_read; - wire slave_write; - wire [31: 0] slave_writedata; - - reg [31: 0] slave_readdata_d; - reg [31: 0] slave_readdata_q; - wire slave_waitrequest; - reg slave_mode; - - assign clk = mgmt_clk; - - assign slave_address = mgmt_address; - assign slave_read = mgmt_read; - assign slave_write = mgmt_write; - assign slave_writedata = mgmt_writedata; - - reg read_waitrequest; - // Outputs - assign mgmt_readdata = slave_readdata_q; - assign mgmt_waitrequest = slave_waitrequest | read_waitrequest; //Read waitrequest asserted in polling mode - - //internal signals - wire locked_orig; - wire locked; - - wire pll_start; - wire pll_start_valid; - reg status_read; - wire read_slave_mode_asserted; - - wire pll_start_asserted; - - reg [1:0] current_state; - reg [1:0] next_state; - - reg status;//0=busy, 1=ready - //user_mode_init user_mode_init_inst (clk, reset, dprio_mdio_dis, ser_shift_load); - //declaring the init wires. These will have 0 on them for 64 clk cycles - wire [ 5:0] init_dprio_address; - wire init_dprio_read; - wire [ 1:0] init_dprio_byteen; - wire init_dprio_write; - wire [15:0] init_dprio_writedata; - - wire init_atpgmode; - wire init_mdio_dis; - wire init_scanen; - wire init_ser_shift_load; - wire dprio_init_done; - - //DPRIO output signals after initialization is done - wire dprio_clk; - reg avmm_dprio_write; - reg avmm_dprio_read; - reg [5:0] avmm_dprio_address; - reg [15:0] avmm_dprio_writedata; - reg [1:0] avmm_dprio_byteen; - wire avmm_atpgmode; - wire avmm_mdio_dis; - wire avmm_scanen; - - //Final output wires that are muxed between the init and avmm wires. - wire dprio_init_reset; - wire [5:0] dprio_address /*synthesis keep*/; - wire dprio_read/*synthesis keep*/; - wire [1:0] dprio_byteen/*synthesis keep*/; - wire dprio_write/*synthesis keep*/; - wire [15:0] dprio_writedata/*synthesis keep*/; - wire dprio_mdio_dis/*synthesis keep*/; - wire dprio_ser_shift_load/*synthesis keep*/; - wire dprio_atpgmode/*synthesis keep*/; - wire dprio_scanen/*synthesis keep*/; - - - //other PLL signals for dyn ph shift - wire phase_done/*synthesis keep*/; - wire phase_en/*synthesis keep*/; - wire up_dn/*synthesis keep*/; - wire [4:0] cnt_sel; - - //DPRIO input signals - wire [15:0] dprio_readdata; - - //internal logic signals - //storage registers for user sent data - reg dprio_temp_read_1; - reg dprio_temp_read_2; - reg dprio_start; - reg mif_start_assert; - reg dps_start_assert; - wire usr_valid_changes; - reg [3:0] dprio_cur_state; - reg [3:0] dprio_next_state; - reg [15:0] dprio_temp_m_n_c_readdata_1_d; - reg [15:0] dprio_temp_m_n_c_readdata_2_d; - reg [15:0] dprio_temp_m_n_c_readdata_1_q; - reg [15:0] dprio_temp_m_n_c_readdata_2_q; - reg dprio_write_done; - //C counters signals - reg [7:0] usr_c_cnt_lo; - reg [7:0] usr_c_cnt_hi; - reg usr_c_cnt_bypass_en; - reg usr_c_cnt_odd_duty_div_en; - reg [7:0] temp_c_cnt_lo [0:17]; - reg [7:0] temp_c_cnt_hi [0:17]; - reg temp_c_cnt_bypass_en [0:17]; - reg temp_c_cnt_odd_duty_div_en [0:17]; - reg any_c_cnt_changed; - reg all_c_cnt_done_q; - reg all_c_cnt_done_d; - reg [17:0] c_cnt_changed; - reg [17:0] c_cnt_done_d; - reg [17:0] c_cnt_done_q; - //N counter signals - reg [7:0] usr_n_cnt_lo; - reg [7:0] usr_n_cnt_hi; - reg usr_n_cnt_bypass_en; - reg usr_n_cnt_odd_duty_div_en; - reg n_cnt_changed; - reg n_cnt_done_d; - reg n_cnt_done_q; - //M counter signals - reg [7:0] usr_m_cnt_lo; - reg [7:0] usr_m_cnt_hi; - reg usr_m_cnt_bypass_en; - reg usr_m_cnt_odd_duty_div_en; - reg m_cnt_changed; - reg m_cnt_done_d; - reg m_cnt_done_q; - //dyn phase regs - reg [15:0] usr_num_shifts; - reg [4:0] usr_cnt_sel /*synthesis preserve*/; - reg usr_up_dn; - reg dps_changed; - wire dps_changed_valid; - wire dps_done; - - //DSM Signals - reg [31:0] usr_k_value; - reg dsm_k_changed; - reg dsm_k_done_d; - reg dsm_k_done_q; - reg dsm_k_ready_false_done_d; - //BW signals - reg [3:0] usr_bwctrl_value; - reg bwctrl_changed; - reg bwctrl_done_d; - reg bwctrl_done_q; - //CP signals - reg [2:0] usr_cp_current_value; - reg cp_current_changed; - reg cp_current_done_d; - reg cp_current_done_q; - //VCO signals - reg usr_vco_value; - reg vco_changed; - reg vco_done_d; - reg vco_done_q; - //Manual DPRIO signals - reg manual_dprio_done_q; - reg manual_dprio_done_d; - reg manual_dprio_changed; - reg [5:0] usr_dprio_address; - reg [15:0] usr_dprio_writedata_0; - reg usr_r_w; - //keeping track of which operation happened last - reg [5:0] operation_address; - // Address wires for all C_counter DPRIO registers - // These are outputs of LUTS, changing depending - // on whether PLL_0 or PLL_1 being used - - - //Fitter will tell if FPLL1 is being used - wire fpll_1; - - // other - reg mif_reg_asserted; - // MAIN FSM - - // Synchronize locked signal - altera_std_synchronizer #( - .depth(3) - ) altera_std_synchronizer_inst ( - .clk(mgmt_clk), - .reset_n(~mgmt_reset), - .din(locked_orig), - .dout(locked) - ); - - always @(posedge clk) - begin - if (reset) - begin - dprio_cur_state <= DPRIO_IDLE; - current_state <= IDLE; - end - else - begin - current_state <= next_state; - dprio_cur_state <= dprio_next_state; - end - end - - always @(*) - begin - case(current_state) - IDLE: - begin - if (pll_start & !slave_waitrequest & usr_valid_changes) - next_state = WAIT_ON_LOCK; - else - next_state = IDLE; - end - WAIT_ON_LOCK: - begin - if (locked & dps_done & dprio_write_done) // received locked high from PLL - begin - if (slave_mode==mode_WR) //if the mode is waitrequest, then - // goto IDLE state directly - next_state = IDLE; - else - next_state = LOCKED; //otherwise go the locked state - end - else - next_state = WAIT_ON_LOCK; - end - - LOCKED: - begin - if (status_read) // stay in LOCKED until user reads status - next_state = IDLE; - else - next_state = LOCKED; - end - - default: next_state = 2'bxx; - - endcase - end - - - // ask the pll to start reconfig - assign pll_start = (pll_start_asserted & (current_state==IDLE)) ; - assign pll_start_valid = (pll_start & (next_state==WAIT_ON_LOCK)) ; - - - - // WRITE OPERATIONS - assign pll_start_asserted = slave_write & (slave_address == START_REG); - assign mif_start_out = pll_start & mif_reg_asserted; - - //reading the mode register to determine what mode the slave will operate - //in. - always @(posedge clk) - begin - if (reset) - slave_mode <= mode_WR; - else if (slave_write & (slave_address == MODE_REG) & !slave_waitrequest) - slave_mode <= slave_writedata[0]; - end - - //record which values user wants to change. - - //reading in the actual values that need to be reconfigged and sending - //them to the PLL - always @(posedge clk) - begin - if (reset) - begin - //reset all regs here - //BW signals reset - usr_bwctrl_value <= 0; - bwctrl_changed <= 0; - bwctrl_done_q <= 0; - //CP signals reset - usr_cp_current_value <= 0; - cp_current_changed <= 0; - cp_current_done_q <= 0; - //VCO signals reset - usr_vco_value <= 0; - vco_changed <= 0; - vco_done_q <= 0; - //DSM signals reset - usr_k_value <= 0; - dsm_k_changed <= 0; - dsm_k_done_q <= 0; - //N counter signals reset - usr_n_cnt_lo <= 0; - usr_n_cnt_hi <= 0; - usr_n_cnt_bypass_en <= 0; - usr_n_cnt_odd_duty_div_en <= 0; - n_cnt_changed <= 0; - n_cnt_done_q <= 0; - //M counter signals reset - usr_m_cnt_lo <= 0; - usr_m_cnt_hi <= 0; - usr_m_cnt_bypass_en <= 0; - usr_m_cnt_odd_duty_div_en <= 0; - m_cnt_changed <= 0; - m_cnt_done_q <= 0; - //C counter signals reset - usr_c_cnt_lo <= 0; - usr_c_cnt_hi <= 0; - usr_c_cnt_bypass_en <= 0; - usr_c_cnt_odd_duty_div_en <= 0; - any_c_cnt_changed <= 0; - all_c_cnt_done_q <= 0; - c_cnt_done_q <= 0; - //generic signals - dprio_start <= 0; - mif_start_assert <= 0; - dps_start_assert <= 0; - dprio_temp_m_n_c_readdata_1_q <= 0; - dprio_temp_m_n_c_readdata_2_q <= 0; - c_cnt_done_q <= 0; - //DPS signals - usr_up_dn <= 0; - usr_cnt_sel <= 0; - usr_num_shifts <= 0; - dps_changed <= 0; - //manual DPRIO signals - manual_dprio_changed <= 0; - usr_dprio_address <= 0; - usr_dprio_writedata_0 <= 0; - usr_r_w <= 0; - operation_address <= 0; - mif_reg_asserted <= 0; - mif_base_addr <= 0; - end - else - begin - if (dprio_temp_read_1) - begin - dprio_temp_m_n_c_readdata_1_q <= dprio_temp_m_n_c_readdata_1_d; - end - if (dprio_temp_read_2) - begin - dprio_temp_m_n_c_readdata_2_q <= dprio_temp_m_n_c_readdata_2_d; - end - if ((dps_done)) dps_changed <= 0; - if (dsm_k_done_d) dsm_k_done_q <= dsm_k_done_d; - if (n_cnt_done_d) n_cnt_done_q <= n_cnt_done_d; - if (m_cnt_done_d) m_cnt_done_q <= m_cnt_done_d; - if (all_c_cnt_done_d) all_c_cnt_done_q <= all_c_cnt_done_d; - if (c_cnt_done_d != 0) c_cnt_done_q <= c_cnt_done_q | c_cnt_done_d; - if (bwctrl_done_d) bwctrl_done_q <= bwctrl_done_d; - if (cp_current_done_d) cp_current_done_q <= cp_current_done_d; - if (vco_done_d) vco_done_q <= vco_done_d; - if (manual_dprio_done_d) manual_dprio_done_q <= manual_dprio_done_d; - - if (mif_start_out == 1'b1) - mif_start_assert <= 0; // Signaled MIF block to start, so deassert on next cycle - - if (dps_done != 1'b1) - dps_start_assert <= 0; // DPS has started, so dessert its start signal on next cycle - - if (dprio_next_state == ONE) - dprio_start <= 0; - if (dprio_write_done) - begin - bwctrl_done_q <= 0; - cp_current_done_q <= 0; - vco_done_q <= 0; - dsm_k_done_q <= 0; - dsm_k_done_q <= 0; - n_cnt_done_q <= 0; - m_cnt_done_q <= 0; - all_c_cnt_done_q <= 0; - c_cnt_done_q <= 0; - dsm_k_changed <= 0; - n_cnt_changed <= 0; - m_cnt_changed <= 0; - any_c_cnt_changed <= 0; - bwctrl_changed <= 0; - cp_current_changed <= 0; - vco_changed <= 0; - manual_dprio_changed <= 0; - manual_dprio_done_q <= 0; - if (dps_changed | dps_changed_valid | !dps_done ) - begin - usr_cnt_sel <= usr_cnt_sel; - end - else - begin - usr_cnt_sel <= 0; - end - mif_reg_asserted <= 0; - end - else - begin - dsm_k_changed <= dsm_k_changed; - n_cnt_changed <= n_cnt_changed; - m_cnt_changed <= m_cnt_changed; - any_c_cnt_changed <= any_c_cnt_changed; - manual_dprio_changed <= manual_dprio_changed; - mif_reg_asserted <= mif_reg_asserted; - usr_cnt_sel <= usr_cnt_sel; - end - - - if(slave_write & !slave_waitrequest) - begin - case(slave_address) - //read in the values here from the user and act on them - DSM_REG: - begin - operation_address <= DSM_REG; - usr_k_value <= slave_writedata[31:0]; - dsm_k_changed <= 1'b1; - dsm_k_done_q <= 0; - dprio_start <= 1'b1; - end - N_REG: - begin - operation_address <= N_REG; - usr_n_cnt_lo <= slave_writedata[7:0]; - usr_n_cnt_hi <= slave_writedata[15:8]; - usr_n_cnt_bypass_en <= slave_writedata[16]; - usr_n_cnt_odd_duty_div_en <= slave_writedata[17]; - n_cnt_changed <= 1'b1; - n_cnt_done_q <= 0; - dprio_start <= 1'b1; - end - M_REG: - begin - operation_address <= M_REG; - usr_m_cnt_lo <= slave_writedata[7:0]; - usr_m_cnt_hi <= slave_writedata[15:8]; - usr_m_cnt_bypass_en <= slave_writedata[16]; - usr_m_cnt_odd_duty_div_en <= slave_writedata[17]; - m_cnt_changed <= 1'b1; - m_cnt_done_q <= 0; - dprio_start <= 1'b1; - end - DPS_REG: - begin - operation_address <= DPS_REG; - usr_num_shifts <= slave_writedata[15:0]; - usr_cnt_sel <= slave_writedata[20:16]; - usr_up_dn <= slave_writedata[21]; - dps_changed <= 1; - dps_start_assert <= 1; - end - C_COUNTERS_REG: - begin - operation_address <= C_COUNTERS_REG; - usr_c_cnt_lo <= slave_writedata[7:0]; - usr_c_cnt_hi <= slave_writedata[15:8]; - usr_c_cnt_bypass_en <= slave_writedata[16]; - usr_c_cnt_odd_duty_div_en <= slave_writedata[17]; - usr_cnt_sel <= slave_writedata[22:18]; - any_c_cnt_changed <= 1'b1; - all_c_cnt_done_q <= 0; - dprio_start <= 1'b1; - end - BWCTRL_REG: - begin - usr_bwctrl_value <= slave_writedata[3:0]; - bwctrl_changed <= 1'b1; - bwctrl_done_q <= 0; - dprio_start <= 1'b1; - operation_address <= BWCTRL_REG; - end - CP_CURRENT_REG: - begin - usr_cp_current_value <= slave_writedata[2:0]; - cp_current_changed <= 1'b1; - cp_current_done_q <= 0; - dprio_start <= 1'b1; - operation_address <= CP_CURRENT_REG; - end - VCO_REG: - begin - usr_vco_value <= slave_writedata[0]; - vco_changed <= 1'b1; - vco_done_q <= 0; - dprio_start <= 1'b1; - operation_address <= VCO_REG; - end - ANY_DPRIO: - begin - operation_address <= ANY_DPRIO; - manual_dprio_changed <= 1'b1; - usr_dprio_address <= slave_writedata[5:0]; - usr_dprio_writedata_0 <= slave_writedata[21:6]; - usr_r_w <= slave_writedata[22]; - manual_dprio_done_q <= 0; - dprio_start <= 1'b1; - end - MIF_REG: - begin - mif_reg_asserted <= 1'b1; - mif_base_addr <= slave_writedata[ROM_ADDR_WIDTH-1:0]; - mif_start_assert <= 1'b1; - end - endcase - end - end - end - //C Counter assigning values to the 2-d array of values for each C counter - - reg [4:0] j; - always @(posedge clk) - begin - - if (reset) - begin - c_cnt_changed[17:0] <= 0; - for (j = 0; j < number_of_counters; j = j + 1'b1) - begin : c_cnt_reset - temp_c_cnt_bypass_en[j] <= 0; - temp_c_cnt_odd_duty_div_en[j] <= 0; - temp_c_cnt_lo[j][7:0] <= 0; - temp_c_cnt_hi[j][7:0] <= 0; - end - end - else - begin - if (dprio_write_done) - begin - c_cnt_changed <= 0; - end - if (any_c_cnt_changed && (operation_address == C_COUNTERS_REG)) - begin - case (cnt_sel) - CNT_0: - begin - temp_c_cnt_lo [0] <= usr_c_cnt_lo; - temp_c_cnt_hi [0] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [0] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [0] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [0] <= 1'b1; - end - CNT_1: - begin - temp_c_cnt_lo [1] <= usr_c_cnt_lo; - temp_c_cnt_hi [1] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [1] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [1] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [1] <= 1'b1; - end - CNT_2: - begin - temp_c_cnt_lo [2] <= usr_c_cnt_lo; - temp_c_cnt_hi [2] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [2] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [2] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [2] <= 1'b1; - end - CNT_3: - begin - temp_c_cnt_lo [3] <= usr_c_cnt_lo; - temp_c_cnt_hi [3] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [3] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [3] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [3] <= 1'b1; - end - CNT_4: - begin - temp_c_cnt_lo [4] <= usr_c_cnt_lo; - temp_c_cnt_hi [4] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [4] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [4] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [4] <= 1'b1; - end - CNT_5: - begin - temp_c_cnt_lo [5] <= usr_c_cnt_lo; - temp_c_cnt_hi [5] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [5] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [5] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [5] <= 1'b1; - end - CNT_6: - begin - temp_c_cnt_lo [6] <= usr_c_cnt_lo; - temp_c_cnt_hi [6] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [6] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [6] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [6] <= 1'b1; - end - CNT_7: - begin - temp_c_cnt_lo [7] <= usr_c_cnt_lo; - temp_c_cnt_hi [7] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [7] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [7] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [7] <= 1'b1; - end - CNT_8: - begin - temp_c_cnt_lo [8] <= usr_c_cnt_lo; - temp_c_cnt_hi [8] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [8] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [8] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [8] <= 1'b1; - end - CNT_9: - begin - temp_c_cnt_lo [9] <= usr_c_cnt_lo; - temp_c_cnt_hi [9] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [9] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [9] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [9] <= 1'b1; - end - CNT_10: - begin - temp_c_cnt_lo [10] <= usr_c_cnt_lo; - temp_c_cnt_hi [10] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [10] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [10] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [10] <= 1'b1; - end - CNT_11: - begin - temp_c_cnt_lo [11] <= usr_c_cnt_lo; - temp_c_cnt_hi [11] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [11] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [11] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [11] <= 1'b1; - end - CNT_12: - begin - temp_c_cnt_lo [12] <= usr_c_cnt_lo; - temp_c_cnt_hi [12] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [12] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [12] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [12] <= 1'b1; - end - CNT_13: - begin - temp_c_cnt_lo [13] <= usr_c_cnt_lo; - temp_c_cnt_hi [13] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [13] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [13] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [13] <= 1'b1; - end - CNT_14: - begin - temp_c_cnt_lo [14] <= usr_c_cnt_lo; - temp_c_cnt_hi [14] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [14] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [14] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [14] <= 1'b1; - end - CNT_15: - begin - temp_c_cnt_lo [15] <= usr_c_cnt_lo; - temp_c_cnt_hi [15] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [15] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [15] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [15] <= 1'b1; - end - CNT_16: - begin - temp_c_cnt_lo [16] <= usr_c_cnt_lo; - temp_c_cnt_hi [16] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [16] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [16] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [16] <= 1'b1; - end - CNT_17: - begin - temp_c_cnt_lo [17] <= usr_c_cnt_lo; - temp_c_cnt_hi [17] <= usr_c_cnt_hi; - temp_c_cnt_bypass_en [17] <= usr_c_cnt_bypass_en; - temp_c_cnt_odd_duty_div_en [17] <= usr_c_cnt_odd_duty_div_en; - c_cnt_changed [17] <= 1'b1; - end - endcase - - end - end - end - - - //logic to handle which writes the user indicated and wants to start. - assign usr_valid_changes =dsm_k_changed| any_c_cnt_changed |n_cnt_changed | m_cnt_changed | dps_changed_valid |manual_dprio_changed |cp_current_changed|bwctrl_changed|vco_changed; - - - //start the reconfig operations by writing to the DPRIO - reg break_loop; - reg [4:0] i; - always @(*) - begin - dprio_temp_read_1 = 0; - dprio_temp_read_2 = 0; - dprio_temp_m_n_c_readdata_1_d = 0; - dprio_temp_m_n_c_readdata_2_d = 0; - break_loop = 0; - dprio_next_state = DPRIO_IDLE; - avmm_dprio_write = 0; - avmm_dprio_read = 0; - avmm_dprio_address = 0; - avmm_dprio_writedata = 0; - avmm_dprio_byteen = 0; - dprio_write_done = 1; - manual_dprio_done_d = 0; - n_cnt_done_d = 0; - dsm_k_done_d = 0; - dsm_k_ready_false_done_d = 0; - m_cnt_done_d = 0; - c_cnt_done_d[17:0] = 0; - all_c_cnt_done_d = 0; - bwctrl_done_d = 0; - cp_current_done_d = 0; - vco_done_d = 0; - i = 0; - - // Deassert dprio_write_done so it doesn't reset mif_reg_asserted (toggled writes) - if (dprio_start | mif_start_assert) - dprio_write_done = 0; - - if (current_state == WAIT_ON_LOCK) - begin - case (dprio_cur_state) - ONE: - begin - if (n_cnt_changed & !n_cnt_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - dprio_next_state = TWO; - avmm_dprio_address = N_CNT_DIV_ADDR; - avmm_dprio_writedata[7:0] = usr_n_cnt_lo; - avmm_dprio_writedata[15:8] = usr_n_cnt_hi; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - dprio_next_state = TWO; - avmm_dprio_address = M_CNT_DIV_ADDR; - avmm_dprio_writedata[7:0] = usr_m_cnt_lo; - avmm_dprio_writedata[15:8] = usr_m_cnt_hi; - end - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - - for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_write_hilo - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - dprio_write_done = 0; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - dprio_next_state = TWO; - if (fpll_1) avmm_dprio_address = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - i; - else avmm_dprio_address = C_CNT_0_DIV_ADDR + i; - avmm_dprio_writedata[7:0] = temp_c_cnt_lo[i]; - avmm_dprio_writedata[15:8] = temp_c_cnt_hi[i]; - //To break from the loop, since only one counter - //is addressed at a time - break_loop = 1'b1; - end - end - end - else if (dsm_k_changed & !dsm_k_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 0; - dprio_next_state = TWO; - end - else if (bwctrl_changed & !bwctrl_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 0; - dprio_next_state = TWO; - end - else if (cp_current_changed & !cp_current_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 0; - dprio_next_state = TWO; - end - else if (vco_changed & !vco_done_q) - begin - dprio_write_done = 0; - avmm_dprio_write = 0; - dprio_next_state = TWO; - end - else if (manual_dprio_changed & !manual_dprio_done_q) - begin - dprio_write_done = 0; - avmm_dprio_byteen = 2'b11; - dprio_next_state = TWO; - avmm_dprio_write = usr_r_w; - avmm_dprio_address = usr_dprio_address; - avmm_dprio_writedata[15:0] = usr_dprio_writedata_0; - end - else dprio_next_state = DPRIO_IDLE; - end - - TWO: - begin - //handle reading the two setting bits on n_cnt, then - //writing them back while preserving other bits. - //Issue two consecutive reads then wait; readLatency=3 - dprio_write_done = 0; - dprio_next_state = THREE; - avmm_dprio_byteen = 2'b11; - avmm_dprio_read = 1'b1; - if (n_cnt_changed & !n_cnt_done_q) - begin - avmm_dprio_address = N_CNT_BYPASS_EN_ADDR; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - avmm_dprio_address = M_CNT_BYPASS_EN_ADDR; - end - - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_read_bypass - if (fpll_1) - begin - if (i > 13) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; - break_loop = 1'b1; - end - end - end - else - begin - if (i < 4) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; - break_loop = 1'b1; - end - end - end - end - end - //reading the K ready 16 bit word. Need to write 0 to it - //afterwards to indicate that K has not been done writing - else if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_READY_ADDR; - dprio_next_state = FOUR; - end - else if (bwctrl_changed & !bwctrl_done_q) - begin - avmm_dprio_address = BWCTRL_ADDR; - dprio_next_state = FOUR; - end - else if (cp_current_changed & !cp_current_done_q) - begin - avmm_dprio_address = CP_CURRENT_ADDR; - dprio_next_state = FOUR; - end - else if (vco_changed & !vco_done_q) - begin - avmm_dprio_address = VCO_ADDR; - dprio_next_state = FOUR; - end - else if (manual_dprio_changed & !manual_dprio_done_q) - begin - avmm_dprio_read = ~usr_r_w; - avmm_dprio_address = usr_dprio_address; - dprio_next_state = DPRIO_DONE; - end - else dprio_next_state = DPRIO_IDLE; - end - THREE: - begin - dprio_write_done = 0; - avmm_dprio_byteen = 2'b11; - avmm_dprio_read = 1'b1; - dprio_next_state = FOUR; - if (n_cnt_changed & !n_cnt_done_q) - begin - avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR; - end - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_read_odd_div - if (fpll_1) - begin - if (i > 13) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; - break_loop = 1'b1; - end - end - end - else - begin - if (i < 4) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; - break_loop = 1'b1; - end - end - end - end - end - else dprio_next_state = DPRIO_IDLE; - end - FOUR: - begin - dprio_temp_read_1 = 1'b1; - dprio_write_done = 0; - if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed) - begin - dprio_temp_m_n_c_readdata_1_d = dprio_readdata; - dprio_next_state = FIVE; - end - else dprio_next_state = DPRIO_IDLE; - end - FIVE: - begin - dprio_write_done = 0; - dprio_temp_read_2 = 1'b1; - if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed) - begin - //this is where DSM ready value comes. - //Need to store in a register to be used later - dprio_temp_m_n_c_readdata_2_d = dprio_readdata; - dprio_next_state = SIX; - end - else dprio_next_state = DPRIO_IDLE; - end - SIX: - begin - dprio_write_done = 0; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - dprio_next_state = SEVEN; - avmm_dprio_writedata = dprio_temp_m_n_c_readdata_1_q; - if (n_cnt_changed & !n_cnt_done_q) - begin - avmm_dprio_address = N_CNT_BYPASS_EN_ADDR; - avmm_dprio_writedata[5] = usr_n_cnt_bypass_en; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - avmm_dprio_address = M_CNT_BYPASS_EN_ADDR; - avmm_dprio_writedata[4] = usr_m_cnt_bypass_en; - end - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_write_bypass - if (fpll_1) - begin - if (i > 13) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; - avmm_dprio_writedata[i-14] = temp_c_cnt_bypass_en[i]; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; - avmm_dprio_writedata[i] = temp_c_cnt_bypass_en[i]; - break_loop = 1'b1; - end - end - end - else - begin - if (i < 4) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; - avmm_dprio_writedata[3-i] = temp_c_cnt_bypass_en[i]; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; - avmm_dprio_writedata[17-i] = temp_c_cnt_bypass_en[i]; - break_loop = 1'b1; - end - end - end - end - end - else if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_write = 0; - end - else if (bwctrl_changed & !bwctrl_done_q) - begin - avmm_dprio_write = 0; - end - else if (cp_current_changed & !cp_current_done_q) - begin - avmm_dprio_write = 0; - end - else if (vco_changed & !vco_done_q) - begin - avmm_dprio_write = 0; - end - else dprio_next_state = DPRIO_IDLE; - end - SEVEN: - begin - dprio_write_done = 0; - dprio_next_state = EIGHT; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q; - if (n_cnt_changed & !n_cnt_done_q) - begin - avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[5] = usr_n_cnt_odd_duty_div_en; - n_cnt_done_d = 1'b1; - end - else if (m_cnt_changed & !m_cnt_done_q) - begin - avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[4] = usr_m_cnt_odd_duty_div_en; - m_cnt_done_d = 1'b1; - end - - else if (any_c_cnt_changed & !all_c_cnt_done_q) - begin - for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) - begin : c_cnt_write_odd_div - if (fpll_1) - begin - if (i > 13) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[i-14] = temp_c_cnt_odd_duty_div_en[i]; - c_cnt_done_d[i] = 1'b1; - //have to OR the signals to prevent - //overwriting of previous dones - c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[i] = temp_c_cnt_odd_duty_div_en[i]; - c_cnt_done_d[i] = 1'b1; - c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; - break_loop = 1'b1; - end - end - end - else - begin - if (i < 4) - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[3-i] = temp_c_cnt_odd_duty_div_en[i]; - c_cnt_done_d[i] = 1'b1; - //have to OR the signals to prevent - //overwriting of previous dones - c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; - break_loop = 1'b1; - end - end - else - begin - if (c_cnt_changed[i] & !c_cnt_done_q[i]) - begin - avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; - avmm_dprio_writedata[17-i] = temp_c_cnt_odd_duty_div_en[i]; - c_cnt_done_d[i] = 1'b1; - c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; - break_loop = 1'b1; - end - end - end - end - end - else if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_READY_ADDR; - avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b0; - dsm_k_ready_false_done_d = 1'b1; - end - else if (bwctrl_changed & !bwctrl_done_q) - begin - avmm_dprio_address = BWCTRL_ADDR; - avmm_dprio_writedata[3:0] = usr_bwctrl_value; - bwctrl_done_d = 1'b1; - end - else if (cp_current_changed & !cp_current_done_q) - begin - avmm_dprio_address = CP_CURRENT_ADDR; - avmm_dprio_writedata[2:0] = usr_cp_current_value; - cp_current_done_d = 1'b1; - end - else if (vco_changed & !vco_done_q) - begin - avmm_dprio_address = VCO_ADDR; - avmm_dprio_writedata[8] = usr_vco_value; - vco_done_d = 1'b1; - end - - - //if all C_cnt that were changed are done, then assert all_c_cnt_done - if (c_cnt_done_d == c_cnt_changed) - all_c_cnt_done_d = 1'b1; - if (n_cnt_changed & n_cnt_done_d) - dprio_next_state = DPRIO_DONE; - if (any_c_cnt_changed & !all_c_cnt_done_d & !all_c_cnt_done_q) - dprio_next_state = ONE; - else if (m_cnt_changed & !m_cnt_done_d & !m_cnt_done_q) - dprio_next_state = ONE; - else if (dsm_k_changed & !dsm_k_ready_false_done_d) - dprio_next_state = TWO; - else if (dsm_k_changed & !dsm_k_done_q) - dprio_next_state = EIGHT; - else if (bwctrl_changed & !bwctrl_done_d) - dprio_next_state = TWO; - else if (cp_current_changed & !cp_current_done_d) - dprio_next_state = TWO; - else if (vco_changed & !vco_done_d) - dprio_next_state = TWO; - else - begin - dprio_next_state = DPRIO_DONE; - dprio_write_done = 1'b1; - end - end - //finish the rest of the DSM reads/writes - //writing k value, writing k_ready to 1. - EIGHT: - begin - dprio_write_done = 0; - dprio_next_state = NINE; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_0; - avmm_dprio_writedata[15:0] = usr_k_value[15:0]; - end - end - NINE: - begin - dprio_write_done = 0; - dprio_next_state = TEN; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_1; - avmm_dprio_writedata[15:0] = usr_k_value[31:16]; - end - end - TEN: - begin - dprio_write_done = 0; - dprio_next_state = ONE; - avmm_dprio_write = 1'b1; - avmm_dprio_byteen = 2'b11; - if (dsm_k_changed & !dsm_k_done_q) - begin - avmm_dprio_address = DSM_K_READY_ADDR; - //already have the readdata for DSM_K_READY_ADDR since we read it - //earlier. Just reuse here - avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q; - avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b1; - dsm_k_done_d = 1'b1; - end - end - DPRIO_DONE: - begin - dprio_write_done = 1'b1; - if (dprio_start) dprio_next_state = DPRIO_IDLE; - else dprio_next_state = DPRIO_DONE; - end - DPRIO_IDLE: - begin - if (dprio_start) dprio_next_state = ONE; - else dprio_next_state = DPRIO_IDLE; - end - default: dprio_next_state = 4'bxxxx; - endcase - end - - end - - - //assert the waitreq signal according to the state of the slave - assign slave_waitrequest = (slave_mode==mode_WR) ? ((locked === 1'b1) ? (((current_state==WAIT_ON_LOCK) & !dprio_write_done) | !dps_done |reset|!dprio_init_done) : 1'b1) : 1'b0; - - // Read operations - always @(*) - begin - status = 0; - if (slave_mode == mode_POLL) - //asserting status to 1 if the slave is done. - status = (current_state == LOCKED); - end - //************************************************************// - //************************************************************// - //******************** READ STATE MACHINE ********************// - //************************************************************// - //************************************************************// - reg [1:0] current_read_state; - reg [1:0] next_read_state; - reg [5:0] slave_address_int_d; - reg [5:0] slave_address_int_q; - reg dprio_read_1; - reg [5:0] dprio_address_1; - reg [1:0] dprio_byteen_1; - reg [4:0] usr_cnt_sel_1; - localparam READ = 2'b00, READ_WAIT = 2'b01, READ_IDLE = 2'b10, READ_POST_WAIT = 2'b11; - - always @(*) - begin - if(next_read_state == READ_IDLE) - begin - read_waitrequest <= 1'b0; - end - else - begin - read_waitrequest <= 1'b1; - end - end - - always @(posedge clk) - begin - if (reset) - begin - current_read_state <= READ_IDLE; - slave_address_int_q <= 0; - slave_readdata_q <= 0; - end - else - begin - current_read_state <= next_read_state; - slave_address_int_q <= slave_address_int_d; - slave_readdata_q <= slave_readdata_d; - end - end - always @(*) - begin - dprio_read_1 = 0; - dprio_address_1 = 0; - dprio_byteen_1 = 0; - slave_address_int_d = 0; - slave_readdata_d = 0; - status_read = 0; - usr_cnt_sel_1 = 0; - case(current_read_state) - READ_IDLE: - begin - slave_address_int_d = 0; - next_read_state = READ_IDLE; - if ((current_state != WAIT_ON_LOCK) && slave_read) - begin - slave_address_int_d = slave_address; - if ((slave_address >= CNT_BASE) && (slave_address < CNT_BASE+18)) - begin - next_read_state = READ_WAIT; - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - usr_cnt_sel_1 = (slave_address[4:0] - CNT_BASE); - if (fpll_1) dprio_address_1 = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - cnt_sel; - else dprio_address_1 = C_CNT_0_DIV_ADDR + cnt_sel; - end - else - begin - case (slave_address) - MODE_REG: - begin - next_read_state = READ_WAIT; - slave_readdata_d = slave_mode; - end - STATUS_REG: - begin - next_read_state = READ_WAIT; - status_read = 1'b1; - slave_readdata_d = status; - end - N_REG: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - dprio_address_1 = N_CNT_DIV_ADDR; - next_read_state = READ_WAIT; - end - M_REG: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - dprio_address_1 = M_CNT_DIV_ADDR; - next_read_state = READ_WAIT; - end - BWCTRL_REG: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - dprio_address_1 = BWCTRL_ADDR; - next_read_state = READ_WAIT; - end - CP_CURRENT_REG: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - dprio_address_1 = CP_CURRENT_ADDR; - next_read_state = READ_WAIT; - end - VCO_REG: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = 1'b1; - dprio_address_1 = VCO_ADDR; - next_read_state = READ_WAIT; - end - ANY_DPRIO: - begin - dprio_byteen_1 = 2'b11; - dprio_read_1 = ~slave_writedata[22]; - dprio_address_1 = slave_writedata[5:0]; - next_read_state = READ_WAIT; - end - default : next_read_state = READ_IDLE; - endcase - end - end - else - next_read_state = READ_IDLE; - end - READ_WAIT: - begin - next_read_state = READ; - slave_address_int_d = slave_address_int_q; - case (slave_address_int_q) - MODE_REG: - begin - slave_readdata_d = slave_readdata_q; - end - STATUS_REG: - begin - slave_readdata_d = slave_readdata_q; - end - endcase - end - READ: - begin - next_read_state = READ_POST_WAIT; - slave_address_int_d = slave_address_int_q; - slave_readdata_d = dprio_readdata; - case (slave_address_int_q) - MODE_REG: - begin - slave_readdata_d = slave_readdata_q; - end - STATUS_REG: - begin - slave_readdata_d = slave_readdata_q; - end - BWCTRL_REG: - begin - slave_readdata_d = dprio_readdata[3:0]; - end - CP_CURRENT_REG: - begin - slave_readdata_d = dprio_readdata[2:0]; - end - VCO_REG: - begin - slave_readdata_d = dprio_readdata[8]; - end - ANY_DPRIO: - begin - slave_readdata_d = dprio_readdata; - end - endcase - end - READ_POST_WAIT: - begin - next_read_state = READ_IDLE; - end - default: next_read_state = 2'bxx; - endcase - end - - - dyn_phase_shift dyn_phase_shift_inst ( - .clk(clk), - .reset(reset), - .phase_done(phase_done), - .pll_start_valid(pll_start_valid), - .dps_changed(dps_changed), - .dps_changed_valid(dps_changed_valid), - .dprio_write_done(dprio_write_done), - .usr_num_shifts(usr_num_shifts), - .usr_cnt_sel(usr_cnt_sel|usr_cnt_sel_1), - .usr_up_dn(usr_up_dn), - .locked(locked), - .dps_done(dps_done), - .phase_en(phase_en), - .up_dn(up_dn), - .cnt_sel(cnt_sel)); - defparam dyn_phase_shift_inst.device_family = device_family; - - assign dprio_clk = clk; - self_reset self_reset_inst (mgmt_reset, clk, reset, dprio_init_reset); - - dprio_mux dprio_mux_inst ( - .init_dprio_address(init_dprio_address), - .init_dprio_read(init_dprio_read), - .init_dprio_byteen(init_dprio_byteen), - .init_dprio_write(init_dprio_write), - .init_dprio_writedata(init_dprio_writedata), - - - .init_atpgmode(init_atpgmode), - .init_mdio_dis(init_mdio_dis), - .init_scanen(init_scanen), - .init_ser_shift_load(init_ser_shift_load), - .dprio_init_done(dprio_init_done), - - // Inputs from avmm master - .avmm_dprio_address(avmm_dprio_address | dprio_address_1), - .avmm_dprio_read(avmm_dprio_read | dprio_read_1), - .avmm_dprio_byteen(avmm_dprio_byteen | dprio_byteen_1), - .avmm_dprio_write(avmm_dprio_write), - .avmm_dprio_writedata(avmm_dprio_writedata), - - .avmm_atpgmode(avmm_atpgmode), - .avmm_mdio_dis(avmm_mdio_dis), - .avmm_scanen(avmm_scanen), - - // Outputs to fpll - .dprio_address(dprio_address), - .dprio_read(dprio_read), - .dprio_byteen(dprio_byteen), - .dprio_write(dprio_write), - .dprio_writedata(dprio_writedata), - - .atpgmode(dprio_atpgmode), - .mdio_dis(dprio_mdio_dis), - .scanen(dprio_scanen), - .ser_shift_load(dprio_ser_shift_load) - ); - - - fpll_dprio_init fpll_dprio_init_inst ( - .clk(clk), - .reset_n(~reset), - .locked(locked), - - //outputs - .dprio_address(init_dprio_address), - .dprio_read(init_dprio_read), - .dprio_byteen(init_dprio_byteen), - .dprio_write(init_dprio_write), - .dprio_writedata(init_dprio_writedata), - - .atpgmode(init_atpgmode), - .mdio_dis(init_mdio_dis), - .scanen(init_scanen), - .ser_shift_load(init_ser_shift_load), - .dprio_init_done(dprio_init_done)); - - //address luts, to be reconfigged by the Fitter - //FPLL_1 or 0 address lut - generic_lcell_comb lcell_fpll_0_1 ( - .dataa(1'b0), - .combout (fpll_1)); - defparam lcell_fpll_0_1.lut_mask = 64'hAAAAAAAAAAAAAAAA; - defparam lcell_fpll_0_1.dont_touch = "on"; - defparam lcell_fpll_0_1.family = device_family; - - - wire dprio_read_combout; - generic_lcell_comb lcell_dprio_read ( - .dataa(fpll_1), - .datab(dprio_read), - .datac(1'b0), - .datad(1'b0), - .datae(1'b0), - .dataf(1'b0), - .combout (dprio_read_combout)); - defparam lcell_dprio_read.lut_mask = 64'hCCCCCCCCCCCCCCCC; - defparam lcell_dprio_read.dont_touch = "on"; - defparam lcell_dprio_read.family = device_family; - - - - - - //assign reconfig_to_pll signals - assign reconfig_to_pll[0] = dprio_clk; - assign reconfig_to_pll[1] = ~dprio_init_reset; - assign reconfig_to_pll[2] = dprio_write; - assign reconfig_to_pll[3] = dprio_read_combout; - assign reconfig_to_pll[9:4] = dprio_address; - assign reconfig_to_pll[25:10] = dprio_writedata; - assign reconfig_to_pll[27:26] = dprio_byteen; - assign reconfig_to_pll[28] = dprio_ser_shift_load; - assign reconfig_to_pll[29] = dprio_mdio_dis; - assign reconfig_to_pll[30] = phase_en; - assign reconfig_to_pll[31] = up_dn; - assign reconfig_to_pll[36:32] = cnt_sel; - assign reconfig_to_pll[37] = dprio_scanen; - assign reconfig_to_pll[38] = dprio_atpgmode; - //assign reconfig_to_pll[40:37] = clken; - assign reconfig_to_pll[63:39] = 0; - - //assign reconfig_from_pll signals - assign dprio_readdata = reconfig_from_pll [15:0]; - assign locked_orig = reconfig_from_pll [16]; - assign phase_done = reconfig_from_pll [17]; - -endmodule -module self_reset (input wire mgmt_reset, input wire clk, output wire reset, output wire init_reset); - - localparam RESET_COUNTER_VALUE = 3'd2; - localparam INITIAL_WAIT_VALUE = 9'd340; - reg [9:0]counter; - reg local_reset; - reg usr_mode_init_wait; - initial - begin - local_reset = 1'b1; - counter = 0; - usr_mode_init_wait = 0; - end - - always @(posedge clk) - begin - if (mgmt_reset) - begin - counter <= 0; - end - else - begin - if (!usr_mode_init_wait) - begin - if (counter == INITIAL_WAIT_VALUE) - begin - local_reset <= 0; - usr_mode_init_wait <= 1'b1; - counter <= 0; - end - else - begin - counter <= counter + 1'b1; - end - end - else - begin - if (counter == RESET_COUNTER_VALUE) - local_reset <= 0; - else - counter <= counter + 1'b1; - end - end - end - assign reset = mgmt_reset | local_reset; - assign init_reset = local_reset; -endmodule - -module dprio_mux ( - // Inputs from init block - input [ 5:0] init_dprio_address, - input init_dprio_read, - input [ 1:0] init_dprio_byteen, - input init_dprio_write, - input [15:0] init_dprio_writedata, - - input init_atpgmode, - input init_mdio_dis, - input init_scanen, - input init_ser_shift_load, - input dprio_init_done, - - // Inputs from avmm master - input [ 5:0] avmm_dprio_address, - input avmm_dprio_read, - input [ 1:0] avmm_dprio_byteen, - input avmm_dprio_write, - input [15:0] avmm_dprio_writedata, - - input avmm_atpgmode, - input avmm_mdio_dis, - input avmm_scanen, - input avmm_ser_shift_load, - - // Outputs to fpll - output [ 5:0] dprio_address, - output dprio_read, - output [ 1:0] dprio_byteen, - output dprio_write, - output [15:0] dprio_writedata, - - output atpgmode, - output mdio_dis, - output scanen, - output ser_shift_load -); - - assign dprio_address = dprio_init_done ? avmm_dprio_address : init_dprio_address; - assign dprio_read = dprio_init_done ? avmm_dprio_read : init_dprio_read; - assign dprio_byteen = dprio_init_done ? avmm_dprio_byteen : init_dprio_byteen; - assign dprio_write = dprio_init_done ? avmm_dprio_write : init_dprio_write; - assign dprio_writedata = dprio_init_done ? avmm_dprio_writedata : init_dprio_writedata; - - assign atpgmode = init_atpgmode; - assign scanen = init_scanen; - assign mdio_dis = init_mdio_dis; - assign ser_shift_load = init_ser_shift_load ; -endmodule -module fpll_dprio_init ( - input clk, - input reset_n, - input locked, - - output [ 5:0] dprio_address, - output dprio_read, - output [ 1:0] dprio_byteen, - output dprio_write, - output [15:0] dprio_writedata, - - output reg atpgmode, - output reg mdio_dis, - output reg scanen, - output reg ser_shift_load, - output reg dprio_init_done -); - - reg [1:0] rst_n = 2'b00; - reg [6:0] count = 7'd0; - reg init_done_forever; - - // Internal versions of control signals - wire int_mdio_dis; - wire int_ser_shift_load; - wire int_dprio_init_done; - wire int_atpgmode/*synthesis keep*/; - wire int_scanen/*synthesis keep*/; - - - assign dprio_address = count[6] ? 5'b0 : count[5:0] ; - assign dprio_byteen = 2'b11; // always enabled - assign dprio_write = ~count[6] & reset_n ; // write for first 64 cycles - assign dprio_read = 1'b0; - assign dprio_writedata = 16'd0; - - assign int_ser_shift_load = count[6] ? |count[2:1] : 1'b1; - assign int_mdio_dis = count[6] ? ~count[2] : 1'b1; - assign int_dprio_init_done = ~init_done_forever ? (count[6] ? &count[2:0] : 1'b0) - : 1'b1; - assign int_atpgmode = 0; - assign int_scanen = 0; - - initial begin - count = 7'd0; - init_done_forever = 0; - mdio_dis = 1'b1; - ser_shift_load = 1'b1; - dprio_init_done = 1'b0; - scanen = 1'b0; - atpgmode = 1'b0; - end - - // reset synch. - always @(posedge clk or negedge reset_n) - if(!reset_n) rst_n <= 2'b00; - else rst_n <= {rst_n[0],1'b1}; - - // counter - always @(posedge clk) - begin - if (!rst_n[1]) - init_done_forever <= 1'b0; - else - begin - if (count[6] && &count[1:0]) - init_done_forever <= 1'b1; - end - end - always @(posedge clk or negedge rst_n[1]) - begin - if(!rst_n[1]) - begin - count <= 7'd0; - end - else if(~int_dprio_init_done) - begin - count <= count + 7'd1; - end - else - begin - count <= count; - end - end - - // outputs - always @(posedge clk) begin - mdio_dis <= int_mdio_dis; - ser_shift_load <= int_ser_shift_load; - dprio_init_done <= int_dprio_init_done; - atpgmode <= int_atpgmode; - scanen <= int_scanen; - end - -endmodule -module dyn_phase_shift -#( - parameter device_family = "Stratix V" -) ( - - input wire clk, - input wire reset, - input wire phase_done, - input wire pll_start_valid, - input wire dps_changed, - input wire dprio_write_done, - input wire [15:0] usr_num_shifts, - input wire [4:0] usr_cnt_sel, - input wire usr_up_dn, - input wire locked, - - //output - output wire dps_done, - output reg phase_en, - output wire up_dn, - output wire dps_changed_valid, - output wire [4:0] cnt_sel); - - - - reg first_phase_shift_d; - reg first_phase_shift_q; - reg [15:0] phase_en_counter; - reg [3:0] dps_current_state; - reg [3:0] dps_next_state; - localparam DPS_START = 4'd0, DPS_WAIT_PHASE_DONE = 4'd1, DPS_DONE = 4'd2, DPS_WAIT_PHASE_EN = 4'd3, DPS_WAIT_DPRIO_WRITING = 4'd4, DPS_CHANGED = 4'd5; - localparam PHASE_EN_WAIT_COUNTER = 5'd1; - - reg [15:0] shifts_done_counter; - reg phase_done_final; - wire gnd /*synthesis keep*/; - - //fsm - //always block controlling the state regs - always @(posedge clk) - begin - if (reset) - begin - dps_current_state <= DPS_DONE; - end - else - begin - dps_current_state <= dps_next_state; - end - end - //the combinational part. assigning the next state - //this turns on the phase_done_final signal when phase_done does this: - //_____ ______ - // |______| - always @(*) - begin - phase_done_final = 0; - first_phase_shift_d = 0; - phase_en = 0; - dps_next_state = DPS_DONE; - case (dps_current_state) - DPS_START: - begin - phase_en = 1'b1; - dps_next_state = DPS_WAIT_PHASE_EN; - end - DPS_WAIT_PHASE_EN: - begin - phase_en = 1'b1; - if (first_phase_shift_q) - begin - first_phase_shift_d = 1'b1; - dps_next_state = DPS_WAIT_PHASE_EN; - end - else - begin - if (phase_en_counter == PHASE_EN_WAIT_COUNTER) - dps_next_state = DPS_WAIT_PHASE_DONE; - else dps_next_state = DPS_WAIT_PHASE_EN; - end - end - DPS_WAIT_PHASE_DONE: - begin - if (!phase_done | !locked) - begin - dps_next_state = DPS_WAIT_PHASE_DONE; - end - else - begin - if ((usr_num_shifts != shifts_done_counter) & (usr_num_shifts != 0)) - begin - dps_next_state = DPS_START; - phase_done_final = 1'b1; - end - else - begin - dps_next_state = DPS_DONE; - end - - end - end - DPS_DONE: - begin - phase_done_final = 0; - if (dps_changed) - dps_next_state = DPS_CHANGED; - else dps_next_state = DPS_DONE; - - end - DPS_CHANGED: - begin - if (pll_start_valid) - dps_next_state = DPS_WAIT_DPRIO_WRITING; - else - dps_next_state = DPS_CHANGED; - end - DPS_WAIT_DPRIO_WRITING: - begin - if (dprio_write_done) - dps_next_state = DPS_START; - else - dps_next_state = DPS_WAIT_DPRIO_WRITING; - end - - default: dps_next_state = 4'bxxxx; - endcase - - - end - - always @(posedge clk) - begin - - - if (dps_current_state == DPS_WAIT_PHASE_DONE) - phase_en_counter <= 0; - else if (dps_current_state == DPS_WAIT_PHASE_EN) - phase_en_counter <= phase_en_counter + 1'b1; - - if (reset) - begin - phase_en_counter <= 0; - shifts_done_counter <= 1'b1; - first_phase_shift_q <= 1; - end - else - begin - if (first_phase_shift_d) - first_phase_shift_q <= 0; - if (dps_done) - begin - shifts_done_counter <= 1'b1; - end - else - begin - if (phase_done_final & (dps_next_state!= DPS_DONE)) - shifts_done_counter <= shifts_done_counter + 1'b1; - else - shifts_done_counter <= shifts_done_counter; - end - end - end - - assign dps_changed_valid = (dps_current_state == DPS_CHANGED); - assign dps_done =(dps_current_state == DPS_DONE) | (dps_current_state == DPS_CHANGED); - assign up_dn = usr_up_dn; - assign gnd = 1'b0; - - //cnt select luts (5) - generic_lcell_comb lcell_cnt_sel_0 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[0])); - defparam lcell_cnt_sel_0.lut_mask = 64'hAAAAAAAAAAAAAAAA; - defparam lcell_cnt_sel_0.dont_touch = "on"; - defparam lcell_cnt_sel_0.family = device_family; - generic_lcell_comb lcell_cnt_sel_1 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[1])); - defparam lcell_cnt_sel_1.lut_mask = 64'hCCCCCCCCCCCCCCCC; - defparam lcell_cnt_sel_1.dont_touch = "on"; - defparam lcell_cnt_sel_1.family = device_family; - generic_lcell_comb lcell_cnt_sel_2 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[2])); - defparam lcell_cnt_sel_2.lut_mask = 64'hF0F0F0F0F0F0F0F0; - defparam lcell_cnt_sel_2.dont_touch = "on"; - defparam lcell_cnt_sel_2.family = device_family; - generic_lcell_comb lcell_cnt_sel_3 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[3])); - defparam lcell_cnt_sel_3.lut_mask = 64'hFF00FF00FF00FF00; - defparam lcell_cnt_sel_3.dont_touch = "on"; - defparam lcell_cnt_sel_3.family = device_family; - generic_lcell_comb lcell_cnt_sel_4 ( - .dataa(usr_cnt_sel[0]), - .datab(usr_cnt_sel[1]), - .datac(usr_cnt_sel[2]), - .datad(usr_cnt_sel[3]), - .datae(usr_cnt_sel[4]), - .dataf(gnd), - .combout (cnt_sel[4])); - defparam lcell_cnt_sel_4.lut_mask = 64'hFFFF0000FFFF0000; - defparam lcell_cnt_sel_4.dont_touch = "on"; - defparam lcell_cnt_sel_4.family = device_family; - - -endmodule - -module generic_lcell_comb -#( - //parameter - parameter family = "Stratix V", - parameter lut_mask = 64'hAAAAAAAAAAAAAAAA, - parameter dont_touch = "on" -) ( - - input dataa, - input datab, - input datac, - input datad, - input datae, - input dataf, - - output combout -); - - generate - if (family == "Stratix V") - begin - stratixv_lcell_comb lcell_inst ( - .dataa(dataa), - .datab(datab), - .datac(datac), - .datad(datad), - .datae(datae), - .dataf(dataf), - .combout (combout)); - defparam lcell_inst.lut_mask = lut_mask; - defparam lcell_inst.dont_touch = dont_touch; - end - else if (family == "Arria V") - begin - arriav_lcell_comb lcell_inst ( - .dataa(dataa), - .datab(datab), - .datac(datac), - .datad(datad), - .datae(datae), - .dataf(dataf), - .combout (combout)); - defparam lcell_inst.lut_mask = lut_mask; - defparam lcell_inst.dont_touch = dont_touch; - end - else if (family == "Arria V GZ") - begin - arriavgz_lcell_comb lcell_inst ( - .dataa(dataa), - .datab(datab), - .datac(datac), - .datad(datad), - .datae(datae), - .dataf(dataf), - .combout (combout)); - defparam lcell_inst.lut_mask = lut_mask; - defparam lcell_inst.dont_touch = dont_touch; - end - else if (family == "Cyclone V") - begin - cyclonev_lcell_comb lcell_inst ( - .dataa(dataa), - .datab(datab), - .datac(datac), - .datad(datad), - .datae(datae), - .dataf(dataf), - .combout (combout)); - defparam lcell_inst.lut_mask = lut_mask; - defparam lcell_inst.dont_touch = dont_touch; - end - endgenerate -endmodule +`timescale 1ps/1ps + +module altera_pll_reconfig_core +#( + parameter reconf_width = 64, + parameter device_family = "Cyclone V", + // MIF Streaming parameters + parameter RECONFIG_ADDR_WIDTH = 6, + parameter RECONFIG_DATA_WIDTH = 32, + parameter ROM_ADDR_WIDTH = 9, + parameter ROM_DATA_WIDTH = 32, + parameter ROM_NUM_WORDS = 512 +) ( + + //input + input wire mgmt_clk, + input wire mgmt_reset, + + + //conduits + output wire [reconf_width-1:0] reconfig_to_pll, + input wire [reconf_width-1:0] reconfig_from_pll, + + // user data (avalon-MM slave interface) + output wire [31:0] mgmt_readdata, + output wire mgmt_waitrequest, + input wire [5:0] mgmt_address, + input wire mgmt_read, + input wire mgmt_write, + input wire [31:0] mgmt_writedata, + + //other + output wire mif_start_out, + output reg [ROM_ADDR_WIDTH-1:0] mif_base_addr +); + localparam mode_WR = 1'b0; + localparam mode_POLL = 1'b1; + localparam MODE_REG = 6'b000000; + localparam STATUS_REG = 6'b000001; + localparam START_REG = 6'b000010; + localparam N_REG = 6'b000011; + localparam M_REG = 6'b000100; + localparam C_COUNTERS_REG = 6'b000101; + localparam DPS_REG = 6'b000110; + localparam DSM_REG = 6'b000111; + localparam BWCTRL_REG = 6'b001000; + localparam CP_CURRENT_REG = 6'b001001; + localparam ANY_DPRIO = 6'b100000; + localparam CNT_BASE = 5'b001010; + localparam VCO_REG = 6'b011100; + localparam MIF_REG = 6'b011111; + + //C Counters + localparam number_of_counters = 5'd18; + localparam CNT_0 = 1'd0, CNT_1 = 5'd1, CNT_2 = 5'd2, + CNT_3 = 5'd3, CNT_4 = 5'd4, CNT_5 = 5'd5, + CNT_6 = 5'd6, CNT_7 = 5'd7, CNT_8 = 5'd8, + CNT_9 = 5'd9, CNT_10 = 5'd10, CNT_11 = 5'd11, + CNT_12 = 5'd12, CNT_13 = 5'd13, CNT_14 = 5'd14, + CNT_15 = 5'd15, CNT_16 = 5'd16, CNT_17 = 5'd17; + //C counter addresses + localparam C_CNT_0_DIV_ADDR = 5'h00; + localparam C_CNT_0_DIV_ADDR_DPRIO_1 = 5'h11; + localparam C_CNT_0_3_BYPASS_EN_ADDR = 5'h15; + localparam C_CNT_0_3_ODD_DIV_EN_ADDR = 5'h17; + localparam C_CNT_4_17_BYPASS_EN_ADDR = 5'h14; + localparam C_CNT_4_17_ODD_DIV_EN_ADDR = 5'h16; + //N counter addresses + localparam N_CNT_DIV_ADDR = 5'h13; + localparam N_CNT_BYPASS_EN_ADDR = 5'h15; + localparam N_CNT_ODD_DIV_EN_ADDR = 5'h17; + //M counter addresses + localparam M_CNT_DIV_ADDR = 5'h12; + localparam M_CNT_BYPASS_EN_ADDR = 5'h15; + localparam M_CNT_ODD_DIV_EN_ADDR = 5'h17; + + //DSM address + localparam DSM_K_FRACTIONAL_DIVISION_ADDR_0 = 5'h18; + localparam DSM_K_FRACTIONAL_DIVISION_ADDR_1 = 5'h19; + localparam DSM_K_READY_ADDR = 5'h17; + localparam DSM_K_DITHER_ADDR = 5'h17; + localparam DSM_OUT_SEL_ADDR = 6'h30; + + //Other DSM params + localparam DSM_K_READY_BIT_INDEX = 4'd11; + //BWCTRL address + //Bit 0-3 of addr + localparam BWCTRL_ADDR = 6'h30; + //CP_CURRENT address + //Bit 0-2 of addr + localparam CP_CURRENT_ADDR = 6'h31; + + // VCODIV address + localparam VCO_ADDR = 5'h17; + + localparam DPRIO_IDLE = 3'd0, ONE = 3'd1, TWO = 3'd2, THREE = 3'd3, FOUR = 3'd4, + FIVE = 3'd5, SIX = 3'd6, SEVEN = 3'd7, EIGHT = 4'd8, NINE = 4'd9, TEN = 4'd10, + ELEVEN = 4'd11, TWELVE = 4'd12, THIRTEEN = 4'd13, FOURTEEN = 4'd14, DPRIO_DONE = 4'd15; + localparam IDLE = 2'b00, WAIT_ON_LOCK = 2'b01, LOCKED = 2'b10; + + wire clk; + wire reset; + wire gnd; + + wire [5: 0] slave_address; + wire slave_read; + wire slave_write; + wire [31: 0] slave_writedata; + + reg [31: 0] slave_readdata_d; + reg [31: 0] slave_readdata_q; + wire slave_waitrequest; + reg slave_mode; + + assign clk = mgmt_clk; + + assign slave_address = mgmt_address; + assign slave_read = mgmt_read; + assign slave_write = mgmt_write; + assign slave_writedata = mgmt_writedata; + + reg read_waitrequest; + // Outputs + assign mgmt_readdata = slave_readdata_q; + assign mgmt_waitrequest = slave_waitrequest | read_waitrequest; //Read waitrequest asserted in polling mode + + //internal signals + wire locked_orig; + wire locked; + + wire pll_start; + wire pll_start_valid; + reg status_read; + wire read_slave_mode_asserted; + + wire pll_start_asserted; + + reg [1:0] current_state; + reg [1:0] next_state; + + reg status;//0=busy, 1=ready + //user_mode_init user_mode_init_inst (clk, reset, dprio_mdio_dis, ser_shift_load); + //declaring the init wires. These will have 0 on them for 64 clk cycles + wire [ 5:0] init_dprio_address; + wire init_dprio_read; + wire [ 1:0] init_dprio_byteen; + wire init_dprio_write; + wire [15:0] init_dprio_writedata; + + wire init_atpgmode; + wire init_mdio_dis; + wire init_scanen; + wire init_ser_shift_load; + wire dprio_init_done; + + //DPRIO output signals after initialization is done + wire dprio_clk; + reg avmm_dprio_write; + reg avmm_dprio_read; + reg [5:0] avmm_dprio_address; + reg [15:0] avmm_dprio_writedata; + reg [1:0] avmm_dprio_byteen; + wire avmm_atpgmode; + wire avmm_mdio_dis; + wire avmm_scanen; + + //Final output wires that are muxed between the init and avmm wires. + wire dprio_init_reset; + wire [5:0] dprio_address /*synthesis keep*/; + wire dprio_read/*synthesis keep*/; + wire [1:0] dprio_byteen/*synthesis keep*/; + wire dprio_write/*synthesis keep*/; + wire [15:0] dprio_writedata/*synthesis keep*/; + wire dprio_mdio_dis/*synthesis keep*/; + wire dprio_ser_shift_load/*synthesis keep*/; + wire dprio_atpgmode/*synthesis keep*/; + wire dprio_scanen/*synthesis keep*/; + + + //other PLL signals for dyn ph shift + wire phase_done/*synthesis keep*/; + wire phase_en/*synthesis keep*/; + wire up_dn/*synthesis keep*/; + wire [4:0] cnt_sel; + + //DPRIO input signals + wire [15:0] dprio_readdata; + + //internal logic signals + //storage registers for user sent data + reg dprio_temp_read_1; + reg dprio_temp_read_2; + reg dprio_start; + reg mif_start_assert; + reg dps_start_assert; + wire usr_valid_changes; + reg [3:0] dprio_cur_state; + reg [3:0] dprio_next_state; + reg [15:0] dprio_temp_m_n_c_readdata_1_d; + reg [15:0] dprio_temp_m_n_c_readdata_2_d; + reg [15:0] dprio_temp_m_n_c_readdata_1_q; + reg [15:0] dprio_temp_m_n_c_readdata_2_q; + reg dprio_write_done; + //C counters signals + reg [7:0] usr_c_cnt_lo; + reg [7:0] usr_c_cnt_hi; + reg usr_c_cnt_bypass_en; + reg usr_c_cnt_odd_duty_div_en; + reg [7:0] temp_c_cnt_lo [0:17]; + reg [7:0] temp_c_cnt_hi [0:17]; + reg temp_c_cnt_bypass_en [0:17]; + reg temp_c_cnt_odd_duty_div_en [0:17]; + reg any_c_cnt_changed; + reg all_c_cnt_done_q; + reg all_c_cnt_done_d; + reg [17:0] c_cnt_changed; + reg [17:0] c_cnt_done_d; + reg [17:0] c_cnt_done_q; + //N counter signals + reg [7:0] usr_n_cnt_lo; + reg [7:0] usr_n_cnt_hi; + reg usr_n_cnt_bypass_en; + reg usr_n_cnt_odd_duty_div_en; + reg n_cnt_changed; + reg n_cnt_done_d; + reg n_cnt_done_q; + //M counter signals + reg [7:0] usr_m_cnt_lo; + reg [7:0] usr_m_cnt_hi; + reg usr_m_cnt_bypass_en; + reg usr_m_cnt_odd_duty_div_en; + reg m_cnt_changed; + reg m_cnt_done_d; + reg m_cnt_done_q; + //dyn phase regs + reg [15:0] usr_num_shifts; + reg [4:0] usr_cnt_sel /*synthesis preserve*/; + reg usr_up_dn; + reg dps_changed; + wire dps_changed_valid; + wire dps_done; + + //DSM Signals + reg [31:0] usr_k_value; + reg dsm_k_changed; + reg dsm_k_done_d; + reg dsm_k_done_q; + reg dsm_k_ready_false_done_d; + //BW signals + reg [3:0] usr_bwctrl_value; + reg bwctrl_changed; + reg bwctrl_done_d; + reg bwctrl_done_q; + //CP signals + reg [2:0] usr_cp_current_value; + reg cp_current_changed; + reg cp_current_done_d; + reg cp_current_done_q; + //VCO signals + reg usr_vco_value; + reg vco_changed; + reg vco_done_d; + reg vco_done_q; + //Manual DPRIO signals + reg manual_dprio_done_q; + reg manual_dprio_done_d; + reg manual_dprio_changed; + reg [5:0] usr_dprio_address; + reg [15:0] usr_dprio_writedata_0; + reg usr_r_w; + //keeping track of which operation happened last + reg [5:0] operation_address; + // Address wires for all C_counter DPRIO registers + // These are outputs of LUTS, changing depending + // on whether PLL_0 or PLL_1 being used + + + //Fitter will tell if FPLL1 is being used + wire fpll_1; + + // other + reg mif_reg_asserted; + // MAIN FSM + + // Synchronize locked signal + altera_std_synchronizer #( + .depth(3) + ) altera_std_synchronizer_inst ( + .clk(mgmt_clk), + .reset_n(~mgmt_reset), + .din(locked_orig), + .dout(locked) + ); + + always @(posedge clk) + begin + if (reset) + begin + dprio_cur_state <= DPRIO_IDLE; + current_state <= IDLE; + end + else + begin + current_state <= next_state; + dprio_cur_state <= dprio_next_state; + end + end + + always @(*) + begin + case(current_state) + IDLE: + begin + if (pll_start & !slave_waitrequest & usr_valid_changes) + next_state = WAIT_ON_LOCK; + else + next_state = IDLE; + end + WAIT_ON_LOCK: + begin + if (locked & dps_done & dprio_write_done) // received locked high from PLL + begin + if (slave_mode==mode_WR) //if the mode is waitrequest, then + // goto IDLE state directly + next_state = IDLE; + else + next_state = LOCKED; //otherwise go the locked state + end + else + next_state = WAIT_ON_LOCK; + end + + LOCKED: + begin + if (status_read) // stay in LOCKED until user reads status + next_state = IDLE; + else + next_state = LOCKED; + end + + default: next_state = 2'bxx; + + endcase + end + + + // ask the pll to start reconfig + assign pll_start = (pll_start_asserted & (current_state==IDLE)) ; + assign pll_start_valid = (pll_start & (next_state==WAIT_ON_LOCK)) ; + + + + // WRITE OPERATIONS + assign pll_start_asserted = slave_write & (slave_address == START_REG); + assign mif_start_out = pll_start & mif_reg_asserted; + + //reading the mode register to determine what mode the slave will operate + //in. + always @(posedge clk) + begin + if (reset) + slave_mode <= mode_WR; + else if (slave_write & (slave_address == MODE_REG) & !slave_waitrequest) + slave_mode <= slave_writedata[0]; + end + + //record which values user wants to change. + + //reading in the actual values that need to be reconfigged and sending + //them to the PLL + always @(posedge clk) + begin + if (reset) + begin + //reset all regs here + //BW signals reset + usr_bwctrl_value <= 0; + bwctrl_changed <= 0; + bwctrl_done_q <= 0; + //CP signals reset + usr_cp_current_value <= 0; + cp_current_changed <= 0; + cp_current_done_q <= 0; + //VCO signals reset + usr_vco_value <= 0; + vco_changed <= 0; + vco_done_q <= 0; + //DSM signals reset + usr_k_value <= 0; + dsm_k_changed <= 0; + dsm_k_done_q <= 0; + //N counter signals reset + usr_n_cnt_lo <= 0; + usr_n_cnt_hi <= 0; + usr_n_cnt_bypass_en <= 0; + usr_n_cnt_odd_duty_div_en <= 0; + n_cnt_changed <= 0; + n_cnt_done_q <= 0; + //M counter signals reset + usr_m_cnt_lo <= 0; + usr_m_cnt_hi <= 0; + usr_m_cnt_bypass_en <= 0; + usr_m_cnt_odd_duty_div_en <= 0; + m_cnt_changed <= 0; + m_cnt_done_q <= 0; + //C counter signals reset + usr_c_cnt_lo <= 0; + usr_c_cnt_hi <= 0; + usr_c_cnt_bypass_en <= 0; + usr_c_cnt_odd_duty_div_en <= 0; + any_c_cnt_changed <= 0; + all_c_cnt_done_q <= 0; + c_cnt_done_q <= 0; + //generic signals + dprio_start <= 0; + mif_start_assert <= 0; + dps_start_assert <= 0; + dprio_temp_m_n_c_readdata_1_q <= 0; + dprio_temp_m_n_c_readdata_2_q <= 0; + c_cnt_done_q <= 0; + //DPS signals + usr_up_dn <= 0; + usr_cnt_sel <= 0; + usr_num_shifts <= 0; + dps_changed <= 0; + //manual DPRIO signals + manual_dprio_changed <= 0; + usr_dprio_address <= 0; + usr_dprio_writedata_0 <= 0; + usr_r_w <= 0; + operation_address <= 0; + mif_reg_asserted <= 0; + mif_base_addr <= 0; + end + else + begin + if (dprio_temp_read_1) + begin + dprio_temp_m_n_c_readdata_1_q <= dprio_temp_m_n_c_readdata_1_d; + end + if (dprio_temp_read_2) + begin + dprio_temp_m_n_c_readdata_2_q <= dprio_temp_m_n_c_readdata_2_d; + end + if ((dps_done)) dps_changed <= 0; + if (dsm_k_done_d) dsm_k_done_q <= dsm_k_done_d; + if (n_cnt_done_d) n_cnt_done_q <= n_cnt_done_d; + if (m_cnt_done_d) m_cnt_done_q <= m_cnt_done_d; + if (all_c_cnt_done_d) all_c_cnt_done_q <= all_c_cnt_done_d; + if (c_cnt_done_d != 0) c_cnt_done_q <= c_cnt_done_q | c_cnt_done_d; + if (bwctrl_done_d) bwctrl_done_q <= bwctrl_done_d; + if (cp_current_done_d) cp_current_done_q <= cp_current_done_d; + if (vco_done_d) vco_done_q <= vco_done_d; + if (manual_dprio_done_d) manual_dprio_done_q <= manual_dprio_done_d; + + if (mif_start_out == 1'b1) + mif_start_assert <= 0; // Signaled MIF block to start, so deassert on next cycle + + if (dps_done != 1'b1) + dps_start_assert <= 0; // DPS has started, so dessert its start signal on next cycle + + if (dprio_next_state == ONE) + dprio_start <= 0; + if (dprio_write_done) + begin + bwctrl_done_q <= 0; + cp_current_done_q <= 0; + vco_done_q <= 0; + dsm_k_done_q <= 0; + dsm_k_done_q <= 0; + n_cnt_done_q <= 0; + m_cnt_done_q <= 0; + all_c_cnt_done_q <= 0; + c_cnt_done_q <= 0; + dsm_k_changed <= 0; + n_cnt_changed <= 0; + m_cnt_changed <= 0; + any_c_cnt_changed <= 0; + bwctrl_changed <= 0; + cp_current_changed <= 0; + vco_changed <= 0; + manual_dprio_changed <= 0; + manual_dprio_done_q <= 0; + if (dps_changed | dps_changed_valid | !dps_done ) + begin + usr_cnt_sel <= usr_cnt_sel; + end + else + begin + usr_cnt_sel <= 0; + end + mif_reg_asserted <= 0; + end + else + begin + dsm_k_changed <= dsm_k_changed; + n_cnt_changed <= n_cnt_changed; + m_cnt_changed <= m_cnt_changed; + any_c_cnt_changed <= any_c_cnt_changed; + manual_dprio_changed <= manual_dprio_changed; + mif_reg_asserted <= mif_reg_asserted; + usr_cnt_sel <= usr_cnt_sel; + end + + + if(slave_write & !slave_waitrequest) + begin + case(slave_address) + //read in the values here from the user and act on them + DSM_REG: + begin + operation_address <= DSM_REG; + usr_k_value <= slave_writedata[31:0]; + dsm_k_changed <= 1'b1; + dsm_k_done_q <= 0; + dprio_start <= 1'b1; + end + N_REG: + begin + operation_address <= N_REG; + usr_n_cnt_lo <= slave_writedata[7:0]; + usr_n_cnt_hi <= slave_writedata[15:8]; + usr_n_cnt_bypass_en <= slave_writedata[16]; + usr_n_cnt_odd_duty_div_en <= slave_writedata[17]; + n_cnt_changed <= 1'b1; + n_cnt_done_q <= 0; + dprio_start <= 1'b1; + end + M_REG: + begin + operation_address <= M_REG; + usr_m_cnt_lo <= slave_writedata[7:0]; + usr_m_cnt_hi <= slave_writedata[15:8]; + usr_m_cnt_bypass_en <= slave_writedata[16]; + usr_m_cnt_odd_duty_div_en <= slave_writedata[17]; + m_cnt_changed <= 1'b1; + m_cnt_done_q <= 0; + dprio_start <= 1'b1; + end + DPS_REG: + begin + operation_address <= DPS_REG; + usr_num_shifts <= slave_writedata[15:0]; + usr_cnt_sel <= slave_writedata[20:16]; + usr_up_dn <= slave_writedata[21]; + dps_changed <= 1; + dps_start_assert <= 1; + end + C_COUNTERS_REG: + begin + operation_address <= C_COUNTERS_REG; + usr_c_cnt_lo <= slave_writedata[7:0]; + usr_c_cnt_hi <= slave_writedata[15:8]; + usr_c_cnt_bypass_en <= slave_writedata[16]; + usr_c_cnt_odd_duty_div_en <= slave_writedata[17]; + usr_cnt_sel <= slave_writedata[22:18]; + any_c_cnt_changed <= 1'b1; + all_c_cnt_done_q <= 0; + dprio_start <= 1'b1; + end + BWCTRL_REG: + begin + usr_bwctrl_value <= slave_writedata[3:0]; + bwctrl_changed <= 1'b1; + bwctrl_done_q <= 0; + dprio_start <= 1'b1; + operation_address <= BWCTRL_REG; + end + CP_CURRENT_REG: + begin + usr_cp_current_value <= slave_writedata[2:0]; + cp_current_changed <= 1'b1; + cp_current_done_q <= 0; + dprio_start <= 1'b1; + operation_address <= CP_CURRENT_REG; + end + VCO_REG: + begin + usr_vco_value <= slave_writedata[0]; + vco_changed <= 1'b1; + vco_done_q <= 0; + dprio_start <= 1'b1; + operation_address <= VCO_REG; + end + ANY_DPRIO: + begin + operation_address <= ANY_DPRIO; + manual_dprio_changed <= 1'b1; + usr_dprio_address <= slave_writedata[5:0]; + usr_dprio_writedata_0 <= slave_writedata[21:6]; + usr_r_w <= slave_writedata[22]; + manual_dprio_done_q <= 0; + dprio_start <= 1'b1; + end + MIF_REG: + begin + mif_reg_asserted <= 1'b1; + mif_base_addr <= slave_writedata[ROM_ADDR_WIDTH-1:0]; + mif_start_assert <= 1'b1; + end + endcase + end + end + end + //C Counter assigning values to the 2-d array of values for each C counter + + reg [4:0] j; + always @(posedge clk) + begin + + if (reset) + begin + c_cnt_changed[17:0] <= 0; + for (j = 0; j < number_of_counters; j = j + 1'b1) + begin : c_cnt_reset + temp_c_cnt_bypass_en[j] <= 0; + temp_c_cnt_odd_duty_div_en[j] <= 0; + temp_c_cnt_lo[j][7:0] <= 0; + temp_c_cnt_hi[j][7:0] <= 0; + end + end + else + begin + if (dprio_write_done) + begin + c_cnt_changed <= 0; + end + if (any_c_cnt_changed && (operation_address == C_COUNTERS_REG)) + begin + case (cnt_sel) + CNT_0: + begin + temp_c_cnt_lo [0] <= usr_c_cnt_lo; + temp_c_cnt_hi [0] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [0] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [0] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [0] <= 1'b1; + end + CNT_1: + begin + temp_c_cnt_lo [1] <= usr_c_cnt_lo; + temp_c_cnt_hi [1] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [1] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [1] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [1] <= 1'b1; + end + CNT_2: + begin + temp_c_cnt_lo [2] <= usr_c_cnt_lo; + temp_c_cnt_hi [2] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [2] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [2] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [2] <= 1'b1; + end + CNT_3: + begin + temp_c_cnt_lo [3] <= usr_c_cnt_lo; + temp_c_cnt_hi [3] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [3] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [3] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [3] <= 1'b1; + end + CNT_4: + begin + temp_c_cnt_lo [4] <= usr_c_cnt_lo; + temp_c_cnt_hi [4] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [4] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [4] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [4] <= 1'b1; + end + CNT_5: + begin + temp_c_cnt_lo [5] <= usr_c_cnt_lo; + temp_c_cnt_hi [5] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [5] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [5] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [5] <= 1'b1; + end + CNT_6: + begin + temp_c_cnt_lo [6] <= usr_c_cnt_lo; + temp_c_cnt_hi [6] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [6] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [6] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [6] <= 1'b1; + end + CNT_7: + begin + temp_c_cnt_lo [7] <= usr_c_cnt_lo; + temp_c_cnt_hi [7] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [7] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [7] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [7] <= 1'b1; + end + CNT_8: + begin + temp_c_cnt_lo [8] <= usr_c_cnt_lo; + temp_c_cnt_hi [8] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [8] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [8] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [8] <= 1'b1; + end + CNT_9: + begin + temp_c_cnt_lo [9] <= usr_c_cnt_lo; + temp_c_cnt_hi [9] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [9] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [9] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [9] <= 1'b1; + end + CNT_10: + begin + temp_c_cnt_lo [10] <= usr_c_cnt_lo; + temp_c_cnt_hi [10] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [10] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [10] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [10] <= 1'b1; + end + CNT_11: + begin + temp_c_cnt_lo [11] <= usr_c_cnt_lo; + temp_c_cnt_hi [11] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [11] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [11] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [11] <= 1'b1; + end + CNT_12: + begin + temp_c_cnt_lo [12] <= usr_c_cnt_lo; + temp_c_cnt_hi [12] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [12] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [12] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [12] <= 1'b1; + end + CNT_13: + begin + temp_c_cnt_lo [13] <= usr_c_cnt_lo; + temp_c_cnt_hi [13] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [13] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [13] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [13] <= 1'b1; + end + CNT_14: + begin + temp_c_cnt_lo [14] <= usr_c_cnt_lo; + temp_c_cnt_hi [14] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [14] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [14] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [14] <= 1'b1; + end + CNT_15: + begin + temp_c_cnt_lo [15] <= usr_c_cnt_lo; + temp_c_cnt_hi [15] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [15] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [15] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [15] <= 1'b1; + end + CNT_16: + begin + temp_c_cnt_lo [16] <= usr_c_cnt_lo; + temp_c_cnt_hi [16] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [16] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [16] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [16] <= 1'b1; + end + CNT_17: + begin + temp_c_cnt_lo [17] <= usr_c_cnt_lo; + temp_c_cnt_hi [17] <= usr_c_cnt_hi; + temp_c_cnt_bypass_en [17] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [17] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [17] <= 1'b1; + end + endcase + + end + end + end + + + //logic to handle which writes the user indicated and wants to start. + assign usr_valid_changes =dsm_k_changed| any_c_cnt_changed |n_cnt_changed | m_cnt_changed | dps_changed_valid |manual_dprio_changed |cp_current_changed|bwctrl_changed|vco_changed; + + + //start the reconfig operations by writing to the DPRIO + reg break_loop; + reg [4:0] i; + always @(*) + begin + dprio_temp_read_1 = 0; + dprio_temp_read_2 = 0; + dprio_temp_m_n_c_readdata_1_d = 0; + dprio_temp_m_n_c_readdata_2_d = 0; + break_loop = 0; + dprio_next_state = DPRIO_IDLE; + avmm_dprio_write = 0; + avmm_dprio_read = 0; + avmm_dprio_address = 0; + avmm_dprio_writedata = 0; + avmm_dprio_byteen = 0; + dprio_write_done = 1; + manual_dprio_done_d = 0; + n_cnt_done_d = 0; + dsm_k_done_d = 0; + dsm_k_ready_false_done_d = 0; + m_cnt_done_d = 0; + c_cnt_done_d[17:0] = 0; + all_c_cnt_done_d = 0; + bwctrl_done_d = 0; + cp_current_done_d = 0; + vco_done_d = 0; + i = 0; + + // Deassert dprio_write_done so it doesn't reset mif_reg_asserted (toggled writes) + if (dprio_start | mif_start_assert) + dprio_write_done = 0; + + if (current_state == WAIT_ON_LOCK) + begin + case (dprio_cur_state) + ONE: + begin + if (n_cnt_changed & !n_cnt_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + dprio_next_state = TWO; + avmm_dprio_address = N_CNT_DIV_ADDR; + avmm_dprio_writedata[7:0] = usr_n_cnt_lo; + avmm_dprio_writedata[15:8] = usr_n_cnt_hi; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + dprio_next_state = TWO; + avmm_dprio_address = M_CNT_DIV_ADDR; + avmm_dprio_writedata[7:0] = usr_m_cnt_lo; + avmm_dprio_writedata[15:8] = usr_m_cnt_hi; + end + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + + for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_write_hilo + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + dprio_write_done = 0; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + dprio_next_state = TWO; + if (fpll_1) avmm_dprio_address = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - i; + else avmm_dprio_address = C_CNT_0_DIV_ADDR + i; + avmm_dprio_writedata[7:0] = temp_c_cnt_lo[i]; + avmm_dprio_writedata[15:8] = temp_c_cnt_hi[i]; + //To break from the loop, since only one counter + //is addressed at a time + break_loop = 1'b1; + end + end + end + else if (dsm_k_changed & !dsm_k_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 0; + dprio_next_state = TWO; + end + else if (bwctrl_changed & !bwctrl_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 0; + dprio_next_state = TWO; + end + else if (cp_current_changed & !cp_current_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 0; + dprio_next_state = TWO; + end + else if (vco_changed & !vco_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 0; + dprio_next_state = TWO; + end + else if (manual_dprio_changed & !manual_dprio_done_q) + begin + dprio_write_done = 0; + avmm_dprio_byteen = 2'b11; + dprio_next_state = TWO; + avmm_dprio_write = usr_r_w; + avmm_dprio_address = usr_dprio_address; + avmm_dprio_writedata[15:0] = usr_dprio_writedata_0; + end + else dprio_next_state = DPRIO_IDLE; + end + + TWO: + begin + //handle reading the two setting bits on n_cnt, then + //writing them back while preserving other bits. + //Issue two consecutive reads then wait; readLatency=3 + dprio_write_done = 0; + dprio_next_state = THREE; + avmm_dprio_byteen = 2'b11; + avmm_dprio_read = 1'b1; + if (n_cnt_changed & !n_cnt_done_q) + begin + avmm_dprio_address = N_CNT_BYPASS_EN_ADDR; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + avmm_dprio_address = M_CNT_BYPASS_EN_ADDR; + end + + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_read_bypass + if (fpll_1) + begin + if (i > 13) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; + break_loop = 1'b1; + end + end + end + else + begin + if (i < 4) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; + break_loop = 1'b1; + end + end + end + end + end + //reading the K ready 16 bit word. Need to write 0 to it + //afterwards to indicate that K has not been done writing + else if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_READY_ADDR; + dprio_next_state = FOUR; + end + else if (bwctrl_changed & !bwctrl_done_q) + begin + avmm_dprio_address = BWCTRL_ADDR; + dprio_next_state = FOUR; + end + else if (cp_current_changed & !cp_current_done_q) + begin + avmm_dprio_address = CP_CURRENT_ADDR; + dprio_next_state = FOUR; + end + else if (vco_changed & !vco_done_q) + begin + avmm_dprio_address = VCO_ADDR; + dprio_next_state = FOUR; + end + else if (manual_dprio_changed & !manual_dprio_done_q) + begin + avmm_dprio_read = ~usr_r_w; + avmm_dprio_address = usr_dprio_address; + dprio_next_state = DPRIO_DONE; + end + else dprio_next_state = DPRIO_IDLE; + end + THREE: + begin + dprio_write_done = 0; + avmm_dprio_byteen = 2'b11; + avmm_dprio_read = 1'b1; + dprio_next_state = FOUR; + if (n_cnt_changed & !n_cnt_done_q) + begin + avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR; + end + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_read_odd_div + if (fpll_1) + begin + if (i > 13) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; + break_loop = 1'b1; + end + end + end + else + begin + if (i < 4) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; + break_loop = 1'b1; + end + end + end + end + end + else dprio_next_state = DPRIO_IDLE; + end + FOUR: + begin + dprio_temp_read_1 = 1'b1; + dprio_write_done = 0; + if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed) + begin + dprio_temp_m_n_c_readdata_1_d = dprio_readdata; + dprio_next_state = FIVE; + end + else dprio_next_state = DPRIO_IDLE; + end + FIVE: + begin + dprio_write_done = 0; + dprio_temp_read_2 = 1'b1; + if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed) + begin + //this is where DSM ready value comes. + //Need to store in a register to be used later + dprio_temp_m_n_c_readdata_2_d = dprio_readdata; + dprio_next_state = SIX; + end + else dprio_next_state = DPRIO_IDLE; + end + SIX: + begin + dprio_write_done = 0; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + dprio_next_state = SEVEN; + avmm_dprio_writedata = dprio_temp_m_n_c_readdata_1_q; + if (n_cnt_changed & !n_cnt_done_q) + begin + avmm_dprio_address = N_CNT_BYPASS_EN_ADDR; + avmm_dprio_writedata[5] = usr_n_cnt_bypass_en; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + avmm_dprio_address = M_CNT_BYPASS_EN_ADDR; + avmm_dprio_writedata[4] = usr_m_cnt_bypass_en; + end + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_write_bypass + if (fpll_1) + begin + if (i > 13) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; + avmm_dprio_writedata[i-14] = temp_c_cnt_bypass_en[i]; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; + avmm_dprio_writedata[i] = temp_c_cnt_bypass_en[i]; + break_loop = 1'b1; + end + end + end + else + begin + if (i < 4) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; + avmm_dprio_writedata[3-i] = temp_c_cnt_bypass_en[i]; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; + avmm_dprio_writedata[17-i] = temp_c_cnt_bypass_en[i]; + break_loop = 1'b1; + end + end + end + end + end + else if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_write = 0; + end + else if (bwctrl_changed & !bwctrl_done_q) + begin + avmm_dprio_write = 0; + end + else if (cp_current_changed & !cp_current_done_q) + begin + avmm_dprio_write = 0; + end + else if (vco_changed & !vco_done_q) + begin + avmm_dprio_write = 0; + end + else dprio_next_state = DPRIO_IDLE; + end + SEVEN: + begin + dprio_write_done = 0; + dprio_next_state = EIGHT; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q; + if (n_cnt_changed & !n_cnt_done_q) + begin + avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[5] = usr_n_cnt_odd_duty_div_en; + n_cnt_done_d = 1'b1; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[4] = usr_m_cnt_odd_duty_div_en; + m_cnt_done_d = 1'b1; + end + + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_write_odd_div + if (fpll_1) + begin + if (i > 13) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[i-14] = temp_c_cnt_odd_duty_div_en[i]; + c_cnt_done_d[i] = 1'b1; + //have to OR the signals to prevent + //overwriting of previous dones + c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[i] = temp_c_cnt_odd_duty_div_en[i]; + c_cnt_done_d[i] = 1'b1; + c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; + break_loop = 1'b1; + end + end + end + else + begin + if (i < 4) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[3-i] = temp_c_cnt_odd_duty_div_en[i]; + c_cnt_done_d[i] = 1'b1; + //have to OR the signals to prevent + //overwriting of previous dones + c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[17-i] = temp_c_cnt_odd_duty_div_en[i]; + c_cnt_done_d[i] = 1'b1; + c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; + break_loop = 1'b1; + end + end + end + end + end + else if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_READY_ADDR; + avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b0; + dsm_k_ready_false_done_d = 1'b1; + end + else if (bwctrl_changed & !bwctrl_done_q) + begin + avmm_dprio_address = BWCTRL_ADDR; + avmm_dprio_writedata[3:0] = usr_bwctrl_value; + bwctrl_done_d = 1'b1; + end + else if (cp_current_changed & !cp_current_done_q) + begin + avmm_dprio_address = CP_CURRENT_ADDR; + avmm_dprio_writedata[2:0] = usr_cp_current_value; + cp_current_done_d = 1'b1; + end + else if (vco_changed & !vco_done_q) + begin + avmm_dprio_address = VCO_ADDR; + avmm_dprio_writedata[8] = usr_vco_value; + vco_done_d = 1'b1; + end + + + //if all C_cnt that were changed are done, then assert all_c_cnt_done + if (c_cnt_done_d == c_cnt_changed) + all_c_cnt_done_d = 1'b1; + if (n_cnt_changed & n_cnt_done_d) + dprio_next_state = DPRIO_DONE; + if (any_c_cnt_changed & !all_c_cnt_done_d & !all_c_cnt_done_q) + dprio_next_state = ONE; + else if (m_cnt_changed & !m_cnt_done_d & !m_cnt_done_q) + dprio_next_state = ONE; + else if (dsm_k_changed & !dsm_k_ready_false_done_d) + dprio_next_state = TWO; + else if (dsm_k_changed & !dsm_k_done_q) + dprio_next_state = EIGHT; + else if (bwctrl_changed & !bwctrl_done_d) + dprio_next_state = TWO; + else if (cp_current_changed & !cp_current_done_d) + dprio_next_state = TWO; + else if (vco_changed & !vco_done_d) + dprio_next_state = TWO; + else + begin + dprio_next_state = DPRIO_DONE; + dprio_write_done = 1'b1; + end + end + //finish the rest of the DSM reads/writes + //writing k value, writing k_ready to 1. + EIGHT: + begin + dprio_write_done = 0; + dprio_next_state = NINE; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_0; + avmm_dprio_writedata[15:0] = usr_k_value[15:0]; + end + end + NINE: + begin + dprio_write_done = 0; + dprio_next_state = TEN; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_1; + avmm_dprio_writedata[15:0] = usr_k_value[31:16]; + end + end + TEN: + begin + dprio_write_done = 0; + dprio_next_state = ONE; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_READY_ADDR; + //already have the readdata for DSM_K_READY_ADDR since we read it + //earlier. Just reuse here + avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q; + avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b1; + dsm_k_done_d = 1'b1; + end + end + DPRIO_DONE: + begin + dprio_write_done = 1'b1; + if (dprio_start) dprio_next_state = DPRIO_IDLE; + else dprio_next_state = DPRIO_DONE; + end + DPRIO_IDLE: + begin + if (dprio_start) dprio_next_state = ONE; + else dprio_next_state = DPRIO_IDLE; + end + default: dprio_next_state = 4'bxxxx; + endcase + end + + end + + + //assert the waitreq signal according to the state of the slave + assign slave_waitrequest = (slave_mode==mode_WR) ? ((locked === 1'b1) ? (((current_state==WAIT_ON_LOCK) & !dprio_write_done) | !dps_done |reset|!dprio_init_done) : 1'b1) : 1'b0; + + // Read operations + always @(*) + begin + status = 0; + if (slave_mode == mode_POLL) + //asserting status to 1 if the slave is done. + status = (current_state == LOCKED); + end + //************************************************************// + //************************************************************// + //******************** READ STATE MACHINE ********************// + //************************************************************// + //************************************************************// + reg [1:0] current_read_state; + reg [1:0] next_read_state; + reg [5:0] slave_address_int_d; + reg [5:0] slave_address_int_q; + reg dprio_read_1; + reg [5:0] dprio_address_1; + reg [1:0] dprio_byteen_1; + reg [4:0] usr_cnt_sel_1; + localparam READ = 2'b00, READ_WAIT = 2'b01, READ_IDLE = 2'b10, READ_POST_WAIT = 2'b11; + + always @(*) + begin + if(next_read_state == READ_IDLE) + begin + read_waitrequest <= 1'b0; + end + else + begin + read_waitrequest <= 1'b1; + end + end + + always @(posedge clk) + begin + if (reset) + begin + current_read_state <= READ_IDLE; + slave_address_int_q <= 0; + slave_readdata_q <= 0; + end + else + begin + current_read_state <= next_read_state; + slave_address_int_q <= slave_address_int_d; + slave_readdata_q <= slave_readdata_d; + end + end + always @(*) + begin + dprio_read_1 = 0; + dprio_address_1 = 0; + dprio_byteen_1 = 0; + slave_address_int_d = 0; + slave_readdata_d = 0; + status_read = 0; + usr_cnt_sel_1 = 0; + case(current_read_state) + READ_IDLE: + begin + slave_address_int_d = 0; + next_read_state = READ_IDLE; + if ((current_state != WAIT_ON_LOCK) && slave_read) + begin + slave_address_int_d = slave_address; + if ((slave_address >= CNT_BASE) && (slave_address < CNT_BASE+18)) + begin + next_read_state = READ_WAIT; + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + usr_cnt_sel_1 = (slave_address[4:0] - CNT_BASE); + if (fpll_1) dprio_address_1 = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - cnt_sel; + else dprio_address_1 = C_CNT_0_DIV_ADDR + cnt_sel; + end + else + begin + case (slave_address) + MODE_REG: + begin + next_read_state = READ_WAIT; + slave_readdata_d = slave_mode; + end + STATUS_REG: + begin + next_read_state = READ_WAIT; + status_read = 1'b1; + slave_readdata_d = status; + end + N_REG: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + dprio_address_1 = N_CNT_DIV_ADDR; + next_read_state = READ_WAIT; + end + M_REG: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + dprio_address_1 = M_CNT_DIV_ADDR; + next_read_state = READ_WAIT; + end + BWCTRL_REG: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + dprio_address_1 = BWCTRL_ADDR; + next_read_state = READ_WAIT; + end + CP_CURRENT_REG: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + dprio_address_1 = CP_CURRENT_ADDR; + next_read_state = READ_WAIT; + end + VCO_REG: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = 1'b1; + dprio_address_1 = VCO_ADDR; + next_read_state = READ_WAIT; + end + ANY_DPRIO: + begin + dprio_byteen_1 = 2'b11; + dprio_read_1 = ~slave_writedata[22]; + dprio_address_1 = slave_writedata[5:0]; + next_read_state = READ_WAIT; + end + default : next_read_state = READ_IDLE; + endcase + end + end + else + next_read_state = READ_IDLE; + end + READ_WAIT: + begin + next_read_state = READ; + slave_address_int_d = slave_address_int_q; + case (slave_address_int_q) + MODE_REG: + begin + slave_readdata_d = slave_readdata_q; + end + STATUS_REG: + begin + slave_readdata_d = slave_readdata_q; + end + endcase + end + READ: + begin + next_read_state = READ_POST_WAIT; + slave_address_int_d = slave_address_int_q; + slave_readdata_d = dprio_readdata; + case (slave_address_int_q) + MODE_REG: + begin + slave_readdata_d = slave_readdata_q; + end + STATUS_REG: + begin + slave_readdata_d = slave_readdata_q; + end + BWCTRL_REG: + begin + slave_readdata_d = dprio_readdata[3:0]; + end + CP_CURRENT_REG: + begin + slave_readdata_d = dprio_readdata[2:0]; + end + VCO_REG: + begin + slave_readdata_d = dprio_readdata[8]; + end + ANY_DPRIO: + begin + slave_readdata_d = dprio_readdata; + end + endcase + end + READ_POST_WAIT: + begin + next_read_state = READ_IDLE; + end + default: next_read_state = 2'bxx; + endcase + end + + + dyn_phase_shift dyn_phase_shift_inst ( + .clk(clk), + .reset(reset), + .phase_done(phase_done), + .pll_start_valid(pll_start_valid), + .dps_changed(dps_changed), + .dps_changed_valid(dps_changed_valid), + .dprio_write_done(dprio_write_done), + .usr_num_shifts(usr_num_shifts), + .usr_cnt_sel(usr_cnt_sel|usr_cnt_sel_1), + .usr_up_dn(usr_up_dn), + .locked(locked), + .dps_done(dps_done), + .phase_en(phase_en), + .up_dn(up_dn), + .cnt_sel(cnt_sel)); + defparam dyn_phase_shift_inst.device_family = device_family; + + assign dprio_clk = clk; + self_reset self_reset_inst (mgmt_reset, clk, reset, dprio_init_reset); + + dprio_mux dprio_mux_inst ( + .init_dprio_address(init_dprio_address), + .init_dprio_read(init_dprio_read), + .init_dprio_byteen(init_dprio_byteen), + .init_dprio_write(init_dprio_write), + .init_dprio_writedata(init_dprio_writedata), + + + .init_atpgmode(init_atpgmode), + .init_mdio_dis(init_mdio_dis), + .init_scanen(init_scanen), + .init_ser_shift_load(init_ser_shift_load), + .dprio_init_done(dprio_init_done), + + // Inputs from avmm master + .avmm_dprio_address(avmm_dprio_address | dprio_address_1), + .avmm_dprio_read(avmm_dprio_read | dprio_read_1), + .avmm_dprio_byteen(avmm_dprio_byteen | dprio_byteen_1), + .avmm_dprio_write(avmm_dprio_write), + .avmm_dprio_writedata(avmm_dprio_writedata), + + .avmm_atpgmode(avmm_atpgmode), + .avmm_mdio_dis(avmm_mdio_dis), + .avmm_scanen(avmm_scanen), + + // Outputs to fpll + .dprio_address(dprio_address), + .dprio_read(dprio_read), + .dprio_byteen(dprio_byteen), + .dprio_write(dprio_write), + .dprio_writedata(dprio_writedata), + + .atpgmode(dprio_atpgmode), + .mdio_dis(dprio_mdio_dis), + .scanen(dprio_scanen), + .ser_shift_load(dprio_ser_shift_load) + ); + + + fpll_dprio_init fpll_dprio_init_inst ( + .clk(clk), + .reset_n(~reset), + .locked(locked), + + //outputs + .dprio_address(init_dprio_address), + .dprio_read(init_dprio_read), + .dprio_byteen(init_dprio_byteen), + .dprio_write(init_dprio_write), + .dprio_writedata(init_dprio_writedata), + + .atpgmode(init_atpgmode), + .mdio_dis(init_mdio_dis), + .scanen(init_scanen), + .ser_shift_load(init_ser_shift_load), + .dprio_init_done(dprio_init_done)); + + //address luts, to be reconfigged by the Fitter + //FPLL_1 or 0 address lut + generic_lcell_comb lcell_fpll_0_1 ( + .dataa(1'b0), + .combout (fpll_1)); + defparam lcell_fpll_0_1.lut_mask = 64'hAAAAAAAAAAAAAAAA; + defparam lcell_fpll_0_1.dont_touch = "on"; + defparam lcell_fpll_0_1.family = device_family; + + + wire dprio_read_combout; + generic_lcell_comb lcell_dprio_read ( + .dataa(fpll_1), + .datab(dprio_read), + .datac(1'b0), + .datad(1'b0), + .datae(1'b0), + .dataf(1'b0), + .combout (dprio_read_combout)); + defparam lcell_dprio_read.lut_mask = 64'hCCCCCCCCCCCCCCCC; + defparam lcell_dprio_read.dont_touch = "on"; + defparam lcell_dprio_read.family = device_family; + + + + + + //assign reconfig_to_pll signals + assign reconfig_to_pll[0] = dprio_clk; + assign reconfig_to_pll[1] = ~dprio_init_reset; + assign reconfig_to_pll[2] = dprio_write; + assign reconfig_to_pll[3] = dprio_read_combout; + assign reconfig_to_pll[9:4] = dprio_address; + assign reconfig_to_pll[25:10] = dprio_writedata; + assign reconfig_to_pll[27:26] = dprio_byteen; + assign reconfig_to_pll[28] = dprio_ser_shift_load; + assign reconfig_to_pll[29] = dprio_mdio_dis; + assign reconfig_to_pll[30] = phase_en; + assign reconfig_to_pll[31] = up_dn; + assign reconfig_to_pll[36:32] = cnt_sel; + assign reconfig_to_pll[37] = dprio_scanen; + assign reconfig_to_pll[38] = dprio_atpgmode; + //assign reconfig_to_pll[40:37] = clken; + assign reconfig_to_pll[63:39] = 0; + + //assign reconfig_from_pll signals + assign dprio_readdata = reconfig_from_pll [15:0]; + assign locked_orig = reconfig_from_pll [16]; + assign phase_done = reconfig_from_pll [17]; + +endmodule +module self_reset (input wire mgmt_reset, input wire clk, output wire reset, output wire init_reset); + + localparam RESET_COUNTER_VALUE = 3'd2; + localparam INITIAL_WAIT_VALUE = 9'd340; + reg [9:0]counter; + reg local_reset; + reg usr_mode_init_wait; + initial + begin + local_reset = 1'b1; + counter = 0; + usr_mode_init_wait = 0; + end + + always @(posedge clk) + begin + if (mgmt_reset) + begin + counter <= 0; + end + else + begin + if (!usr_mode_init_wait) + begin + if (counter == INITIAL_WAIT_VALUE) + begin + local_reset <= 0; + usr_mode_init_wait <= 1'b1; + counter <= 0; + end + else + begin + counter <= counter + 1'b1; + end + end + else + begin + if (counter == RESET_COUNTER_VALUE) + local_reset <= 0; + else + counter <= counter + 1'b1; + end + end + end + assign reset = mgmt_reset | local_reset; + assign init_reset = local_reset; +endmodule + +module dprio_mux ( + // Inputs from init block + input [ 5:0] init_dprio_address, + input init_dprio_read, + input [ 1:0] init_dprio_byteen, + input init_dprio_write, + input [15:0] init_dprio_writedata, + + input init_atpgmode, + input init_mdio_dis, + input init_scanen, + input init_ser_shift_load, + input dprio_init_done, + + // Inputs from avmm master + input [ 5:0] avmm_dprio_address, + input avmm_dprio_read, + input [ 1:0] avmm_dprio_byteen, + input avmm_dprio_write, + input [15:0] avmm_dprio_writedata, + + input avmm_atpgmode, + input avmm_mdio_dis, + input avmm_scanen, + input avmm_ser_shift_load, + + // Outputs to fpll + output [ 5:0] dprio_address, + output dprio_read, + output [ 1:0] dprio_byteen, + output dprio_write, + output [15:0] dprio_writedata, + + output atpgmode, + output mdio_dis, + output scanen, + output ser_shift_load +); + + assign dprio_address = dprio_init_done ? avmm_dprio_address : init_dprio_address; + assign dprio_read = dprio_init_done ? avmm_dprio_read : init_dprio_read; + assign dprio_byteen = dprio_init_done ? avmm_dprio_byteen : init_dprio_byteen; + assign dprio_write = dprio_init_done ? avmm_dprio_write : init_dprio_write; + assign dprio_writedata = dprio_init_done ? avmm_dprio_writedata : init_dprio_writedata; + + assign atpgmode = init_atpgmode; + assign scanen = init_scanen; + assign mdio_dis = init_mdio_dis; + assign ser_shift_load = init_ser_shift_load ; +endmodule +module fpll_dprio_init ( + input clk, + input reset_n, + input locked, + + output [ 5:0] dprio_address, + output dprio_read, + output [ 1:0] dprio_byteen, + output dprio_write, + output [15:0] dprio_writedata, + + output reg atpgmode, + output reg mdio_dis, + output reg scanen, + output reg ser_shift_load, + output reg dprio_init_done +); + + reg [1:0] rst_n = 2'b00; + reg [6:0] count = 7'd0; + reg init_done_forever; + + // Internal versions of control signals + wire int_mdio_dis; + wire int_ser_shift_load; + wire int_dprio_init_done; + wire int_atpgmode/*synthesis keep*/; + wire int_scanen/*synthesis keep*/; + + + assign dprio_address = count[6] ? 5'b0 : count[5:0] ; + assign dprio_byteen = 2'b11; // always enabled + assign dprio_write = ~count[6] & reset_n ; // write for first 64 cycles + assign dprio_read = 1'b0; + assign dprio_writedata = 16'd0; + + assign int_ser_shift_load = count[6] ? |count[2:1] : 1'b1; + assign int_mdio_dis = count[6] ? ~count[2] : 1'b1; + assign int_dprio_init_done = ~init_done_forever ? (count[6] ? &count[2:0] : 1'b0) + : 1'b1; + assign int_atpgmode = 0; + assign int_scanen = 0; + + initial begin + count = 7'd0; + init_done_forever = 0; + mdio_dis = 1'b1; + ser_shift_load = 1'b1; + dprio_init_done = 1'b0; + scanen = 1'b0; + atpgmode = 1'b0; + end + + // reset synch. + always @(posedge clk or negedge reset_n) + if(!reset_n) rst_n <= 2'b00; + else rst_n <= {rst_n[0],1'b1}; + + // counter + always @(posedge clk) + begin + if (!rst_n[1]) + init_done_forever <= 1'b0; + else + begin + if (count[6] && &count[1:0]) + init_done_forever <= 1'b1; + end + end + always @(posedge clk or negedge rst_n[1]) + begin + if(!rst_n[1]) + begin + count <= 7'd0; + end + else if(~int_dprio_init_done) + begin + count <= count + 7'd1; + end + else + begin + count <= count; + end + end + + // outputs + always @(posedge clk) begin + mdio_dis <= int_mdio_dis; + ser_shift_load <= int_ser_shift_load; + dprio_init_done <= int_dprio_init_done; + atpgmode <= int_atpgmode; + scanen <= int_scanen; + end + +endmodule +module dyn_phase_shift +#( + parameter device_family = "Cyclone V" +) ( + + input wire clk, + input wire reset, + input wire phase_done, + input wire pll_start_valid, + input wire dps_changed, + input wire dprio_write_done, + input wire [15:0] usr_num_shifts, + input wire [4:0] usr_cnt_sel, + input wire usr_up_dn, + input wire locked, + + //output + output wire dps_done, + output reg phase_en, + output wire up_dn, + output wire dps_changed_valid, + output wire [4:0] cnt_sel); + + + + reg first_phase_shift_d; + reg first_phase_shift_q; + reg [15:0] phase_en_counter; + reg [3:0] dps_current_state; + reg [3:0] dps_next_state; + localparam DPS_START = 4'd0, DPS_WAIT_PHASE_DONE = 4'd1, DPS_DONE = 4'd2, DPS_WAIT_PHASE_EN = 4'd3, DPS_WAIT_DPRIO_WRITING = 4'd4, DPS_CHANGED = 4'd5; + localparam PHASE_EN_WAIT_COUNTER = 5'd1; + + reg [15:0] shifts_done_counter; + reg phase_done_final; + wire gnd /*synthesis keep*/; + + //fsm + //always block controlling the state regs + always @(posedge clk) + begin + if (reset) + begin + dps_current_state <= DPS_DONE; + end + else + begin + dps_current_state <= dps_next_state; + end + end + //the combinational part. assigning the next state + //this turns on the phase_done_final signal when phase_done does this: + //_____ ______ + // |______| + always @(*) + begin + phase_done_final = 0; + first_phase_shift_d = 0; + phase_en = 0; + dps_next_state = DPS_DONE; + case (dps_current_state) + DPS_START: + begin + phase_en = 1'b1; + dps_next_state = DPS_WAIT_PHASE_EN; + end + DPS_WAIT_PHASE_EN: + begin + phase_en = 1'b1; + if (first_phase_shift_q) + begin + first_phase_shift_d = 1'b1; + dps_next_state = DPS_WAIT_PHASE_EN; + end + else + begin + if (phase_en_counter == PHASE_EN_WAIT_COUNTER) + dps_next_state = DPS_WAIT_PHASE_DONE; + else dps_next_state = DPS_WAIT_PHASE_EN; + end + end + DPS_WAIT_PHASE_DONE: + begin + if (!phase_done | !locked) + begin + dps_next_state = DPS_WAIT_PHASE_DONE; + end + else + begin + if ((usr_num_shifts != shifts_done_counter) & (usr_num_shifts != 0)) + begin + dps_next_state = DPS_START; + phase_done_final = 1'b1; + end + else + begin + dps_next_state = DPS_DONE; + end + + end + end + DPS_DONE: + begin + phase_done_final = 0; + if (dps_changed) + dps_next_state = DPS_CHANGED; + else dps_next_state = DPS_DONE; + + end + DPS_CHANGED: + begin + if (pll_start_valid) + dps_next_state = DPS_WAIT_DPRIO_WRITING; + else + dps_next_state = DPS_CHANGED; + end + DPS_WAIT_DPRIO_WRITING: + begin + if (dprio_write_done) + dps_next_state = DPS_START; + else + dps_next_state = DPS_WAIT_DPRIO_WRITING; + end + + default: dps_next_state = 4'bxxxx; + endcase + + + end + + always @(posedge clk) + begin + + + if (dps_current_state == DPS_WAIT_PHASE_DONE) + phase_en_counter <= 0; + else if (dps_current_state == DPS_WAIT_PHASE_EN) + phase_en_counter <= phase_en_counter + 1'b1; + + if (reset) + begin + phase_en_counter <= 0; + shifts_done_counter <= 1'b1; + first_phase_shift_q <= 1; + end + else + begin + if (first_phase_shift_d) + first_phase_shift_q <= 0; + if (dps_done) + begin + shifts_done_counter <= 1'b1; + end + else + begin + if (phase_done_final & (dps_next_state!= DPS_DONE)) + shifts_done_counter <= shifts_done_counter + 1'b1; + else + shifts_done_counter <= shifts_done_counter; + end + end + end + + assign dps_changed_valid = (dps_current_state == DPS_CHANGED); + assign dps_done =(dps_current_state == DPS_DONE) | (dps_current_state == DPS_CHANGED); + assign up_dn = usr_up_dn; + assign gnd = 1'b0; + + //cnt select luts (5) + generic_lcell_comb lcell_cnt_sel_0 ( + .dataa(usr_cnt_sel[0]), + .datab(usr_cnt_sel[1]), + .datac(usr_cnt_sel[2]), + .datad(usr_cnt_sel[3]), + .datae(usr_cnt_sel[4]), + .dataf(gnd), + .combout (cnt_sel[0])); + defparam lcell_cnt_sel_0.lut_mask = 64'hAAAAAAAAAAAAAAAA; + defparam lcell_cnt_sel_0.dont_touch = "on"; + defparam lcell_cnt_sel_0.family = device_family; + generic_lcell_comb lcell_cnt_sel_1 ( + .dataa(usr_cnt_sel[0]), + .datab(usr_cnt_sel[1]), + .datac(usr_cnt_sel[2]), + .datad(usr_cnt_sel[3]), + .datae(usr_cnt_sel[4]), + .dataf(gnd), + .combout (cnt_sel[1])); + defparam lcell_cnt_sel_1.lut_mask = 64'hCCCCCCCCCCCCCCCC; + defparam lcell_cnt_sel_1.dont_touch = "on"; + defparam lcell_cnt_sel_1.family = device_family; + generic_lcell_comb lcell_cnt_sel_2 ( + .dataa(usr_cnt_sel[0]), + .datab(usr_cnt_sel[1]), + .datac(usr_cnt_sel[2]), + .datad(usr_cnt_sel[3]), + .datae(usr_cnt_sel[4]), + .dataf(gnd), + .combout (cnt_sel[2])); + defparam lcell_cnt_sel_2.lut_mask = 64'hF0F0F0F0F0F0F0F0; + defparam lcell_cnt_sel_2.dont_touch = "on"; + defparam lcell_cnt_sel_2.family = device_family; + generic_lcell_comb lcell_cnt_sel_3 ( + .dataa(usr_cnt_sel[0]), + .datab(usr_cnt_sel[1]), + .datac(usr_cnt_sel[2]), + .datad(usr_cnt_sel[3]), + .datae(usr_cnt_sel[4]), + .dataf(gnd), + .combout (cnt_sel[3])); + defparam lcell_cnt_sel_3.lut_mask = 64'hFF00FF00FF00FF00; + defparam lcell_cnt_sel_3.dont_touch = "on"; + defparam lcell_cnt_sel_3.family = device_family; + generic_lcell_comb lcell_cnt_sel_4 ( + .dataa(usr_cnt_sel[0]), + .datab(usr_cnt_sel[1]), + .datac(usr_cnt_sel[2]), + .datad(usr_cnt_sel[3]), + .datae(usr_cnt_sel[4]), + .dataf(gnd), + .combout (cnt_sel[4])); + defparam lcell_cnt_sel_4.lut_mask = 64'hFFFF0000FFFF0000; + defparam lcell_cnt_sel_4.dont_touch = "on"; + defparam lcell_cnt_sel_4.family = device_family; + + +endmodule + +module generic_lcell_comb +#( + //parameter + parameter family = "Cyclone V", + parameter lut_mask = 64'hAAAAAAAAAAAAAAAA, + parameter dont_touch = "on" +) ( + + input dataa, + input datab, + input datac, + input datad, + input datae, + input dataf, + + output combout +); + + generate + if (family == "Stratix V") + begin + stratixv_lcell_comb lcell_inst ( + .dataa(dataa), + .datab(datab), + .datac(datac), + .datad(datad), + .datae(datae), + .dataf(dataf), + .combout (combout)); + defparam lcell_inst.lut_mask = lut_mask; + defparam lcell_inst.dont_touch = dont_touch; + end + else if (family == "Arria V") + begin + arriav_lcell_comb lcell_inst ( + .dataa(dataa), + .datab(datab), + .datac(datac), + .datad(datad), + .datae(datae), + .dataf(dataf), + .combout (combout)); + defparam lcell_inst.lut_mask = lut_mask; + defparam lcell_inst.dont_touch = dont_touch; + end + else if (family == "Arria V GZ") + begin + arriavgz_lcell_comb lcell_inst ( + .dataa(dataa), + .datab(datab), + .datac(datac), + .datad(datad), + .datae(datae), + .dataf(dataf), + .combout (combout)); + defparam lcell_inst.lut_mask = lut_mask; + defparam lcell_inst.dont_touch = dont_touch; + end + else if (family == "Cyclone V") + begin + cyclonev_lcell_comb lcell_inst ( + .dataa(dataa), + .datab(datab), + .datac(datac), + .datad(datad), + .datae(datae), + .dataf(dataf), + .combout (combout)); + defparam lcell_inst.lut_mask = lut_mask; + defparam lcell_inst.dont_touch = dont_touch; + end + endgenerate +endmodule diff --git a/sys/pll_cfg/altera_pll_reconfig_top.v b/sys/pll_cfg/altera_pll_reconfig_top.v index c6d27bf..843c970 100644 --- a/sys/pll_cfg/altera_pll_reconfig_top.v +++ b/sys/pll_cfg/altera_pll_reconfig_top.v @@ -11,418 +11,418 @@ // agreement for further details. -`timescale 1ps/1ps - -module altera_pll_reconfig_top -#( - parameter reconf_width = 64, - parameter device_family = "Stratix V", - parameter RECONFIG_ADDR_WIDTH = 6, - parameter RECONFIG_DATA_WIDTH = 32, - - parameter ROM_ADDR_WIDTH = 9, - parameter ROM_DATA_WIDTH = 32, - parameter ROM_NUM_WORDS = 512, - - parameter ENABLE_MIF = 0, - parameter MIF_FILE_NAME = "", - - parameter ENABLE_BYTEENABLE = 0, - parameter BYTEENABLE_WIDTH = 4, - parameter WAIT_FOR_LOCK = 1 -) ( - - //input - input wire mgmt_clk, - input wire mgmt_reset, - - - //conduits - output wire [reconf_width-1:0] reconfig_to_pll, - input wire [reconf_width-1:0] reconfig_from_pll, - - // user data (avalon-MM slave interface) - output wire [RECONFIG_DATA_WIDTH-1:0] mgmt_readdata, - output wire mgmt_waitrequest, - input wire [RECONFIG_ADDR_WIDTH-1:0] mgmt_address, - input wire mgmt_read, - input wire mgmt_write, - input wire [RECONFIG_DATA_WIDTH-1:0] mgmt_writedata, - - //conditional input - input wire [BYTEENABLE_WIDTH-1:0] mgmt_byteenable -); - -localparam NM28_START_REG = 6'b000010; -localparam NM20_START_REG = 9'b000000000; -localparam NM20_MIFSTART_ADDR = 9'b000010000; - -localparam MIF_STATE_DONE = 2'b00; -localparam MIF_STATE_START = 2'b01; -localparam MIF_STATE_BUSY = 2'b10; - -wire mgmt_byteenable_write; -assign mgmt_byteenable_write = (ENABLE_BYTEENABLE == 1) ? - ((mgmt_byteenable == {BYTEENABLE_WIDTH{1'b1}}) ? mgmt_write : 1'b0) : - mgmt_write; - -generate -if (device_family == "Arria 10") -begin:nm20_reconfig - if(ENABLE_MIF == 1) - begin:mif_reconfig_20nm // Generate Reconfig with MIF - - // MIF-related regs/wires - reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr; - reg reconfig_mgmt_read; - reg reconfig_mgmt_write; - reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata; - wire reconfig_mgmt_waitrequest; - wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata; - - wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr; - wire mif_busy; - wire mif2reconfig_read; - wire mif2reconfig_write; - wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata; - wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; - reg mif_select; - //wire mif_user_start; // start signal provided by user to start mif - //reg user_start; - - reg [1:0] mif_curstate; - reg [1:0] mif_nextstate; - - wire mif_start; //start signal to mif reader - - assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif_busy;// | user_start; - // Don't output readdata if MIF streaming is taking place - assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata; - - //user must lower this by the time mif streaming is done - suggest to lower after 1 cycle - assign mif_start = mgmt_byteenable_write & (mgmt_address == NM20_MIFSTART_ADDR); - - //mif base addr is initially specified by the user - assign mif_base_addr = mgmt_writedata[ROM_ADDR_WIDTH-1:0]; - - //MIF statemachine - always @(posedge mgmt_clk) - begin - if(mgmt_reset) - mif_curstate <= MIF_STATE_DONE; - else - mif_curstate <= mif_nextstate; - end - - always @(*) - begin - case (mif_curstate) - MIF_STATE_DONE: - begin - if(mif_start) - mif_nextstate <= MIF_STATE_START; - else - mif_nextstate <= MIF_STATE_DONE; - end - MIF_STATE_START: - begin - mif_nextstate <= MIF_STATE_BUSY; - end - MIF_STATE_BUSY: - begin - if(mif_busy) - mif_nextstate <= MIF_STATE_BUSY; - else - mif_nextstate <= MIF_STATE_DONE; - end - endcase - end - - //Mif muxes - always @(*) - begin - if (mgmt_reset) - begin - reconfig_mgmt_addr <= 0; - reconfig_mgmt_read <= 0; - reconfig_mgmt_write <= 0; - reconfig_mgmt_writedata <= 0; - //user_start <= 0; - end - else - begin - reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address; - reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read; - reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write; - reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata; - //user_start <= (mgmt_address == NM20_START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0; - end - end - - always @(*) - begin - if (mgmt_reset) - begin - mif_select <= 0; - end - else - begin - mif_select <= (mif_start || mif_busy) ? 1'b1 : 1'b0; - end - end - - twentynm_pll_reconfig_mif_reader - #( - .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), - .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), - .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), - .ROM_DATA_WIDTH(ROM_DATA_WIDTH), - .ROM_NUM_WORDS(ROM_NUM_WORDS), - .DEVICE_FAMILY(device_family), - .ENABLE_MIF(ENABLE_MIF), - .MIF_FILE_NAME(MIF_FILE_NAME) - ) twentynm_pll_reconfig_mif_reader_inst0 ( - .mif_clk(mgmt_clk), - .mif_rst(mgmt_reset), - - //Altera_PLL Reconfig interface - //inputs - .reconfig_waitrequest(reconfig_mgmt_waitrequest), - //.reconfig_read_data(reconfig_mgmt_readdata), - //outputs - .reconfig_write_data(mif2reconfig_writedata), - .reconfig_addr(mif2reconfig_addr), - .reconfig_write(mif2reconfig_write), - .reconfig_read(mif2reconfig_read), - - //MIF Ctrl Interface - //inputs - .mif_base_addr(mif_base_addr), - .mif_start(mif_start), - //outputs - .mif_busy(mif_busy) - ); - - // ------ END MIF-RELATED MANAGEMENT ------ - - twentynm_iopll_reconfig_core - #( - .WAIT_FOR_LOCK(WAIT_FOR_LOCK) - ) twentynm_iopll_reconfig_core_inst ( - // Inputs - .mgmt_clk(mgmt_clk), - .mgmt_rst_n(~mgmt_reset), - .mgmt_read(reconfig_mgmt_read), - .mgmt_write(reconfig_mgmt_write), - .mgmt_address(reconfig_mgmt_addr), - .mgmt_writedata(reconfig_mgmt_writedata), - - // Outputs - .mgmt_readdata(reconfig_mgmt_readdata), - .mgmt_waitrequest(reconfig_mgmt_waitrequest), - - // PLL Conduits - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll) - ); - - end // End generate reconfig with MIF - else - begin:reconfig_core_20nm - twentynm_iopll_reconfig_core - #( - .WAIT_FOR_LOCK(WAIT_FOR_LOCK) - ) twentynm_iopll_reconfig_core_inst ( - // Inputs - .mgmt_clk(mgmt_clk), - .mgmt_rst_n(~mgmt_reset), - .mgmt_read(mgmt_read), - .mgmt_write(mgmt_byteenable_write), - .mgmt_address(mgmt_address), - .mgmt_writedata(mgmt_writedata), - - // Outputs - .mgmt_readdata(mgmt_readdata), - .mgmt_waitrequest(mgmt_waitrequest), - - // PLL Conduits - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll) - ); - end -end // 20nm reconfig -else -begin:NM28_reconfig - if (ENABLE_MIF == 1) - begin:mif_reconfig // Generate Reconfig with MIF - - // MIF-related regs/wires - reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr; - reg reconfig_mgmt_read; - reg reconfig_mgmt_write; - reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata; - wire reconfig_mgmt_waitrequest; - wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata; - - wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr; - wire mif2reconfig_busy; - wire mif2reconfig_read; - wire mif2reconfig_write; - wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata; - wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; - reg mif_select; - reg user_start; - - wire reconfig2mif_start_out; - - assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start; - // Don't output readdata if MIF streaming is taking place - assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata; - - always @(posedge mgmt_clk) - begin - if (mgmt_reset) - begin - reconfig_mgmt_addr <= 0; - reconfig_mgmt_read <= 0; - reconfig_mgmt_write <= 0; - reconfig_mgmt_writedata <= 0; - user_start <= 0; - end - else - begin - reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address; - reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read; - reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write; - reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata; - user_start <= (mgmt_address == NM28_START_REG && mgmt_byteenable_write == 1'b1) ? 1'b1 : 1'b0; - end - end - - always @(*) - begin - if (mgmt_reset) - begin - mif_select <= 0; - end - else - begin - mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0; - end - end - - altera_pll_reconfig_mif_reader - #( - .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), - .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), - .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), - .ROM_DATA_WIDTH(ROM_DATA_WIDTH), - .ROM_NUM_WORDS(ROM_NUM_WORDS), - .DEVICE_FAMILY(device_family), - .ENABLE_MIF(ENABLE_MIF), - .MIF_FILE_NAME(MIF_FILE_NAME) - ) altera_pll_reconfig_mif_reader_inst0 ( - .mif_clk(mgmt_clk), - .mif_rst(mgmt_reset), - - //Altera_PLL Reconfig interface - //inputs - .reconfig_busy(reconfig_mgmt_waitrequest), - .reconfig_read_data(reconfig_mgmt_readdata), - //outputs - .reconfig_write_data(mif2reconfig_writedata), - .reconfig_addr(mif2reconfig_addr), - .reconfig_write(mif2reconfig_write), - .reconfig_read(mif2reconfig_read), - - //MIF Ctrl Interface - //inputs - .mif_base_addr(mif_base_addr), - .mif_start(reconfig2mif_start_out), - //outputs - .mif_busy(mif2reconfig_busy) - ); - - // ------ END MIF-RELATED MANAGEMENT ------ - - - altera_pll_reconfig_core - #( - .reconf_width(reconf_width), - .device_family(device_family), - .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), - .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), - .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), - .ROM_DATA_WIDTH(ROM_DATA_WIDTH), - .ROM_NUM_WORDS(ROM_NUM_WORDS) - ) altera_pll_reconfig_core_inst0 ( - //inputs - .mgmt_clk(mgmt_clk), - .mgmt_reset(mgmt_reset), - - //PLL interface conduits - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll), - - //User data outputs - .mgmt_readdata(reconfig_mgmt_readdata), - .mgmt_waitrequest(reconfig_mgmt_waitrequest), - - //User data inputs - .mgmt_address(reconfig_mgmt_addr), - .mgmt_read(reconfig_mgmt_read), - .mgmt_write(reconfig_mgmt_write), - .mgmt_writedata(reconfig_mgmt_writedata), - - // other - .mif_start_out(reconfig2mif_start_out), - .mif_base_addr(mif_base_addr) - ); - - end // End generate reconfig with MIF - else - begin:reconfig_core // Generate Reconfig core only - - wire reconfig2mif_start_out; - wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; - - altera_pll_reconfig_core - #( - .reconf_width(reconf_width), - .device_family(device_family), - .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), - .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), - .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), - .ROM_DATA_WIDTH(ROM_DATA_WIDTH), - .ROM_NUM_WORDS(ROM_NUM_WORDS) - ) altera_pll_reconfig_core_inst0 ( - //inputs - .mgmt_clk(mgmt_clk), - .mgmt_reset(mgmt_reset), - - //PLL interface conduits - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll), - - //User data outputs - .mgmt_readdata(mgmt_readdata), - .mgmt_waitrequest(mgmt_waitrequest), - - //User data inputs - .mgmt_address(mgmt_address), - .mgmt_read(mgmt_read), - .mgmt_write(mgmt_byteenable_write), - .mgmt_writedata(mgmt_writedata), - - // other - .mif_start_out(reconfig2mif_start_out), - .mif_base_addr(mif_base_addr) - ); - - - end // End generate reconfig core only -end // End 28nm Reconfig -endgenerate - -endmodule - +`timescale 1ps/1ps + +module altera_pll_reconfig_top +#( + parameter reconf_width = 64, + parameter device_family = "Cyclone V", + parameter RECONFIG_ADDR_WIDTH = 6, + parameter RECONFIG_DATA_WIDTH = 32, + + parameter ROM_ADDR_WIDTH = 9, + parameter ROM_DATA_WIDTH = 32, + parameter ROM_NUM_WORDS = 512, + + parameter ENABLE_MIF = 0, + parameter MIF_FILE_NAME = "", + + parameter ENABLE_BYTEENABLE = 0, + parameter BYTEENABLE_WIDTH = 4, + parameter WAIT_FOR_LOCK = 1 +) ( + + //input + input wire mgmt_clk, + input wire mgmt_reset, + + + //conduits + output wire [reconf_width-1:0] reconfig_to_pll, + input wire [reconf_width-1:0] reconfig_from_pll, + + // user data (avalon-MM slave interface) + output wire [RECONFIG_DATA_WIDTH-1:0] mgmt_readdata, + output wire mgmt_waitrequest, + input wire [RECONFIG_ADDR_WIDTH-1:0] mgmt_address, + input wire mgmt_read, + input wire mgmt_write, + input wire [RECONFIG_DATA_WIDTH-1:0] mgmt_writedata, + + //conditional input + input wire [BYTEENABLE_WIDTH-1:0] mgmt_byteenable +); + +localparam NM28_START_REG = 6'b000010; +localparam NM20_START_REG = 9'b000000000; +localparam NM20_MIFSTART_ADDR = 9'b000010000; + +localparam MIF_STATE_DONE = 2'b00; +localparam MIF_STATE_START = 2'b01; +localparam MIF_STATE_BUSY = 2'b10; + +wire mgmt_byteenable_write; +assign mgmt_byteenable_write = (ENABLE_BYTEENABLE == 1) ? + ((mgmt_byteenable == {BYTEENABLE_WIDTH{1'b1}}) ? mgmt_write : 1'b0) : + mgmt_write; + +generate +if (device_family == "Arria 10") +begin:nm20_reconfig + if(ENABLE_MIF == 1) + begin:mif_reconfig_20nm // Generate Reconfig with MIF + + // MIF-related regs/wires + reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr; + reg reconfig_mgmt_read; + reg reconfig_mgmt_write; + reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata; + wire reconfig_mgmt_waitrequest; + wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata; + + wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr; + wire mif_busy; + wire mif2reconfig_read; + wire mif2reconfig_write; + wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata; + wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; + reg mif_select; + //wire mif_user_start; // start signal provided by user to start mif + //reg user_start; + + reg [1:0] mif_curstate; + reg [1:0] mif_nextstate; + + wire mif_start; //start signal to mif reader + + assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif_busy;// | user_start; + // Don't output readdata if MIF streaming is taking place + assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata; + + //user must lower this by the time mif streaming is done - suggest to lower after 1 cycle + assign mif_start = mgmt_byteenable_write & (mgmt_address == NM20_MIFSTART_ADDR); + + //mif base addr is initially specified by the user + assign mif_base_addr = mgmt_writedata[ROM_ADDR_WIDTH-1:0]; + + //MIF statemachine + always @(posedge mgmt_clk) + begin + if(mgmt_reset) + mif_curstate <= MIF_STATE_DONE; + else + mif_curstate <= mif_nextstate; + end + + always @(*) + begin + case (mif_curstate) + MIF_STATE_DONE: + begin + if(mif_start) + mif_nextstate <= MIF_STATE_START; + else + mif_nextstate <= MIF_STATE_DONE; + end + MIF_STATE_START: + begin + mif_nextstate <= MIF_STATE_BUSY; + end + MIF_STATE_BUSY: + begin + if(mif_busy) + mif_nextstate <= MIF_STATE_BUSY; + else + mif_nextstate <= MIF_STATE_DONE; + end + endcase + end + + //Mif muxes + always @(*) + begin + if (mgmt_reset) + begin + reconfig_mgmt_addr <= 0; + reconfig_mgmt_read <= 0; + reconfig_mgmt_write <= 0; + reconfig_mgmt_writedata <= 0; + //user_start <= 0; + end + else + begin + reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address; + reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read; + reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write; + reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata; + //user_start <= (mgmt_address == NM20_START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0; + end + end + + always @(*) + begin + if (mgmt_reset) + begin + mif_select <= 0; + end + else + begin + mif_select <= (mif_start || mif_busy) ? 1'b1 : 1'b0; + end + end + + twentynm_pll_reconfig_mif_reader + #( + .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), + .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), + .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), + .ROM_DATA_WIDTH(ROM_DATA_WIDTH), + .ROM_NUM_WORDS(ROM_NUM_WORDS), + .DEVICE_FAMILY(device_family), + .ENABLE_MIF(ENABLE_MIF), + .MIF_FILE_NAME(MIF_FILE_NAME) + ) twentynm_pll_reconfig_mif_reader_inst0 ( + .mif_clk(mgmt_clk), + .mif_rst(mgmt_reset), + + //Altera_PLL Reconfig interface + //inputs + .reconfig_waitrequest(reconfig_mgmt_waitrequest), + //.reconfig_read_data(reconfig_mgmt_readdata), + //outputs + .reconfig_write_data(mif2reconfig_writedata), + .reconfig_addr(mif2reconfig_addr), + .reconfig_write(mif2reconfig_write), + .reconfig_read(mif2reconfig_read), + + //MIF Ctrl Interface + //inputs + .mif_base_addr(mif_base_addr), + .mif_start(mif_start), + //outputs + .mif_busy(mif_busy) + ); + + // ------ END MIF-RELATED MANAGEMENT ------ + + twentynm_iopll_reconfig_core + #( + .WAIT_FOR_LOCK(WAIT_FOR_LOCK) + ) twentynm_iopll_reconfig_core_inst ( + // Inputs + .mgmt_clk(mgmt_clk), + .mgmt_rst_n(~mgmt_reset), + .mgmt_read(reconfig_mgmt_read), + .mgmt_write(reconfig_mgmt_write), + .mgmt_address(reconfig_mgmt_addr), + .mgmt_writedata(reconfig_mgmt_writedata), + + // Outputs + .mgmt_readdata(reconfig_mgmt_readdata), + .mgmt_waitrequest(reconfig_mgmt_waitrequest), + + // PLL Conduits + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll) + ); + + end // End generate reconfig with MIF + else + begin:reconfig_core_20nm + twentynm_iopll_reconfig_core + #( + .WAIT_FOR_LOCK(WAIT_FOR_LOCK) + ) twentynm_iopll_reconfig_core_inst ( + // Inputs + .mgmt_clk(mgmt_clk), + .mgmt_rst_n(~mgmt_reset), + .mgmt_read(mgmt_read), + .mgmt_write(mgmt_byteenable_write), + .mgmt_address(mgmt_address), + .mgmt_writedata(mgmt_writedata), + + // Outputs + .mgmt_readdata(mgmt_readdata), + .mgmt_waitrequest(mgmt_waitrequest), + + // PLL Conduits + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll) + ); + end +end // 20nm reconfig +else +begin:NM28_reconfig + if (ENABLE_MIF == 1) + begin:mif_reconfig // Generate Reconfig with MIF + + // MIF-related regs/wires + reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr; + reg reconfig_mgmt_read; + reg reconfig_mgmt_write; + reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata; + wire reconfig_mgmt_waitrequest; + wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata; + + wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr; + wire mif2reconfig_busy; + wire mif2reconfig_read; + wire mif2reconfig_write; + wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata; + wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; + reg mif_select; + reg user_start; + + wire reconfig2mif_start_out; + + assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start; + // Don't output readdata if MIF streaming is taking place + assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata; + + always @(posedge mgmt_clk) + begin + if (mgmt_reset) + begin + reconfig_mgmt_addr <= 0; + reconfig_mgmt_read <= 0; + reconfig_mgmt_write <= 0; + reconfig_mgmt_writedata <= 0; + user_start <= 0; + end + else + begin + reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address; + reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read; + reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write; + reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata; + user_start <= (mgmt_address == NM28_START_REG && mgmt_byteenable_write == 1'b1) ? 1'b1 : 1'b0; + end + end + + always @(*) + begin + if (mgmt_reset) + begin + mif_select <= 0; + end + else + begin + mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0; + end + end + + altera_pll_reconfig_mif_reader + #( + .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), + .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), + .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), + .ROM_DATA_WIDTH(ROM_DATA_WIDTH), + .ROM_NUM_WORDS(ROM_NUM_WORDS), + .DEVICE_FAMILY(device_family), + .ENABLE_MIF(ENABLE_MIF), + .MIF_FILE_NAME(MIF_FILE_NAME) + ) altera_pll_reconfig_mif_reader_inst0 ( + .mif_clk(mgmt_clk), + .mif_rst(mgmt_reset), + + //Altera_PLL Reconfig interface + //inputs + .reconfig_busy(reconfig_mgmt_waitrequest), + .reconfig_read_data(reconfig_mgmt_readdata), + //outputs + .reconfig_write_data(mif2reconfig_writedata), + .reconfig_addr(mif2reconfig_addr), + .reconfig_write(mif2reconfig_write), + .reconfig_read(mif2reconfig_read), + + //MIF Ctrl Interface + //inputs + .mif_base_addr(mif_base_addr), + .mif_start(reconfig2mif_start_out), + //outputs + .mif_busy(mif2reconfig_busy) + ); + + // ------ END MIF-RELATED MANAGEMENT ------ + + + altera_pll_reconfig_core + #( + .reconf_width(reconf_width), + .device_family(device_family), + .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), + .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), + .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), + .ROM_DATA_WIDTH(ROM_DATA_WIDTH), + .ROM_NUM_WORDS(ROM_NUM_WORDS) + ) altera_pll_reconfig_core_inst0 ( + //inputs + .mgmt_clk(mgmt_clk), + .mgmt_reset(mgmt_reset), + + //PLL interface conduits + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll), + + //User data outputs + .mgmt_readdata(reconfig_mgmt_readdata), + .mgmt_waitrequest(reconfig_mgmt_waitrequest), + + //User data inputs + .mgmt_address(reconfig_mgmt_addr), + .mgmt_read(reconfig_mgmt_read), + .mgmt_write(reconfig_mgmt_write), + .mgmt_writedata(reconfig_mgmt_writedata), + + // other + .mif_start_out(reconfig2mif_start_out), + .mif_base_addr(mif_base_addr) + ); + + end // End generate reconfig with MIF + else + begin:reconfig_core // Generate Reconfig core only + + wire reconfig2mif_start_out; + wire [ROM_ADDR_WIDTH-1:0] mif_base_addr; + + altera_pll_reconfig_core + #( + .reconf_width(reconf_width), + .device_family(device_family), + .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH), + .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH), + .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH), + .ROM_DATA_WIDTH(ROM_DATA_WIDTH), + .ROM_NUM_WORDS(ROM_NUM_WORDS) + ) altera_pll_reconfig_core_inst0 ( + //inputs + .mgmt_clk(mgmt_clk), + .mgmt_reset(mgmt_reset), + + //PLL interface conduits + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll), + + //User data outputs + .mgmt_readdata(mgmt_readdata), + .mgmt_waitrequest(mgmt_waitrequest), + + //User data inputs + .mgmt_address(mgmt_address), + .mgmt_read(mgmt_read), + .mgmt_write(mgmt_byteenable_write), + .mgmt_writedata(mgmt_writedata), + + // other + .mif_start_out(reconfig2mif_start_out), + .mif_base_addr(mif_base_addr) + ); + + + end // End generate reconfig core only +end // End 28nm Reconfig +endgenerate + +endmodule + diff --git a/sys/pll_cfg.v b/sys/pll_cfg/pll_cfg.v similarity index 98% rename from sys/pll_cfg.v rename to sys/pll_cfg/pll_cfg.v index 2a2f078..0adc36f 100644 --- a/sys/pll_cfg.v +++ b/sys/pll_cfg/pll_cfg.v @@ -1,86 +1,86 @@ -// megafunction wizard: %Altera PLL Reconfig v17.0% -// GENERATION: XML -// pll_cfg.v - -// Generated using ACDS version 17.0 598 - -`timescale 1 ps / 1 ps -module pll_cfg #( - parameter ENABLE_BYTEENABLE = 0, - parameter BYTEENABLE_WIDTH = 4, - parameter RECONFIG_ADDR_WIDTH = 6, - parameter RECONFIG_DATA_WIDTH = 32, - parameter reconf_width = 64, - parameter WAIT_FOR_LOCK = 1 - ) ( - input wire mgmt_clk, // mgmt_clk.clk - input wire mgmt_reset, // mgmt_reset.reset - output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest - input wire mgmt_read, // .read - input wire mgmt_write, // .write - output wire [31:0] mgmt_readdata, // .readdata - input wire [5:0] mgmt_address, // .address - input wire [31:0] mgmt_writedata, // .writedata - output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll - input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll - ); - - altera_pll_reconfig_top #( - .device_family ("Cyclone V"), - .ENABLE_MIF (0), - .MIF_FILE_NAME ("sys/pll_cfg.mif"), - .ENABLE_BYTEENABLE (ENABLE_BYTEENABLE), - .BYTEENABLE_WIDTH (BYTEENABLE_WIDTH), - .RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH), - .RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH), - .reconf_width (reconf_width), - .WAIT_FOR_LOCK (WAIT_FOR_LOCK) - ) pll_cfg_inst ( - .mgmt_clk (mgmt_clk), // mgmt_clk.clk - .mgmt_reset (mgmt_reset), // mgmt_reset.reset - .mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest - .mgmt_read (mgmt_read), // .read - .mgmt_write (mgmt_write), // .write - .mgmt_readdata (mgmt_readdata), // .readdata - .mgmt_address (mgmt_address), // .address - .mgmt_writedata (mgmt_writedata), // .writedata - .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll - .reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll - .mgmt_byteenable (4'b0000) // (terminated) - ); - -endmodule -// Retrieval info: -// -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// IPFS_FILES : pll_cfg.vo -// RELATED_FILES: pll_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v +// megafunction wizard: %Altera PLL Reconfig v17.0% +// GENERATION: XML +// pll_cfg.v + +// Generated using ACDS version 17.0 598 + +`timescale 1 ps / 1 ps +module pll_cfg #( + parameter ENABLE_BYTEENABLE = 0, + parameter BYTEENABLE_WIDTH = 4, + parameter RECONFIG_ADDR_WIDTH = 6, + parameter RECONFIG_DATA_WIDTH = 32, + parameter reconf_width = 64, + parameter WAIT_FOR_LOCK = 1 + ) ( + input wire mgmt_clk, // mgmt_clk.clk + input wire mgmt_reset, // mgmt_reset.reset + output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest + input wire mgmt_read, // .read + input wire mgmt_write, // .write + output wire [31:0] mgmt_readdata, // .readdata + input wire [5:0] mgmt_address, // .address + input wire [31:0] mgmt_writedata, // .writedata + output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll + input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll + ); + + altera_pll_reconfig_top #( + .device_family ("Cyclone V"), + .ENABLE_MIF (0), + .MIF_FILE_NAME ("sys/pll_cfg.mif"), + .ENABLE_BYTEENABLE (ENABLE_BYTEENABLE), + .BYTEENABLE_WIDTH (BYTEENABLE_WIDTH), + .RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH), + .RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH), + .reconf_width (reconf_width), + .WAIT_FOR_LOCK (WAIT_FOR_LOCK) + ) pll_cfg_inst ( + .mgmt_clk (mgmt_clk), // mgmt_clk.clk + .mgmt_reset (mgmt_reset), // mgmt_reset.reset + .mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest + .mgmt_read (mgmt_read), // .read + .mgmt_write (mgmt_write), // .write + .mgmt_readdata (mgmt_readdata), // .readdata + .mgmt_address (mgmt_address), // .address + .mgmt_writedata (mgmt_writedata), // .writedata + .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll + .reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll + .mgmt_byteenable (4'b0000) // (terminated) + ); + +endmodule +// Retrieval info: +// +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// IPFS_FILES : pll_cfg.vo +// RELATED_FILES: pll_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v diff --git a/sys/pll_cfg/pll_cfg_hdmi.v b/sys/pll_cfg/pll_cfg_hdmi.v new file mode 100644 index 0000000..1912c2a --- /dev/null +++ b/sys/pll_cfg/pll_cfg_hdmi.v @@ -0,0 +1,1282 @@ +// (C) 2001-2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + +// original file was altera_pll_reconfig_core.v +// not needed functionality was cut out to reduce ressource consumption + +module pll_cfg_hdmi +#( + parameter reconf_width = 64, + parameter device_family = "Cyclone V" +) ( + + //input + input wire mgmt_clk, + input wire mgmt_reset, + + + //conduits + output wire [reconf_width-1:0] reconfig_to_pll, + input wire [reconf_width-1:0] reconfig_from_pll, + + // user data (avalon-MM slave interface) + output wire mgmt_waitrequest, + input wire [5:0] mgmt_address, + input wire mgmt_write, + input wire [31:0] mgmt_writedata +); + localparam mode_WR = 1'b0; + localparam MODE_REG = 6'b000000; + localparam START_REG = 6'b000010; + localparam N_REG = 6'b000011; + localparam M_REG = 6'b000100; + localparam C_COUNTERS_REG = 6'b000101; + //localparam DPS_REG = 6'b000110; // unused + localparam DSM_REG = 6'b000111; + localparam BWCTRL_REG = 6'b001000; + localparam CP_CURRENT_REG = 6'b001001; + //localparam ANY_DPRIO = 6'b100000; // unused + //localparam CNT_BASE = 5'b001010; // unused + //localparam VCO_REG = 6'b011100; // unused + + //C Counters + localparam number_of_counters = 5'd6; + //C counter addresses + localparam C_CNT_0_DIV_ADDR = 5'h00; + localparam C_CNT_0_DIV_ADDR_DPRIO_1 = 5'h11; + localparam C_CNT_0_3_BYPASS_EN_ADDR = 5'h15; + localparam C_CNT_0_3_ODD_DIV_EN_ADDR = 5'h17; + localparam C_CNT_4_17_BYPASS_EN_ADDR = 5'h14; + localparam C_CNT_4_17_ODD_DIV_EN_ADDR = 5'h16; + //N counter addresses + localparam N_CNT_DIV_ADDR = 5'h13; + localparam N_CNT_BYPASS_EN_ADDR = 5'h15; + localparam N_CNT_ODD_DIV_EN_ADDR = 5'h17; + //M counter addresses + localparam M_CNT_DIV_ADDR = 5'h12; + localparam M_CNT_BYPASS_EN_ADDR = 5'h15; + localparam M_CNT_ODD_DIV_EN_ADDR = 5'h17; + + //DSM address + localparam DSM_K_FRACTIONAL_DIVISION_ADDR_0 = 5'h18; + localparam DSM_K_FRACTIONAL_DIVISION_ADDR_1 = 5'h19; + localparam DSM_K_READY_ADDR = 5'h17; + localparam DSM_K_DITHER_ADDR = 5'h17; + localparam DSM_OUT_SEL_ADDR = 6'h30; + + //Other DSM params + localparam DSM_K_READY_BIT_INDEX = 4'd11; + //BWCTRL address + //Bit 0-3 of addr + localparam BWCTRL_ADDR = 6'h30; + //CP_CURRENT address + //Bit 0-2 of addr + localparam CP_CURRENT_ADDR = 6'h31; + + // VCODIV address + localparam VCO_ADDR = 5'h17; + + localparam DPRIO_IDLE = 3'd0, ONE = 3'd1, TWO = 3'd2, THREE = 3'd3, FOUR = 3'd4, + FIVE = 3'd5, SIX = 3'd6, SEVEN = 3'd7, EIGHT = 4'd8, NINE = 4'd9, TEN = 4'd10, + ELEVEN = 4'd11, TWELVE = 4'd12, THIRTEEN = 4'd13, FOURTEEN = 4'd14, DPRIO_DONE = 4'd15; + localparam IDLE = 2'b00, WAIT_ON_LOCK = 2'b01, LOCKED = 2'b10; + + wire clk; + wire reset; + wire gnd; + + wire [5: 0] slave_address; + wire slave_write; + wire [31: 0] slave_writedata; + + wire slave_waitrequest; + reg slave_mode; + + assign clk = mgmt_clk; + + assign slave_address = mgmt_address; + assign slave_write = mgmt_write; + assign slave_writedata = mgmt_writedata; + + // Outputs + assign mgmt_waitrequest = slave_waitrequest; //Read waitrequest asserted in polling mode + + //internal signals + wire locked_orig; + wire locked; + + wire pll_start; + wire pll_start_valid; + + wire pll_start_asserted; + + reg [1:0] current_state; + reg [1:0] next_state; + + reg status;//0=busy, 1=ready + //user_mode_init user_mode_init_inst (clk, reset, dprio_mdio_dis, ser_shift_load); + //declaring the init wires. These will have 0 on them for 64 clk cycles + wire [ 5:0] init_dprio_address; + wire init_dprio_read; + wire [ 1:0] init_dprio_byteen; + wire init_dprio_write; + wire [15:0] init_dprio_writedata; + + wire init_atpgmode; + wire init_mdio_dis; + wire init_scanen; + wire init_ser_shift_load; + wire dprio_init_done; + + //DPRIO output signals after initialization is done + wire dprio_clk; + reg avmm_dprio_write; + reg avmm_dprio_read; + reg [5:0] avmm_dprio_address; + reg [15:0] avmm_dprio_writedata; + reg [1:0] avmm_dprio_byteen; + wire avmm_atpgmode; + wire avmm_mdio_dis; + wire avmm_scanen; + + //Final output wires that are muxed between the init and avmm wires. + wire dprio_init_reset; + wire [5:0] dprio_address /*synthesis keep*/; + wire dprio_read/*synthesis keep*/; + wire [1:0] dprio_byteen/*synthesis keep*/; + wire dprio_write/*synthesis keep*/; + wire [15:0] dprio_writedata/*synthesis keep*/; + wire dprio_mdio_dis/*synthesis keep*/; + wire dprio_ser_shift_load/*synthesis keep*/; + wire dprio_atpgmode/*synthesis keep*/; + wire dprio_scanen/*synthesis keep*/; + + + //other PLL signals for dyn ph shift + wire phase_done/*synthesis keep*/; + wire phase_en/*synthesis keep*/; + wire up_dn/*synthesis keep*/; + wire [4:0] cnt_sel; + + //DPRIO input signals + wire [15:0] dprio_readdata; + + //internal logic signals + //storage registers for user sent data + reg dprio_temp_read_1; + reg dprio_temp_read_2; + reg dprio_start; + wire usr_valid_changes; + reg [3:0] dprio_cur_state; + reg [3:0] dprio_next_state; + reg [15:0] dprio_temp_m_n_c_readdata_1_d; + reg [15:0] dprio_temp_m_n_c_readdata_2_d; + reg [15:0] dprio_temp_m_n_c_readdata_1_q; + reg [15:0] dprio_temp_m_n_c_readdata_2_q; + reg dprio_write_done; + //C counters signals + reg [7:0] usr_c_cnt_lo; + reg [7:0] usr_c_cnt_hi; + reg usr_c_cnt_bypass_en; + reg usr_c_cnt_odd_duty_div_en; + reg temp_c_cnt_bypass_en [0:17]; + reg temp_c_cnt_odd_duty_div_en [0:17]; + reg any_c_cnt_changed; + reg all_c_cnt_done_q; + reg all_c_cnt_done_d; + reg [17:0] c_cnt_changed; + reg [17:0] c_cnt_done_d; + reg [17:0] c_cnt_done_q; + //N counter signals + reg [7:0] usr_n_cnt_lo; + reg [7:0] usr_n_cnt_hi; + reg usr_n_cnt_bypass_en; + reg usr_n_cnt_odd_duty_div_en; + reg n_cnt_changed; + reg n_cnt_done_d; + reg n_cnt_done_q; + //M counter signals + reg [7:0] usr_m_cnt_lo; + reg [7:0] usr_m_cnt_hi; + reg usr_m_cnt_bypass_en; + reg usr_m_cnt_odd_duty_div_en; + reg m_cnt_changed; + reg m_cnt_done_d; + reg m_cnt_done_q; + //dyn phase regs + reg [15:0] usr_num_shifts; + reg [4:0] usr_cnt_sel /*synthesis preserve*/; + reg usr_up_dn; + reg dps_changed; + wire dps_changed_valid; + wire dps_done; + + //DSM Signals + reg [31:0] usr_k_value; + reg dsm_k_changed; + reg dsm_k_done_d; + reg dsm_k_done_q; + reg dsm_k_ready_false_done_d; + //BW signals + reg [3:0] usr_bwctrl_value; + reg bwctrl_changed; + reg bwctrl_done_d; + reg bwctrl_done_q; + //CP signals + reg [2:0] usr_cp_current_value; + reg cp_current_changed; + reg cp_current_done_d; + reg cp_current_done_q; + //VCO signals + reg usr_vco_value; + reg vco_changed; + reg vco_done_d; + reg vco_done_q; + //Manual DPRIO signals + reg manual_dprio_done_q; + reg manual_dprio_done_d; + reg manual_dprio_changed; + reg [5:0] usr_dprio_address; + reg [15:0] usr_dprio_writedata_0; + reg usr_r_w; + //keeping track of which operation happened last + reg [5:0] operation_address; + // Address wires for all C_counter DPRIO registers + // These are outputs of LUTS, changing depending + // on whether PLL_0 or PLL_1 being used + + + //Fitter will tell if FPLL1 is being used + wire fpll_1; + + // MAIN FSM + + // Synchronize locked signal + altera_std_synchronizer #( + .depth(3) + ) altera_std_synchronizer_inst ( + .clk(mgmt_clk), + .reset_n(~mgmt_reset), + .din(locked_orig), + .dout(locked) + ); + + always @(posedge clk) + begin + if (reset) + begin + dprio_cur_state <= DPRIO_IDLE; + current_state <= IDLE; + end + else + begin + current_state <= next_state; + dprio_cur_state <= dprio_next_state; + end + end + + always @(*) + begin + case(current_state) + IDLE: + begin + if (pll_start & !slave_waitrequest & usr_valid_changes) + next_state = WAIT_ON_LOCK; + else + next_state = IDLE; + end + WAIT_ON_LOCK: + begin + if (locked & dps_done & dprio_write_done) // received locked high from PLL + begin + if (slave_mode==mode_WR) //if the mode is waitrequest, then + // goto IDLE state directly + next_state = IDLE; + else + next_state = LOCKED; //otherwise go the locked state + end + else + next_state = WAIT_ON_LOCK; + end + + LOCKED: + begin + next_state = LOCKED; + end + + default: next_state = 2'bxx; + + endcase + end + + + // ask the pll to start reconfig + assign pll_start = (pll_start_asserted & (current_state==IDLE)) ; + assign pll_start_valid = (pll_start & (next_state==WAIT_ON_LOCK)) ; + + + + // WRITE OPERATIONS + assign pll_start_asserted = slave_write & (slave_address == START_REG); + + //reading the mode register to determine what mode the slave will operate + //in. + always @(posedge clk) + begin + if (reset) + slave_mode <= mode_WR; + else if (slave_write & (slave_address == MODE_REG) & !slave_waitrequest) + slave_mode <= slave_writedata[0]; + end + + //record which values user wants to change. + + //reading in the actual values that need to be reconfigged and sending + //them to the PLL + always @(posedge clk) + begin + if (reset) + begin + //reset all regs here + //BW signals reset + usr_bwctrl_value <= 0; + bwctrl_changed <= 0; + bwctrl_done_q <= 0; + //CP signals reset + usr_cp_current_value <= 0; + cp_current_changed <= 0; + cp_current_done_q <= 0; + //VCO signals reset + usr_vco_value <= 0; + vco_changed <= 0; + vco_done_q <= 0; + //DSM signals reset + usr_k_value <= 0; + dsm_k_changed <= 0; + dsm_k_done_q <= 0; + //N counter signals reset + usr_n_cnt_lo <= 0; + usr_n_cnt_hi <= 0; + usr_n_cnt_bypass_en <= 0; + usr_n_cnt_odd_duty_div_en <= 0; + n_cnt_changed <= 0; + n_cnt_done_q <= 0; + //M counter signals reset + usr_m_cnt_lo <= 0; + usr_m_cnt_hi <= 0; + usr_m_cnt_bypass_en <= 0; + usr_m_cnt_odd_duty_div_en <= 0; + m_cnt_changed <= 0; + m_cnt_done_q <= 0; + //C counter signals reset + usr_c_cnt_lo <= 0; + usr_c_cnt_hi <= 0; + usr_c_cnt_bypass_en <= 0; + usr_c_cnt_odd_duty_div_en <= 0; + any_c_cnt_changed <= 0; + all_c_cnt_done_q <= 0; + c_cnt_done_q <= 0; + //generic signals + dprio_start <= 0; + dprio_temp_m_n_c_readdata_1_q <= 0; + dprio_temp_m_n_c_readdata_2_q <= 0; + c_cnt_done_q <= 0; + //DPS signals + usr_up_dn <= 0; + usr_cnt_sel <= 0; + usr_num_shifts <= 0; + dps_changed <= 0; + //manual DPRIO signals + manual_dprio_changed <= 0; + usr_dprio_address <= 0; + usr_dprio_writedata_0 <= 0; + usr_r_w <= 0; + operation_address <= 0; + end + else + begin + if (dprio_temp_read_1) + begin + dprio_temp_m_n_c_readdata_1_q <= dprio_temp_m_n_c_readdata_1_d; + end + if (dprio_temp_read_2) + begin + dprio_temp_m_n_c_readdata_2_q <= dprio_temp_m_n_c_readdata_2_d; + end + if ((dps_done)) dps_changed <= 0; + if (dsm_k_done_d) dsm_k_done_q <= dsm_k_done_d; + if (n_cnt_done_d) n_cnt_done_q <= n_cnt_done_d; + if (m_cnt_done_d) m_cnt_done_q <= m_cnt_done_d; + if (all_c_cnt_done_d) all_c_cnt_done_q <= all_c_cnt_done_d; + if (c_cnt_done_d != 0) c_cnt_done_q <= c_cnt_done_q | c_cnt_done_d; + if (bwctrl_done_d) bwctrl_done_q <= bwctrl_done_d; + if (cp_current_done_d) cp_current_done_q <= cp_current_done_d; + if (vco_done_d) vco_done_q <= vco_done_d; + if (manual_dprio_done_d) manual_dprio_done_q <= manual_dprio_done_d; + + if (dprio_next_state == ONE) + dprio_start <= 0; + if (dprio_write_done) + begin + bwctrl_done_q <= 0; + cp_current_done_q <= 0; + vco_done_q <= 0; + dsm_k_done_q <= 0; + dsm_k_done_q <= 0; + n_cnt_done_q <= 0; + m_cnt_done_q <= 0; + all_c_cnt_done_q <= 0; + c_cnt_done_q <= 0; + dsm_k_changed <= 0; + n_cnt_changed <= 0; + m_cnt_changed <= 0; + any_c_cnt_changed <= 0; + bwctrl_changed <= 0; + cp_current_changed <= 0; + vco_changed <= 0; + manual_dprio_changed <= 0; + manual_dprio_done_q <= 0; + + end + else + begin + dsm_k_changed <= dsm_k_changed; + n_cnt_changed <= n_cnt_changed; + m_cnt_changed <= m_cnt_changed; + any_c_cnt_changed <= any_c_cnt_changed; + manual_dprio_changed <= manual_dprio_changed; + end + + + if(slave_write & !slave_waitrequest) + begin + case(slave_address) + //read in the values here from the user and act on them + DSM_REG: + begin + operation_address <= DSM_REG; + usr_k_value <= slave_writedata[31:0]; + dsm_k_changed <= 1'b1; + dsm_k_done_q <= 0; + dprio_start <= 1'b1; + end + N_REG: + begin + operation_address <= N_REG; + usr_n_cnt_lo <= slave_writedata[7:0]; + usr_n_cnt_hi <= slave_writedata[15:8]; + usr_n_cnt_bypass_en <= slave_writedata[16]; + usr_n_cnt_odd_duty_div_en <= slave_writedata[17]; + n_cnt_changed <= 1'b1; + n_cnt_done_q <= 0; + dprio_start <= 1'b1; + end + M_REG: + begin + operation_address <= M_REG; + usr_m_cnt_lo <= slave_writedata[7:0]; + usr_m_cnt_hi <= slave_writedata[15:8]; + usr_m_cnt_bypass_en <= slave_writedata[16]; + usr_m_cnt_odd_duty_div_en <= slave_writedata[17]; + m_cnt_changed <= 1'b1; + m_cnt_done_q <= 0; + dprio_start <= 1'b1; + end + //DPS_REG: + //begin + // operation_address <= DPS_REG; + // usr_num_shifts <= slave_writedata[15:0]; + // usr_up_dn <= slave_writedata[21]; + // dps_changed <= 1; + //end + C_COUNTERS_REG: + begin + operation_address <= C_COUNTERS_REG; + usr_c_cnt_lo <= slave_writedata[7:0]; + usr_c_cnt_hi <= slave_writedata[15:8]; + usr_c_cnt_bypass_en <= slave_writedata[16]; + usr_c_cnt_odd_duty_div_en <= slave_writedata[17]; + any_c_cnt_changed <= 1'b1; + all_c_cnt_done_q <= 0; + dprio_start <= 1'b1; + end + BWCTRL_REG: + begin + usr_bwctrl_value <= slave_writedata[3:0]; + bwctrl_changed <= 1'b1; + bwctrl_done_q <= 0; + dprio_start <= 1'b1; + operation_address <= BWCTRL_REG; + end + CP_CURRENT_REG: + begin + usr_cp_current_value <= slave_writedata[2:0]; + cp_current_changed <= 1'b1; + cp_current_done_q <= 0; + dprio_start <= 1'b1; + operation_address <= CP_CURRENT_REG; + end + //VCO_REG: + //begin + // usr_vco_value <= slave_writedata[0]; + // vco_changed <= 1'b1; + // vco_done_q <= 0; + // dprio_start <= 1'b1; + // operation_address <= VCO_REG; + //end + //ANY_DPRIO: + //begin + // operation_address <= ANY_DPRIO; + // manual_dprio_changed <= 1'b1; + // usr_dprio_address <= slave_writedata[5:0]; + // usr_dprio_writedata_0 <= slave_writedata[21:6]; + // usr_r_w <= slave_writedata[22]; + // manual_dprio_done_q <= 0; + // dprio_start <= 1'b1; + //end + endcase + end + end + end + //C Counter assigning values to the 2-d array of values for each C counter + + reg [4:0] j; + always @(posedge clk) + begin + + if (reset) + begin + c_cnt_changed[17:0] <= 0; + for (j = 0; j < number_of_counters; j = j + 1'b1) + begin : c_cnt_reset + temp_c_cnt_bypass_en[j] <= 0; + temp_c_cnt_odd_duty_div_en[j] <= 0; + end + end + else + begin + if (dprio_write_done) + begin + c_cnt_changed <= 0; + end + if (any_c_cnt_changed && (operation_address == C_COUNTERS_REG)) + begin + temp_c_cnt_bypass_en [5] <= usr_c_cnt_bypass_en; + temp_c_cnt_odd_duty_div_en [5] <= usr_c_cnt_odd_duty_div_en; + c_cnt_changed [5] <= 1'b1; + end + end + end + + + //logic to handle which writes the user indicated and wants to start. + assign usr_valid_changes =dsm_k_changed| any_c_cnt_changed |n_cnt_changed | m_cnt_changed | dps_changed_valid |manual_dprio_changed |cp_current_changed|bwctrl_changed|vco_changed; + + + //start the reconfig operations by writing to the DPRIO + reg break_loop; + reg [4:0] i; + always @(*) + begin + dprio_temp_read_1 = 0; + dprio_temp_read_2 = 0; + dprio_temp_m_n_c_readdata_1_d = 0; + dprio_temp_m_n_c_readdata_2_d = 0; + break_loop = 0; + dprio_next_state = DPRIO_IDLE; + avmm_dprio_write = 0; + avmm_dprio_read = 0; + avmm_dprio_address = 0; + avmm_dprio_writedata = 0; + avmm_dprio_byteen = 0; + dprio_write_done = 1; + manual_dprio_done_d = 0; + n_cnt_done_d = 0; + dsm_k_done_d = 0; + dsm_k_ready_false_done_d = 0; + m_cnt_done_d = 0; + c_cnt_done_d[17:0] = 0; + all_c_cnt_done_d = 0; + bwctrl_done_d = 0; + cp_current_done_d = 0; + vco_done_d = 0; + i = 0; + + // Deassert dprio_write_done so it doesn't reset mif_reg_asserted (toggled writes) + if (dprio_start) + dprio_write_done = 0; + + if (current_state == WAIT_ON_LOCK) + begin + case (dprio_cur_state) + ONE: + begin + if (n_cnt_changed & !n_cnt_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + dprio_next_state = TWO; + avmm_dprio_address = N_CNT_DIV_ADDR; + avmm_dprio_writedata[7:0] = usr_n_cnt_lo; + avmm_dprio_writedata[15:8] = usr_n_cnt_hi; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + dprio_next_state = TWO; + avmm_dprio_address = M_CNT_DIV_ADDR; + avmm_dprio_writedata[7:0] = usr_m_cnt_lo; + avmm_dprio_writedata[15:8] = usr_m_cnt_hi; + end + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + + for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_write_hilo + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + dprio_write_done = 0; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + dprio_next_state = TWO; + if (fpll_1) avmm_dprio_address = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - i; + else avmm_dprio_address = C_CNT_0_DIV_ADDR + i; + avmm_dprio_writedata[7:0] = usr_c_cnt_lo; + avmm_dprio_writedata[15:8] = usr_c_cnt_hi; + //To break from the loop, since only one counter + //is addressed at a time + break_loop = 1'b1; + end + end + end + else if (dsm_k_changed & !dsm_k_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 0; + dprio_next_state = TWO; + end + else if (bwctrl_changed & !bwctrl_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 0; + dprio_next_state = TWO; + end + else if (cp_current_changed & !cp_current_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 0; + dprio_next_state = TWO; + end + else if (vco_changed & !vco_done_q) + begin + dprio_write_done = 0; + avmm_dprio_write = 0; + dprio_next_state = TWO; + end + else if (manual_dprio_changed & !manual_dprio_done_q) + begin + dprio_write_done = 0; + avmm_dprio_byteen = 2'b11; + dprio_next_state = TWO; + avmm_dprio_write = usr_r_w; + avmm_dprio_address = usr_dprio_address; + avmm_dprio_writedata[15:0] = usr_dprio_writedata_0; + end + else dprio_next_state = DPRIO_IDLE; + end + + TWO: + begin + //handle reading the two setting bits on n_cnt, then + //writing them back while preserving other bits. + //Issue two consecutive reads then wait; readLatency=3 + dprio_write_done = 0; + dprio_next_state = THREE; + avmm_dprio_byteen = 2'b11; + avmm_dprio_read = 1'b1; + if (n_cnt_changed & !n_cnt_done_q) + begin + avmm_dprio_address = N_CNT_BYPASS_EN_ADDR; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + avmm_dprio_address = M_CNT_BYPASS_EN_ADDR; + end + + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + for (i = 5; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_read_bypass + if (fpll_1) + begin + if (i > 13) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; + break_loop = 1'b1; + end + end + end + else + begin + if (i < 4) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; + break_loop = 1'b1; + end + end + end + end + end + //reading the K ready 16 bit word. Need to write 0 to it + //afterwards to indicate that K has not been done writing + else if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_READY_ADDR; + dprio_next_state = FOUR; + end + else if (bwctrl_changed & !bwctrl_done_q) + begin + avmm_dprio_address = BWCTRL_ADDR; + dprio_next_state = FOUR; + end + else if (cp_current_changed & !cp_current_done_q) + begin + avmm_dprio_address = CP_CURRENT_ADDR; + dprio_next_state = FOUR; + end + else if (vco_changed & !vco_done_q) + begin + avmm_dprio_address = VCO_ADDR; + dprio_next_state = FOUR; + end + else if (manual_dprio_changed & !manual_dprio_done_q) + begin + avmm_dprio_read = ~usr_r_w; + avmm_dprio_address = usr_dprio_address; + dprio_next_state = DPRIO_DONE; + end + else dprio_next_state = DPRIO_IDLE; + end + THREE: + begin + dprio_write_done = 0; + avmm_dprio_byteen = 2'b11; + avmm_dprio_read = 1'b1; + dprio_next_state = FOUR; + if (n_cnt_changed & !n_cnt_done_q) + begin + avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR; + end + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + for (i = 5; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_read_odd_div + if (fpll_1) + begin + if (i > 13) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; + break_loop = 1'b1; + end + end + end + else + begin + if (i < 4) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; + break_loop = 1'b1; + end + end + end + end + end + else dprio_next_state = DPRIO_IDLE; + end + FOUR: + begin + dprio_temp_read_1 = 1'b1; + dprio_write_done = 0; + if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed) + begin + dprio_temp_m_n_c_readdata_1_d = dprio_readdata; + dprio_next_state = FIVE; + end + else dprio_next_state = DPRIO_IDLE; + end + FIVE: + begin + dprio_write_done = 0; + dprio_temp_read_2 = 1'b1; + if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed) + begin + //this is where DSM ready value comes. + //Need to store in a register to be used later + dprio_temp_m_n_c_readdata_2_d = dprio_readdata; + dprio_next_state = SIX; + end + else dprio_next_state = DPRIO_IDLE; + end + SIX: + begin + dprio_write_done = 0; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + dprio_next_state = SEVEN; + avmm_dprio_writedata = dprio_temp_m_n_c_readdata_1_q; + if (n_cnt_changed & !n_cnt_done_q) + begin + avmm_dprio_address = N_CNT_BYPASS_EN_ADDR; + avmm_dprio_writedata[5] = usr_n_cnt_bypass_en; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + avmm_dprio_address = M_CNT_BYPASS_EN_ADDR; + avmm_dprio_writedata[4] = usr_m_cnt_bypass_en; + end + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + for (i = 5; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_write_bypass + if (fpll_1) + begin + if (i > 13) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; + avmm_dprio_writedata[i-14] = temp_c_cnt_bypass_en[i]; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; + avmm_dprio_writedata[i] = temp_c_cnt_bypass_en[i]; + break_loop = 1'b1; + end + end + end + else + begin + if (i < 4) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR; + avmm_dprio_writedata[3-i] = temp_c_cnt_bypass_en[i]; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR; + avmm_dprio_writedata[17-i] = temp_c_cnt_bypass_en[i]; + break_loop = 1'b1; + end + end + end + end + end + else if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_write = 0; + end + else if (bwctrl_changed & !bwctrl_done_q) + begin + avmm_dprio_write = 0; + end + else if (cp_current_changed & !cp_current_done_q) + begin + avmm_dprio_write = 0; + end + else if (vco_changed & !vco_done_q) + begin + avmm_dprio_write = 0; + end + else dprio_next_state = DPRIO_IDLE; + end + SEVEN: + begin + dprio_write_done = 0; + dprio_next_state = EIGHT; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q; + if (n_cnt_changed & !n_cnt_done_q) + begin + avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[5] = usr_n_cnt_odd_duty_div_en; + n_cnt_done_d = 1'b1; + end + else if (m_cnt_changed & !m_cnt_done_q) + begin + avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[4] = usr_m_cnt_odd_duty_div_en; + m_cnt_done_d = 1'b1; + end + + else if (any_c_cnt_changed & !all_c_cnt_done_q) + begin + for (i = 5; (i < number_of_counters) & !break_loop; i = i + 1'b1) + begin : c_cnt_write_odd_div + if (fpll_1) + begin + if (i > 13) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[i-14] = temp_c_cnt_odd_duty_div_en[i]; + c_cnt_done_d[i] = 1'b1; + //have to OR the signals to prevent + //overwriting of previous dones + c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[i] = temp_c_cnt_odd_duty_div_en[i]; + c_cnt_done_d[i] = 1'b1; + c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; + break_loop = 1'b1; + end + end + end + else + begin + if (i < 4) + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[3-i] = temp_c_cnt_odd_duty_div_en[i]; + c_cnt_done_d[i] = 1'b1; + //have to OR the signals to prevent + //overwriting of previous dones + c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; + break_loop = 1'b1; + end + end + else + begin + if (c_cnt_changed[i] & !c_cnt_done_q[i]) + begin + avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR; + avmm_dprio_writedata[17-i] = temp_c_cnt_odd_duty_div_en[i]; + c_cnt_done_d[i] = 1'b1; + c_cnt_done_d = c_cnt_done_d | c_cnt_done_q; + break_loop = 1'b1; + end + end + end + end + end + else if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_READY_ADDR; + avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b0; + dsm_k_ready_false_done_d = 1'b1; + end + else if (bwctrl_changed & !bwctrl_done_q) + begin + avmm_dprio_address = BWCTRL_ADDR; + avmm_dprio_writedata[3:0] = usr_bwctrl_value; + bwctrl_done_d = 1'b1; + end + else if (cp_current_changed & !cp_current_done_q) + begin + avmm_dprio_address = CP_CURRENT_ADDR; + avmm_dprio_writedata[2:0] = usr_cp_current_value; + cp_current_done_d = 1'b1; + end + else if (vco_changed & !vco_done_q) + begin + avmm_dprio_address = VCO_ADDR; + avmm_dprio_writedata[8] = usr_vco_value; + vco_done_d = 1'b1; + end + + + //if all C_cnt that were changed are done, then assert all_c_cnt_done + if (c_cnt_done_d == c_cnt_changed) + all_c_cnt_done_d = 1'b1; + if (n_cnt_changed & n_cnt_done_d) + dprio_next_state = DPRIO_DONE; + if (any_c_cnt_changed & !all_c_cnt_done_d & !all_c_cnt_done_q) + dprio_next_state = ONE; + else if (m_cnt_changed & !m_cnt_done_d & !m_cnt_done_q) + dprio_next_state = ONE; + else if (dsm_k_changed & !dsm_k_ready_false_done_d) + dprio_next_state = TWO; + else if (dsm_k_changed & !dsm_k_done_q) + dprio_next_state = EIGHT; + else if (bwctrl_changed & !bwctrl_done_d) + dprio_next_state = TWO; + else if (cp_current_changed & !cp_current_done_d) + dprio_next_state = TWO; + else if (vco_changed & !vco_done_d) + dprio_next_state = TWO; + else + begin + dprio_next_state = DPRIO_DONE; + dprio_write_done = 1'b1; + end + end + //finish the rest of the DSM reads/writes + //writing k value, writing k_ready to 1. + EIGHT: + begin + dprio_write_done = 0; + dprio_next_state = NINE; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_0; + avmm_dprio_writedata[15:0] = usr_k_value[15:0]; + end + end + NINE: + begin + dprio_write_done = 0; + dprio_next_state = TEN; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_1; + avmm_dprio_writedata[15:0] = usr_k_value[31:16]; + end + end + TEN: + begin + dprio_write_done = 0; + dprio_next_state = ONE; + avmm_dprio_write = 1'b1; + avmm_dprio_byteen = 2'b11; + if (dsm_k_changed & !dsm_k_done_q) + begin + avmm_dprio_address = DSM_K_READY_ADDR; + //already have the readdata for DSM_K_READY_ADDR since we read it + //earlier. Just reuse here + avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q; + avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b1; + dsm_k_done_d = 1'b1; + end + end + DPRIO_DONE: + begin + dprio_write_done = 1'b1; + if (dprio_start) dprio_next_state = DPRIO_IDLE; + else dprio_next_state = DPRIO_DONE; + end + DPRIO_IDLE: + begin + if (dprio_start) dprio_next_state = ONE; + else dprio_next_state = DPRIO_IDLE; + end + default: dprio_next_state = 4'bxxxx; + endcase + end + + end + + + //assert the waitreq signal according to the state of the slave + assign slave_waitrequest = (slave_mode==mode_WR) ? ((locked === 1'b1) ? (((current_state==WAIT_ON_LOCK) & !dprio_write_done) | !dps_done |reset|!dprio_init_done) : 1'b1) : 1'b0; + + + dyn_phase_shift dyn_phase_shift_inst ( + .clk(clk), + .reset(reset), + .phase_done(phase_done), + .pll_start_valid(pll_start_valid), + .dps_changed(dps_changed), + .dps_changed_valid(dps_changed_valid), + .dprio_write_done(dprio_write_done), + .usr_num_shifts(usr_num_shifts), + .usr_cnt_sel(usr_cnt_sel), + .usr_up_dn(usr_up_dn), + .locked(locked), + .dps_done(dps_done), + .phase_en(phase_en), + .up_dn(up_dn), + .cnt_sel(cnt_sel)); + defparam dyn_phase_shift_inst.device_family = device_family; + + assign dprio_clk = clk; + self_reset self_reset_inst (mgmt_reset, clk, reset, dprio_init_reset); + + dprio_mux dprio_mux_inst ( + .init_dprio_address(init_dprio_address), + .init_dprio_read(init_dprio_read), + .init_dprio_byteen(init_dprio_byteen), + .init_dprio_write(init_dprio_write), + .init_dprio_writedata(init_dprio_writedata), + + + .init_atpgmode(init_atpgmode), + .init_mdio_dis(init_mdio_dis), + .init_scanen(init_scanen), + .init_ser_shift_load(init_ser_shift_load), + .dprio_init_done(dprio_init_done), + + // Inputs from avmm master + .avmm_dprio_address(avmm_dprio_address), + .avmm_dprio_read(avmm_dprio_read), + .avmm_dprio_byteen(avmm_dprio_byteen), + .avmm_dprio_write(avmm_dprio_write), + .avmm_dprio_writedata(avmm_dprio_writedata), + + .avmm_atpgmode(avmm_atpgmode), + .avmm_mdio_dis(avmm_mdio_dis), + .avmm_scanen(avmm_scanen), + + // Outputs to fpll + .dprio_address(dprio_address), + .dprio_read(dprio_read), + .dprio_byteen(dprio_byteen), + .dprio_write(dprio_write), + .dprio_writedata(dprio_writedata), + + .atpgmode(dprio_atpgmode), + .mdio_dis(dprio_mdio_dis), + .scanen(dprio_scanen), + .ser_shift_load(dprio_ser_shift_load) + ); + + + fpll_dprio_init fpll_dprio_init_inst ( + .clk(clk), + .reset_n(~reset), + .locked(locked), + + //outputs + .dprio_address(init_dprio_address), + .dprio_read(init_dprio_read), + .dprio_byteen(init_dprio_byteen), + .dprio_write(init_dprio_write), + .dprio_writedata(init_dprio_writedata), + + .atpgmode(init_atpgmode), + .mdio_dis(init_mdio_dis), + .scanen(init_scanen), + .ser_shift_load(init_ser_shift_load), + .dprio_init_done(dprio_init_done)); + + //address luts, to be reconfigged by the Fitter + //FPLL_1 or 0 address lut + generic_lcell_comb lcell_fpll_0_1 ( + .dataa(1'b0), + .combout (fpll_1)); + defparam lcell_fpll_0_1.lut_mask = 64'hAAAAAAAAAAAAAAAA; + defparam lcell_fpll_0_1.dont_touch = "on"; + defparam lcell_fpll_0_1.family = device_family; + + + wire dprio_read_combout; + generic_lcell_comb lcell_dprio_read ( + .dataa(fpll_1), + .datab(dprio_read), + .datac(1'b0), + .datad(1'b0), + .datae(1'b0), + .dataf(1'b0), + .combout (dprio_read_combout)); + defparam lcell_dprio_read.lut_mask = 64'hCCCCCCCCCCCCCCCC; + defparam lcell_dprio_read.dont_touch = "on"; + defparam lcell_dprio_read.family = device_family; + + + + + + //assign reconfig_to_pll signals + assign reconfig_to_pll[0] = dprio_clk; + assign reconfig_to_pll[1] = ~dprio_init_reset; + assign reconfig_to_pll[2] = dprio_write; + assign reconfig_to_pll[3] = dprio_read_combout; + assign reconfig_to_pll[9:4] = dprio_address; + assign reconfig_to_pll[25:10] = dprio_writedata; + assign reconfig_to_pll[27:26] = dprio_byteen; + assign reconfig_to_pll[28] = dprio_ser_shift_load; + assign reconfig_to_pll[29] = dprio_mdio_dis; + assign reconfig_to_pll[30] = phase_en; + assign reconfig_to_pll[31] = up_dn; + assign reconfig_to_pll[36:32] = cnt_sel; + assign reconfig_to_pll[37] = dprio_scanen; + assign reconfig_to_pll[38] = dprio_atpgmode; + //assign reconfig_to_pll[40:37] = clken; + assign reconfig_to_pll[63:39] = 0; + + //assign reconfig_from_pll signals + assign dprio_readdata = reconfig_from_pll [15:0]; + assign locked_orig = reconfig_from_pll [16]; + assign phase_done = reconfig_from_pll [17]; + +endmodule diff --git a/sys/pll_hdmi.v b/sys/pll_hdmi.v index 52a9de9..0cefd25 100644 --- a/sys/pll_hdmi.v +++ b/sys/pll_hdmi.v @@ -1,256 +1,256 @@ -// megafunction wizard: %Altera PLL v17.0% -// GENERATION: XML -// pll_hdmi.v - -// Generated using ACDS version 17.0 598 - -`timescale 1 ps / 1 ps -module pll_hdmi ( - input wire refclk, // refclk.clk - input wire rst, // reset.reset - output wire outclk_0, // outclk0.clk - input wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll - output wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll - ); - - pll_hdmi_0002 pll_hdmi_inst ( - .refclk (refclk), // refclk.clk - .rst (rst), // reset.reset - .outclk_0 (outclk_0), // outclk0.clk - .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll - .reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll - .locked () // (terminated) - ); - -endmodule -// Retrieval info: -// -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// Retrieval info: -// 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megafunction wizard: %Altera PLL v17.0% +// GENERATION: XML +// pll_hdmi.v + +// Generated using ACDS version 17.0 598 + +`timescale 1 ps / 1 ps +module pll_hdmi ( + input wire refclk, // refclk.clk + input wire rst, // reset.reset + output wire outclk_0, // outclk0.clk + input wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll + output wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll + ); + + pll_hdmi_0002 pll_hdmi_inst ( + .refclk (refclk), // refclk.clk + .rst (rst), // reset.reset + .outclk_0 (outclk_0), // outclk0.clk + .reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll + .reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll + .locked () // (terminated) + ); + +endmodule +// Retrieval info: +// +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval 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dc63100..9347c76 100644 --- a/sys/pll_hdmi/pll_hdmi_0002.v +++ b/sys/pll_hdmi/pll_hdmi_0002.v @@ -1,241 +1,241 @@ -`timescale 1ns/10ps -module pll_hdmi_0002( - - // interface 'refclk' - input wire refclk, - - // interface 'reset' - input wire rst, - - // interface 'outclk0' - output wire outclk_0, - - // interface 'locked' - output wire locked, - - // interface 'reconfig_to_pll' - input wire [63:0] reconfig_to_pll, - - // interface 'reconfig_from_pll' - output wire [63:0] reconfig_from_pll -); - - altera_pll #( - .fractional_vco_multiplier("true"), - .reference_clock_frequency("50.0 MHz"), - .pll_fractional_cout(32), - .pll_dsm_out_sel("1st_order"), - .operation_mode("direct"), - .number_of_clocks(1), - .output_clock_frequency0("148.500000 MHz"), - .phase_shift0("0 ps"), - .duty_cycle0(50), - .output_clock_frequency1("0 MHz"), - .phase_shift1("0 ps"), - .duty_cycle1(50), - .output_clock_frequency2("0 MHz"), - .phase_shift2("0 ps"), - .duty_cycle2(50), - .output_clock_frequency3("0 MHz"), - .phase_shift3("0 ps"), - .duty_cycle3(50), - .output_clock_frequency4("0 MHz"), - .phase_shift4("0 ps"), - .duty_cycle4(50), - .output_clock_frequency5("0 MHz"), - .phase_shift5("0 ps"), - .duty_cycle5(50), - .output_clock_frequency6("0 MHz"), - .phase_shift6("0 ps"), - .duty_cycle6(50), - .output_clock_frequency7("0 MHz"), - .phase_shift7("0 ps"), - .duty_cycle7(50), - .output_clock_frequency8("0 MHz"), - .phase_shift8("0 ps"), - .duty_cycle8(50), - .output_clock_frequency9("0 MHz"), - .phase_shift9("0 ps"), - .duty_cycle9(50), - .output_clock_frequency10("0 MHz"), - .phase_shift10("0 ps"), - .duty_cycle10(50), - .output_clock_frequency11("0 MHz"), - .phase_shift11("0 ps"), - .duty_cycle11(50), - .output_clock_frequency12("0 MHz"), - .phase_shift12("0 ps"), - .duty_cycle12(50), - .output_clock_frequency13("0 MHz"), - .phase_shift13("0 ps"), - .duty_cycle13(50), - .output_clock_frequency14("0 MHz"), - .phase_shift14("0 ps"), - .duty_cycle14(50), - .output_clock_frequency15("0 MHz"), - .phase_shift15("0 ps"), - .duty_cycle15(50), - .output_clock_frequency16("0 MHz"), - .phase_shift16("0 ps"), - .duty_cycle16(50), - .output_clock_frequency17("0 MHz"), - .phase_shift17("0 ps"), - .duty_cycle17(50), - .pll_type("Cyclone V"), - .pll_subtype("Reconfigurable"), - .m_cnt_hi_div(4), - .m_cnt_lo_div(4), - .n_cnt_hi_div(256), - .n_cnt_lo_div(256), - .m_cnt_bypass_en("false"), - .n_cnt_bypass_en("true"), - .m_cnt_odd_div_duty_en("false"), - .n_cnt_odd_div_duty_en("false"), - .c_cnt_hi_div0(2), - .c_cnt_lo_div0(1), - .c_cnt_prst0(1), - .c_cnt_ph_mux_prst0(0), - .c_cnt_in_src0("ph_mux_clk"), - .c_cnt_bypass_en0("false"), - .c_cnt_odd_div_duty_en0("true"), - .c_cnt_hi_div1(1), - .c_cnt_lo_div1(1), - .c_cnt_prst1(1), - .c_cnt_ph_mux_prst1(0), - .c_cnt_in_src1("ph_mux_clk"), - .c_cnt_bypass_en1("true"), - .c_cnt_odd_div_duty_en1("false"), - .c_cnt_hi_div2(1), - .c_cnt_lo_div2(1), - .c_cnt_prst2(1), - .c_cnt_ph_mux_prst2(0), - .c_cnt_in_src2("ph_mux_clk"), - .c_cnt_bypass_en2("true"), - .c_cnt_odd_div_duty_en2("false"), - .c_cnt_hi_div3(1), - .c_cnt_lo_div3(1), - .c_cnt_prst3(1), - .c_cnt_ph_mux_prst3(0), - .c_cnt_in_src3("ph_mux_clk"), - .c_cnt_bypass_en3("true"), - .c_cnt_odd_div_duty_en3("false"), - .c_cnt_hi_div4(1), - .c_cnt_lo_div4(1), - .c_cnt_prst4(1), - .c_cnt_ph_mux_prst4(0), - .c_cnt_in_src4("ph_mux_clk"), - .c_cnt_bypass_en4("true"), - .c_cnt_odd_div_duty_en4("false"), - .c_cnt_hi_div5(1), - .c_cnt_lo_div5(1), - .c_cnt_prst5(1), - .c_cnt_ph_mux_prst5(0), - .c_cnt_in_src5("ph_mux_clk"), - .c_cnt_bypass_en5("true"), - .c_cnt_odd_div_duty_en5("false"), - .c_cnt_hi_div6(1), - .c_cnt_lo_div6(1), - .c_cnt_prst6(1), - .c_cnt_ph_mux_prst6(0), - .c_cnt_in_src6("ph_mux_clk"), - .c_cnt_bypass_en6("true"), - .c_cnt_odd_div_duty_en6("false"), - .c_cnt_hi_div7(1), - .c_cnt_lo_div7(1), - .c_cnt_prst7(1), - .c_cnt_ph_mux_prst7(0), - .c_cnt_in_src7("ph_mux_clk"), - .c_cnt_bypass_en7("true"), - .c_cnt_odd_div_duty_en7("false"), - .c_cnt_hi_div8(1), - .c_cnt_lo_div8(1), - .c_cnt_prst8(1), - .c_cnt_ph_mux_prst8(0), - .c_cnt_in_src8("ph_mux_clk"), - .c_cnt_bypass_en8("true"), - .c_cnt_odd_div_duty_en8("false"), - .c_cnt_hi_div9(1), - .c_cnt_lo_div9(1), - .c_cnt_prst9(1), - .c_cnt_ph_mux_prst9(0), - .c_cnt_in_src9("ph_mux_clk"), - .c_cnt_bypass_en9("true"), - .c_cnt_odd_div_duty_en9("false"), - .c_cnt_hi_div10(1), - .c_cnt_lo_div10(1), - .c_cnt_prst10(1), - .c_cnt_ph_mux_prst10(0), - .c_cnt_in_src10("ph_mux_clk"), - .c_cnt_bypass_en10("true"), - .c_cnt_odd_div_duty_en10("false"), - .c_cnt_hi_div11(1), - .c_cnt_lo_div11(1), - .c_cnt_prst11(1), - .c_cnt_ph_mux_prst11(0), - .c_cnt_in_src11("ph_mux_clk"), - .c_cnt_bypass_en11("true"), - .c_cnt_odd_div_duty_en11("false"), - .c_cnt_hi_div12(1), - .c_cnt_lo_div12(1), - .c_cnt_prst12(1), - .c_cnt_ph_mux_prst12(0), - .c_cnt_in_src12("ph_mux_clk"), - .c_cnt_bypass_en12("true"), - .c_cnt_odd_div_duty_en12("false"), - .c_cnt_hi_div13(1), - .c_cnt_lo_div13(1), - .c_cnt_prst13(1), - .c_cnt_ph_mux_prst13(0), - .c_cnt_in_src13("ph_mux_clk"), - .c_cnt_bypass_en13("true"), - .c_cnt_odd_div_duty_en13("false"), - .c_cnt_hi_div14(1), - .c_cnt_lo_div14(1), - .c_cnt_prst14(1), - .c_cnt_ph_mux_prst14(0), - .c_cnt_in_src14("ph_mux_clk"), - .c_cnt_bypass_en14("true"), - .c_cnt_odd_div_duty_en14("false"), - .c_cnt_hi_div15(1), - .c_cnt_lo_div15(1), - .c_cnt_prst15(1), - .c_cnt_ph_mux_prst15(0), - .c_cnt_in_src15("ph_mux_clk"), - .c_cnt_bypass_en15("true"), - .c_cnt_odd_div_duty_en15("false"), - .c_cnt_hi_div16(1), - .c_cnt_lo_div16(1), - .c_cnt_prst16(1), - .c_cnt_ph_mux_prst16(0), - .c_cnt_in_src16("ph_mux_clk"), - .c_cnt_bypass_en16("true"), - .c_cnt_odd_div_duty_en16("false"), - .c_cnt_hi_div17(1), - .c_cnt_lo_div17(1), - .c_cnt_prst17(1), - .c_cnt_ph_mux_prst17(0), - .c_cnt_in_src17("ph_mux_clk"), - .c_cnt_bypass_en17("true"), - .c_cnt_odd_div_duty_en17("false"), - .pll_vco_div(2), - .pll_cp_current(20), - .pll_bwctrl(4000), - .pll_output_clk_frequency("445.499999 MHz"), - .pll_fractional_division("3908420153"), - .mimic_fbclk_type("none"), - .pll_fbclk_mux_1("glb"), - .pll_fbclk_mux_2("m_cnt"), - .pll_m_cnt_in_src("ph_mux_clk"), - .pll_slf_rst("true") - ) altera_pll_i ( - .rst (rst), - .outclk ({outclk_0}), - .locked (locked), - .reconfig_to_pll (reconfig_to_pll), - .fboutclk ( ), - .fbclk (1'b0), - .refclk (refclk), - .reconfig_from_pll (reconfig_from_pll) - ); -endmodule - +`timescale 1ns/10ps +module pll_hdmi_0002( + + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'locked' + output wire locked, + + // interface 'reconfig_to_pll' + input wire [63:0] reconfig_to_pll, + + // interface 'reconfig_from_pll' + output wire [63:0] reconfig_from_pll +); + + altera_pll #( + .fractional_vco_multiplier("true"), + .reference_clock_frequency("50.0 MHz"), + .pll_fractional_cout(32), + .pll_dsm_out_sel("1st_order"), + .operation_mode("direct"), + .number_of_clocks(1), + .output_clock_frequency0("148.500000 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("0 MHz"), + .phase_shift1("0 ps"), + .duty_cycle1(50), + .output_clock_frequency2("0 MHz"), + .phase_shift2("0 ps"), + .duty_cycle2(50), + .output_clock_frequency3("0 MHz"), + .phase_shift3("0 ps"), + .duty_cycle3(50), + .output_clock_frequency4("0 MHz"), + .phase_shift4("0 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("Cyclone V"), + .pll_subtype("Reconfigurable"), + .m_cnt_hi_div(4), + .m_cnt_lo_div(4), + .n_cnt_hi_div(256), + .n_cnt_lo_div(256), + .m_cnt_bypass_en("false"), + .n_cnt_bypass_en("true"), + .m_cnt_odd_div_duty_en("false"), + .n_cnt_odd_div_duty_en("false"), + .c_cnt_hi_div0(2), + .c_cnt_lo_div0(1), + .c_cnt_prst0(1), + .c_cnt_ph_mux_prst0(0), + .c_cnt_in_src0("ph_mux_clk"), + .c_cnt_bypass_en0("false"), + .c_cnt_odd_div_duty_en0("true"), + .c_cnt_hi_div1(1), + .c_cnt_lo_div1(1), + .c_cnt_prst1(1), + .c_cnt_ph_mux_prst1(0), + .c_cnt_in_src1("ph_mux_clk"), + .c_cnt_bypass_en1("true"), + .c_cnt_odd_div_duty_en1("false"), + .c_cnt_hi_div2(1), + .c_cnt_lo_div2(1), + .c_cnt_prst2(1), + .c_cnt_ph_mux_prst2(0), + .c_cnt_in_src2("ph_mux_clk"), + .c_cnt_bypass_en2("true"), + .c_cnt_odd_div_duty_en2("false"), + .c_cnt_hi_div3(1), + .c_cnt_lo_div3(1), + .c_cnt_prst3(1), + .c_cnt_ph_mux_prst3(0), + .c_cnt_in_src3("ph_mux_clk"), + .c_cnt_bypass_en3("true"), + .c_cnt_odd_div_duty_en3("false"), + .c_cnt_hi_div4(1), + .c_cnt_lo_div4(1), + .c_cnt_prst4(1), + .c_cnt_ph_mux_prst4(0), + .c_cnt_in_src4("ph_mux_clk"), + .c_cnt_bypass_en4("true"), + .c_cnt_odd_div_duty_en4("false"), + .c_cnt_hi_div5(1), + .c_cnt_lo_div5(1), + .c_cnt_prst5(1), + .c_cnt_ph_mux_prst5(0), + .c_cnt_in_src5("ph_mux_clk"), + .c_cnt_bypass_en5("true"), + .c_cnt_odd_div_duty_en5("false"), + .c_cnt_hi_div6(1), + .c_cnt_lo_div6(1), + .c_cnt_prst6(1), + .c_cnt_ph_mux_prst6(0), + .c_cnt_in_src6("ph_mux_clk"), + .c_cnt_bypass_en6("true"), + .c_cnt_odd_div_duty_en6("false"), + .c_cnt_hi_div7(1), + .c_cnt_lo_div7(1), + .c_cnt_prst7(1), + .c_cnt_ph_mux_prst7(0), + .c_cnt_in_src7("ph_mux_clk"), + .c_cnt_bypass_en7("true"), + .c_cnt_odd_div_duty_en7("false"), + .c_cnt_hi_div8(1), + .c_cnt_lo_div8(1), + .c_cnt_prst8(1), + .c_cnt_ph_mux_prst8(0), + .c_cnt_in_src8("ph_mux_clk"), + .c_cnt_bypass_en8("true"), + .c_cnt_odd_div_duty_en8("false"), + .c_cnt_hi_div9(1), + .c_cnt_lo_div9(1), + .c_cnt_prst9(1), + .c_cnt_ph_mux_prst9(0), + .c_cnt_in_src9("ph_mux_clk"), + .c_cnt_bypass_en9("true"), + .c_cnt_odd_div_duty_en9("false"), + .c_cnt_hi_div10(1), + .c_cnt_lo_div10(1), + .c_cnt_prst10(1), + .c_cnt_ph_mux_prst10(0), + .c_cnt_in_src10("ph_mux_clk"), + .c_cnt_bypass_en10("true"), + .c_cnt_odd_div_duty_en10("false"), + .c_cnt_hi_div11(1), + .c_cnt_lo_div11(1), + .c_cnt_prst11(1), + .c_cnt_ph_mux_prst11(0), + .c_cnt_in_src11("ph_mux_clk"), + .c_cnt_bypass_en11("true"), + .c_cnt_odd_div_duty_en11("false"), + .c_cnt_hi_div12(1), + .c_cnt_lo_div12(1), + .c_cnt_prst12(1), + .c_cnt_ph_mux_prst12(0), + .c_cnt_in_src12("ph_mux_clk"), + .c_cnt_bypass_en12("true"), + .c_cnt_odd_div_duty_en12("false"), + .c_cnt_hi_div13(1), + .c_cnt_lo_div13(1), + .c_cnt_prst13(1), + .c_cnt_ph_mux_prst13(0), + .c_cnt_in_src13("ph_mux_clk"), + .c_cnt_bypass_en13("true"), + .c_cnt_odd_div_duty_en13("false"), + .c_cnt_hi_div14(1), + .c_cnt_lo_div14(1), + .c_cnt_prst14(1), + .c_cnt_ph_mux_prst14(0), + .c_cnt_in_src14("ph_mux_clk"), + .c_cnt_bypass_en14("true"), + .c_cnt_odd_div_duty_en14("false"), + .c_cnt_hi_div15(1), + .c_cnt_lo_div15(1), + .c_cnt_prst15(1), + .c_cnt_ph_mux_prst15(0), + .c_cnt_in_src15("ph_mux_clk"), + .c_cnt_bypass_en15("true"), + .c_cnt_odd_div_duty_en15("false"), + .c_cnt_hi_div16(1), + .c_cnt_lo_div16(1), + .c_cnt_prst16(1), + .c_cnt_ph_mux_prst16(0), + .c_cnt_in_src16("ph_mux_clk"), + .c_cnt_bypass_en16("true"), + .c_cnt_odd_div_duty_en16("false"), + .c_cnt_hi_div17(1), + .c_cnt_lo_div17(1), + .c_cnt_prst17(1), + .c_cnt_ph_mux_prst17(0), + .c_cnt_in_src17("ph_mux_clk"), + .c_cnt_bypass_en17("true"), + .c_cnt_odd_div_duty_en17("false"), + .pll_vco_div(2), + .pll_cp_current(20), + .pll_bwctrl(4000), + .pll_output_clk_frequency("445.499999 MHz"), + .pll_fractional_division("3908420153"), + .mimic_fbclk_type("none"), + .pll_fbclk_mux_1("glb"), + .pll_fbclk_mux_2("m_cnt"), + .pll_m_cnt_in_src("ph_mux_clk"), + .pll_slf_rst("true") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_0}), + .locked (locked), + .reconfig_to_pll (reconfig_to_pll), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk), + .reconfig_from_pll (reconfig_from_pll) + ); +endmodule + diff --git a/sys/pll_q13.qip b/sys/pll_q13.qip index 13a7ed4..78e7e40 100644 --- a/sys/pll_q13.qip +++ b/sys/pll_q13.qip @@ -1,6 +1,4 @@ set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ] set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ] set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ] diff --git a/sys/scandoubler.v b/sys/scandoubler.v index a1d5a44..81e7c3f 100644 --- a/sys/scandoubler.v +++ b/sys/scandoubler.v @@ -2,7 +2,7 @@ // scandoubler.v // // Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017-2019 Sorgelig +// Copyright (c) 2017-2021 Alexey Melnikov // // This source file is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published @@ -23,23 +23,20 @@ module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) ( // system interface input clk_vid, - input ce_pix, - output ce_pix_out, - input hq2x, // shifter video interface + input ce_pix, input hs_in, input vs_in, input hb_in, input vb_in, - input [DWIDTH:0] r_in, input [DWIDTH:0] g_in, input [DWIDTH:0] b_in, - input mono, // output interface + output ce_pix_out, output reg hs_out, output vs_out, output hb_out, @@ -109,7 +106,6 @@ Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x .ce_in(ce_x4i), .inputpixel({b_d,g_d,r_d}), - .mono(mono), .disable_hq2x(~hq2x), .reset_frame(vb_in), .reset_line(req_line_reset), diff --git a/sys/scanlines.v b/sys/scanlines.v index 59d29bd..43f890f 100644 --- a/sys/scanlines.v +++ b/sys/scanlines.v @@ -5,11 +5,11 @@ module scanlines #(parameter v2=0) input [1:0] scanlines, input [23:0] din, input hs_in,vs_in, - input de_in, + input de_in,ce_in, output reg [23:0] dout, output reg hs_out,vs_out, - output reg de_out + output reg de_out,ce_out ); reg [1:0] scanline; @@ -56,12 +56,13 @@ end always @(posedge clk) begin reg [23:0] dout1, dout2; - reg de1,de2,vs1,vs2,hs1,hs2; + reg de1,de2,vs1,vs2,hs1,hs2,ce1,ce2; dout <= dout2; dout2 <= dout1; dout1 <= d; vs_out <= vs2; vs2 <= vs1; vs1 <= vs_in; hs_out <= hs2; hs2 <= hs1; hs1 <= hs_in; de_out <= de2; de2 <= de1; de1 <= de_in; + ce_out <= ce2; ce2 <= ce1; ce1 <= ce_in; end endmodule diff --git a/sys/sd_card.sv b/sys/sd_card.sv index 734bd16..417d8d4 100644 --- a/sys/sd_card.sv +++ b/sys/sd_card.sv @@ -1,537 +1,463 @@ -// -// sd_card.v -// -// Copyright (c) 2014 Till Harbaum -// Copyright (c) 2015-2018 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the Lesser GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// http://elm-chan.org/docs/mmc/mmc_e.html -// -///////////////////////////////////////////////////////////////////////// - -// -// Made module syncrhronous. Total code refactoring. (Sorgelig) -// clk_spi must be at least 4 x sck for proper work. - -module sd_card #(parameter WIDE = 0) -( - input clk_sys, - input reset, - - input sdhc, - - output [31:0] sd_lba, - output reg sd_rd, - output reg sd_wr, - input sd_ack, - input sd_ack_conf, - - input [AW:0] sd_buff_addr, - input [DW:0] sd_buff_dout, - output [DW:0] sd_buff_din, - input sd_buff_wr, - - // SPI interface - input clk_spi, - - input ss, - input sck, - input mosi, - output reg miso -); - -localparam AW = WIDE ? 7 : 8; -localparam DW = WIDE ? 15 : 7; - -assign sd_lba = sdhc ? lba : {9'd0, lba[31:9]}; - -wire[31:0] OCR = { 1'b1, sdhc, 30'd0 }; // bit30 = 1 -> high capaciry card (sdhc) // bit31 = 0 -> card power up finished -wire [7:0] READ_DATA_TOKEN = 8'hfe; -wire [7:0] WRITE_DATA_RESPONSE = 8'he5; - -// number of bytes to wait after a command before sending the reply -localparam NCR=3; - -localparam RD_STATE_IDLE = 0; -localparam RD_STATE_WAIT_IO = 1; -localparam RD_STATE_SEND_TOKEN = 2; -localparam RD_STATE_SEND_DATA = 3; -localparam RD_STATE_WAIT_M = 4; - -localparam WR_STATE_IDLE = 0; -localparam WR_STATE_EXP_DTOKEN = 1; -localparam WR_STATE_RECV_DATA = 2; -localparam WR_STATE_RECV_CRC0 = 3; -localparam WR_STATE_RECV_CRC1 = 4; -localparam WR_STATE_SEND_DRESP = 5; -localparam WR_STATE_BUSY = 6; - -sdbuf #(WIDE) buffer -( - .clock_a(clk_sys), - .address_a(sd_buff_addr), - .data_a(sd_buff_dout), - .wren_a(sd_ack & sd_buff_wr), - .q_a(sd_buff_din), - - .clock_b(clk_spi), - .address_b(buffer_ptr), - .data_b(buffer_din), - .wren_b(buffer_wr), - .q_b(buffer_dout) -); - -sdbuf #(WIDE) conf -( - .clock_a(clk_sys), - .address_a(sd_buff_addr), - .data_a(sd_buff_dout), - .wren_a(sd_ack_conf & sd_buff_wr), - - .clock_b(clk_spi), - .address_b(buffer_ptr), - .q_b(config_dout) -); - -reg [31:0] lba, new_lba; -reg [8:0] buffer_ptr; -reg [7:0] buffer_din; -wire [7:0] buffer_dout; -wire [7:0] config_dout; -reg buffer_wr; - -always @(posedge clk_spi) begin - reg [2:0] read_state; - reg [2:0] write_state; - reg [6:0] sbuf; - reg cmd55; - reg [7:0] cmd; - reg [2:0] bit_cnt; - reg [3:0] byte_cnt; - reg [7:0] reply; - reg [7:0] reply0, reply1, reply2, reply3; - reg [3:0] reply_len; - reg tx_finish; - reg rx_finish; - reg old_sck; - reg synced; - reg [5:0] ack; - reg io_ack; - reg [4:0] idle_cnt = 0; - reg [2:0] wait_m_cnt; - - if(buffer_wr & ~&buffer_ptr) buffer_ptr <= buffer_ptr + 1'd1; - buffer_wr <= 0; - - ack <= {ack[4:0], sd_ack}; - if(ack[5:4] == 2'b10) io_ack <= 1; - if(ack[5:4] == 2'b01) {sd_rd,sd_wr} <= 0; - - old_sck <= sck; - - if(~ss) idle_cnt <= 31; - else if(~old_sck && sck && idle_cnt) idle_cnt <= idle_cnt - 1'd1; - - if(reset || !idle_cnt) begin - bit_cnt <= 0; - byte_cnt <= 15; - synced <= 0; - miso <= 1; - sbuf <= 7'b1111111; - tx_finish <= 0; - rx_finish <= 0; - read_state <= RD_STATE_IDLE; - write_state <= WR_STATE_IDLE; - end - - if(old_sck & ~sck & ~ss) begin - tx_finish <= 0; - miso <= 1; // default: send 1's (busy/wait) - - if(byte_cnt == 5+NCR) begin - miso <= reply[~bit_cnt]; - - if(bit_cnt == 7) begin - // these three commands all have a reply_len of 0 and will thus - // not send more than a single reply byte - - // CMD9: SEND_CSD - // CMD10: SEND_CID - if((cmd == 'h49) | (cmd == 'h4a)) - read_state <= RD_STATE_SEND_TOKEN; // jump directly to data transmission - - // CMD17/CMD18 - if((cmd == 'h51) | (cmd == 'h52)) begin - io_ack <= 0; - read_state <= RD_STATE_WAIT_IO; // start waiting for data from io controller - lba <= new_lba; - sd_rd <= 1; // trigger request to io controller - end - end - end - else if((reply_len > 0) && (byte_cnt == 5+NCR+1)) miso <= reply0[~bit_cnt]; - else if((reply_len > 1) && (byte_cnt == 5+NCR+2)) miso <= reply1[~bit_cnt]; - else if((reply_len > 2) && (byte_cnt == 5+NCR+3)) miso <= reply2[~bit_cnt]; - else if((reply_len > 3) && (byte_cnt == 5+NCR+4)) miso <= reply3[~bit_cnt]; - else begin - if(byte_cnt > 5+NCR && read_state==RD_STATE_IDLE && write_state==WR_STATE_IDLE) tx_finish <= 1; - end - - // ---------- read state machine processing ------------- - - case(read_state) - RD_STATE_IDLE: ; // do nothing - - - // waiting for io controller to return data - RD_STATE_WAIT_IO: begin - if(io_ack & (bit_cnt == 7)) read_state <= RD_STATE_SEND_TOKEN; - end - - // send data token - RD_STATE_SEND_TOKEN: begin - miso <= READ_DATA_TOKEN[~bit_cnt]; - - if(bit_cnt == 7) begin - read_state <= RD_STATE_SEND_DATA; // next: send data - buffer_ptr <= 0; - if(cmd == 'h49) buffer_ptr <= 16; - end - end - - // send data - RD_STATE_SEND_DATA: begin - - miso <= ((cmd == 'h49) | (cmd == 'h4A)) ? config_dout[~bit_cnt] : buffer_dout[~bit_cnt]; - - if(bit_cnt == 7) begin - - // sent 512 sector data bytes? - if((cmd == 'h51) & &buffer_ptr) read_state <= RD_STATE_IDLE; - else if((cmd == 'h52) & &buffer_ptr) begin - read_state <= RD_STATE_WAIT_M; - wait_m_cnt <= 0; - end - - // sent 16 cid/csd data bytes? - else if(((cmd == 'h49) | (cmd == 'h4a)) & (&buffer_ptr[3:0])) read_state <= RD_STATE_IDLE; - - // not done yet -> trigger read of next data byte - else buffer_ptr <= buffer_ptr + 1'd1; - end - end - - RD_STATE_WAIT_M: begin - if(bit_cnt == 7) begin - wait_m_cnt <= wait_m_cnt + 1'd1; - if(&wait_m_cnt) begin - lba <= lba + 1; - io_ack <= 0; - sd_rd <= 1; - read_state <= RD_STATE_WAIT_IO; - end - end - end - endcase - - // ------------------ write support ---------------------- - // send write data response - if(write_state == WR_STATE_SEND_DRESP) miso <= WRITE_DATA_RESPONSE[~bit_cnt]; - - // busy after write until the io controller sends ack - if(write_state == WR_STATE_BUSY) miso <= 0; - end - - if(~old_sck & sck & ~ss) begin - - if(synced) bit_cnt <= bit_cnt + 1'd1; - - // assemble byte - if(bit_cnt != 7) begin - sbuf[6:0] <= { sbuf[5:0], mosi }; - - // resync while waiting for token - if(write_state==WR_STATE_EXP_DTOKEN) begin - if(cmd == 'h58) begin - if({sbuf,mosi} == 8'hfe) begin - write_state <= WR_STATE_RECV_DATA; - buffer_ptr <= 0; - bit_cnt <= 0; - end - end - else begin - if({sbuf,mosi} == 8'hfc) begin - write_state <= WR_STATE_RECV_DATA; - buffer_ptr <= 0; - bit_cnt <= 0; - end - if({sbuf,mosi} == 8'hfd) begin - write_state <= WR_STATE_IDLE; - rx_finish <= 1; - bit_cnt <= 0; - end - end - end - end - else begin - // finished reading one byte - // byte counter runs against 15 byte boundary - if(byte_cnt != 15) byte_cnt <= byte_cnt + 1'd1; - - // byte_cnt > 6 -> complete command received - // first byte of valid command is 01xxxxxx - // don't accept new commands once a write or read command has been accepted - if((byte_cnt > 5) & (write_state == WR_STATE_IDLE) & (read_state == RD_STATE_IDLE) && !rx_finish) begin - byte_cnt <= 0; - cmd <= { sbuf, mosi}; - - // set cmd55 flag if previous command was 55 - cmd55 <= (cmd == 'h77); - end - - if((byte_cnt > 5) & (read_state == RD_STATE_WAIT_M) && ({sbuf, mosi} == 8'h4c)) begin - byte_cnt <= 0; - rx_finish <= 0; - cmd <= {sbuf, mosi}; - read_state <= RD_STATE_IDLE; - end - - // parse additional command bytes - if(byte_cnt == 0) new_lba[31:24] <= { sbuf, mosi}; - if(byte_cnt == 1) new_lba[23:16] <= { sbuf, mosi}; - if(byte_cnt == 2) new_lba[15:8] <= { sbuf, mosi}; - if(byte_cnt == 3) new_lba[7:0] <= { sbuf, mosi}; - - // last byte (crc) received, evaluate - if(byte_cnt == 4) begin - - // default: - reply <= 4; // illegal command - reply_len <= 0; // no extra reply bytes - rx_finish <= 1; - - case(cmd) - // CMD0: GO_IDLE_STATE - 'h40: reply <= 1; // ok, busy - - // CMD1: SEND_OP_COND - 'h41: reply <= 0; // ok, not busy - - // CMD8: SEND_IF_COND (V2 only) - 'h48: begin - reply <= 1; // ok, busy - - reply0 <= 'h00; - reply1 <= 'h00; - reply2 <= 'h01; - reply3 <= 'hAA; - reply_len <= 4; - end - - // CMD9: SEND_CSD - 'h49: reply <= 0; // ok - - // CMD10: SEND_CID - 'h4a: reply <= 0; // ok - - // CMD12: STOP_TRANSMISSION - 'h4c: reply <= 0; // ok - - // CMD13: SEND_STATUS - 'h4d: begin - reply <= 'h00; // ok - reply0 <='h00; - reply_len <= 1; - end - - // CMD16: SET_BLOCKLEN - 'h50: begin - // we only support a block size of 512 - if(new_lba == 512) reply <= 0; // ok - else reply <= 'h40; // parmeter error - end - - // CMD17: READ_SINGLE_BLOCK - 'h51: reply <= 0; // ok - - // CMD18: READ_MULTIPLE - 'h52: reply <= 0; // ok - // ACMD23: SET_WR_BLK_ERASE_COUNT - 'h57: reply <= 0; //ok - - // CMD24: WRITE_BLOCK - 'h58, - // CMD25: WRITE_MULTIPLE - 'h59: begin - reply <= 0; // ok - write_state <= WR_STATE_EXP_DTOKEN; // expect data token - rx_finish <=0; - lba <= new_lba; - end - - // ACMD41: APP_SEND_OP_COND - 'h69: if(cmd55) reply <= 0; // ok, not busy - - // CMD55: APP_COND - 'h77: reply <= 1; // ok, busy - - // CMD58: READ_OCR - 'h7a: begin - reply <= 0; // ok - - reply0 <= OCR[31:24]; // bit 30 = 1 -> high capacity card - reply1 <= OCR[23:16]; - reply2 <= OCR[15:8]; - reply3 <= OCR[7:0]; - reply_len <= 4; - end - - // CMD59: CRC_ON_OFF - 'h7b: reply <= 0; // ok - endcase - end - - // ---------- handle write ----------- - case(write_state) - // do nothing in idle state - WR_STATE_IDLE: ; - - // waiting for data token - WR_STATE_EXP_DTOKEN: begin - buffer_ptr <= 0; - if(cmd == 'h58) begin - if({sbuf,mosi} == 8'hfe) write_state <= WR_STATE_RECV_DATA; - end - else begin - if({sbuf,mosi} == 8'hfc) write_state <= WR_STATE_RECV_DATA; - if({sbuf,mosi} == 8'hfd) begin - write_state <= WR_STATE_IDLE; - rx_finish <= 1; - end - end - end - - // transfer 512 bytes - WR_STATE_RECV_DATA: begin - // push one byte into local buffer - buffer_wr <= 1; - buffer_din <= {sbuf, mosi}; - - // all bytes written? - if(&buffer_ptr) write_state <= WR_STATE_RECV_CRC0; - end - - // transfer 1st crc byte - WR_STATE_RECV_CRC0: - write_state <= WR_STATE_RECV_CRC1; - - // transfer 2nd crc byte - WR_STATE_RECV_CRC1: - write_state <= WR_STATE_SEND_DRESP; - - // send data response - WR_STATE_SEND_DRESP: begin - write_state <= WR_STATE_BUSY; - io_ack <= 0; - sd_wr <= 1; - end - - // wait for io controller to accept data - WR_STATE_BUSY: - if(io_ack) begin - if(cmd == 'h59) begin - write_state <= WR_STATE_EXP_DTOKEN; - lba <= lba + 1; - end - else begin - write_state <= WR_STATE_IDLE; - rx_finish <= 1; - end - end - endcase - end - - // wait for first 0 bit until start counting bits - if(!synced && !mosi) begin - synced <= 1; - bit_cnt <= 1; // byte assembly prepare for next time loop - sbuf <= 7'b1111110; // byte assembly prepare for next time loop - rx_finish<= 0; - end else if (synced && tx_finish && rx_finish ) begin - synced <= 0; - bit_cnt <= 0; - rx_finish<= 0; - end - end -end - -endmodule - -module sdbuf #(parameter WIDE) -( - input clock_a, - input [AW:0] address_a, - input [DW:0] data_a, - input wren_a, - output reg [DW:0] q_a, - - input clock_b, - input [8:0] address_b, - input [7:0] data_b, - input wren_b, - output reg [7:0] q_b -); - -localparam AW = WIDE ? 7 : 8; -localparam DW = WIDE ? 15 : 7; - -always@(posedge clock_a) begin - if(wren_a) begin - ram[address_a] <= data_a; - q_a <= data_a; - end - else begin - q_a <= ram[address_a]; - end -end - -generate - if(WIDE) begin - reg [1:0][7:0] ram[1<<8]; - always@(posedge clock_b) begin - if(wren_b) begin - ram[address_b[8:1]][address_b[0]] <= data_b; - q_b <= data_b; - end - else begin - q_b <= ram[address_b[8:1]][address_b[0]]; - end - end - end - else begin - reg [7:0] ram[1<<9]; - always@(posedge clock_b) begin - if(wren_b) begin - ram[address_b] <= data_b; - q_b <= data_b; - end - else begin - q_b <= ram[address_b]; - end - end - end -endgenerate - -endmodule +// +// sd_card.v +// +// Copyright (c) 2014 Till Harbaum +// Copyright (c) 2015-2018 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the Lesser GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// http://elm-chan.org/docs/mmc/mmc_e.html +// +///////////////////////////////////////////////////////////////////////// + +// +// Made module syncrhronous. Total code refactoring. (Sorgelig) +// clk_spi must be at least 2 x sck for proper work. + +module sd_card #(parameter WIDE = 0, OCTAL=0) +( + input clk_sys, + input reset, + + input sdhc, + input img_mounted, + input [63:0] img_size, + + output reg [31:0] sd_lba, + output reg sd_rd, + output reg sd_wr, + input sd_ack, + + input [AW:0] sd_buff_addr, + input [DW:0] sd_buff_dout, + output [DW:0] sd_buff_din, + input sd_buff_wr, + + // SPI interface + input clk_spi, + + input ss, + input sck, + input [SW:0] mosi, + output reg [SW:0] miso +); + +localparam AW = WIDE ? 7 : 8; +localparam DW = WIDE ? 15 : 7; +localparam SZ = OCTAL ? 8 : 1; +localparam SW = SZ-1; + +localparam DATA_TOKEN_CMD25 = 8'hfc; +localparam STOP_TRAN = 8'hfd; +localparam DATA_TOKEN = 8'hfe; +localparam WRITE_DATA_RESPONSE = 8'he5; + +// number of bytes to wait after a command before sending the reply +localparam NCR = 5+3; // 5 bytes are required (command length) + +localparam RD_STATE_IDLE = 0; +localparam RD_STATE_START = 1; +localparam RD_STATE_WAIT_IO = 2; +localparam RD_STATE_SEND_TOKEN = 3; +localparam RD_STATE_SEND_DATA = 4; +localparam RD_STATE_WAIT_M = 5; + +localparam WR_STATE_IDLE = 0; +localparam WR_STATE_EXP_DTOKEN = 1; +localparam WR_STATE_RECV_DATA = 2; +localparam WR_STATE_RECV_CRC0 = 3; +localparam WR_STATE_RECV_CRC1 = 4; +localparam WR_STATE_SEND_DRESP = 5; +localparam WR_STATE_BUSY = 6; + +localparam PREF_STATE_IDLE = 0; +localparam PREF_STATE_RD = 1; +localparam PREF_STATE_FINISH = 2; + +altsyncram sdbuf +( + .clock0 (clk_sys), + .address_a ({sd_buf,sd_buff_addr}), + .data_a (sd_buff_dout), + .wren_a (sd_ack & sd_buff_wr), + .q_a (sd_buff_din), + + .clock1 (clk_spi), + .address_b ({spi_buf,buffer_ptr}), + .data_b (buffer_din), + .wren_b (buffer_wr), + .q_b (buffer_dout), + + .aclr0(1'b0), + .aclr1(1'b0), + .addressstall_a(1'b0), + .addressstall_b(1'b0), + .byteena_a(1'b1), + .byteena_b(1'b1), + .clocken0(1'b1), + .clocken1(1'b1), + .clocken2(1'b1), + .clocken3(1'b1), + .eccstatus(), + .rden_a(1'b1), + .rden_b(1'b1) +); +defparam + sdbuf.numwords_a = 1<<(AW+3), + sdbuf.widthad_a = AW+3, + sdbuf.width_a = DW+1, + sdbuf.numwords_b = 2048, + sdbuf.widthad_b = 11, + sdbuf.width_b = 8, + sdbuf.address_reg_b = "CLOCK1", + sdbuf.clock_enable_input_a = "BYPASS", + sdbuf.clock_enable_input_b = "BYPASS", + sdbuf.clock_enable_output_a = "BYPASS", + sdbuf.clock_enable_output_b = "BYPASS", + sdbuf.indata_reg_b = "CLOCK1", + sdbuf.intended_device_family = "Cyclone V", + sdbuf.lpm_type = "altsyncram", + sdbuf.operation_mode = "BIDIR_DUAL_PORT", + sdbuf.outdata_aclr_a = "NONE", + sdbuf.outdata_aclr_b = "NONE", + sdbuf.outdata_reg_a = "UNREGISTERED", + sdbuf.outdata_reg_b = "UNREGISTERED", + sdbuf.power_up_uninitialized = "FALSE", + sdbuf.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + sdbuf.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + sdbuf.width_byteena_a = 1, + sdbuf.width_byteena_b = 1, + sdbuf.wrcontrol_wraddress_reg_b = "CLOCK1"; + +reg [26:0] csd_size; +reg csd_sdhc; +always @(posedge clk_sys) begin + if (img_mounted) begin + csd_sdhc <= sdhc; + if (sdhc) begin + csd_size[0] <= 0; + csd_size[22:1] <= img_size[40:19]; // in 512K units + csd_size[26:23] <= 0; + end + else begin + csd_size[2:0] <= 7; // C_SIZE_MULT + csd_size[14:3] <= 12'b101101101101; + csd_size[26:15] <= img_size[29:18]; // in 256K units ((2**(C_SIZE_MULT+2))*512) + end + end +end + +wire [127:0] CSD = {1'b0,csd_sdhc,6'h00,8'h0e,8'h00,8'h32,8'h5b,8'h59,6'h00,csd_size,7'h7f,8'h80,8'h0a,8'h40,8'h40,8'hf1}; +wire [127:0] CID = {8'hcd,8'hc7,8'h00,8'h93,8'h6f,8'h2f,8'h73,8'h00,8'h00,8'h44,8'h32,8'h38,8'h34,8'h00,8'h00,8'h3e}; + +reg [8:0] buffer_ptr; +reg [7:0] buffer_din; +wire [7:0] buffer_dout; +reg buffer_wr; + +reg [1:0] sd_buf, spi_buf; + +reg [6:0] sbuf; +reg [2:0] bit_cnt; + +wire last_bit = &bit_cnt || OCTAL; +wire [7:0] ibuf = OCTAL ? mosi : {sbuf,mosi[0]}; + +always @(posedge clk_spi) begin + reg [2:0] read_state; + reg [2:0] write_state; + reg [1:0] pref_state; + reg [5:0] cmd; + reg cmd55; + reg [39:0] reply; + reg [3:0] byte_cnt; + reg old_sck; + reg [2:0] ack; + reg [2:0] wait_m_cnt; + reg [31:0] arg; + + ack[1:0] <= {ack[0],sd_ack}; + if(ack[1] == ack[0]) ack[2] <= ack[1]; + + if(~ack[2] & ack[1]) {sd_rd,sd_wr} <= 0; + if( ack[2] & ~ack[1]) begin + sd_buf <= sd_buf + 1'd1; + sd_lba <= sd_lba + 1; + end + + buffer_wr <= 0; + + if(reset) begin + bit_cnt <= 0; + byte_cnt <= '1; + miso <= '1; + cmd <= 0; + sd_wr <= 0; + sd_rd <= 0; + read_state <= RD_STATE_IDLE; + write_state <= WR_STATE_IDLE; + pref_state <= PREF_STATE_IDLE; + end + else begin + + if(buffer_wr) begin + if(~&buffer_ptr) buffer_ptr <= buffer_ptr + 1'd1; + else begin + spi_buf <= spi_buf + 1'd1; + sd_wr <= 1; + end + end + + case(pref_state) + PREF_STATE_IDLE: + if(((sd_buf - spi_buf) <= 1) && (read_state != RD_STATE_IDLE) && (cmd == 17 || cmd == 18)) begin + sd_rd <= 1; + pref_state <= PREF_STATE_RD; + end + + PREF_STATE_RD: + if(read_state == RD_STATE_IDLE) begin + pref_state <= PREF_STATE_IDLE; + end + else if(ack[2] & ~ack[1]) begin + pref_state <= (cmd == 18) ? PREF_STATE_IDLE : PREF_STATE_FINISH; + end + + PREF_STATE_FINISH: + if(read_state == RD_STATE_IDLE) begin + pref_state <= PREF_STATE_IDLE; + end + endcase + + old_sck <= sck; + if(ss) begin + bit_cnt <= 0; + byte_cnt <= '1; + miso <= '1; + end + else if(old_sck & ~sck) begin + miso <= '1; // default: send 1's (busy/wait) + if(byte_cnt >= NCR) {miso,reply} <= {reply, {SZ{1'b1}}}; + + // ---------- read state machine processing ------------- + case(read_state) + RD_STATE_IDLE: ; + + RD_STATE_START: begin + if(byte_cnt == NCR && last_bit) read_state <= (cmd == 9 || cmd == 10) ? RD_STATE_SEND_TOKEN : RD_STATE_WAIT_IO; + end + + // waiting for io controller to return data + RD_STATE_WAIT_IO: begin + if(sd_buf != spi_buf && last_bit) read_state <= RD_STATE_SEND_TOKEN; + end + + // send data token + RD_STATE_SEND_TOKEN: begin + miso <= DATA_TOKEN[~bit_cnt -:SZ]; + if(last_bit) begin + read_state <= RD_STATE_SEND_DATA; // next: send data + buffer_ptr <= 0; + end + end + + // send data + RD_STATE_SEND_DATA: begin + + miso <= (cmd == 9) ? CSD[{buffer_ptr[3:0],~bit_cnt} -:SZ] : (cmd == 10) ? CID[{buffer_ptr[3:0],~bit_cnt} -:SZ] : buffer_dout[~bit_cnt -:SZ]; + + if(last_bit) begin + + // sent 512 sector data bytes? + if(cmd == 17 && &buffer_ptr) read_state <= RD_STATE_IDLE; + else if(cmd == 18 && &buffer_ptr) begin + read_state <= RD_STATE_WAIT_M; + wait_m_cnt <= 0; + end + + // sent 16 cid/csd data bytes? + else if((cmd == 9 || cmd == 10) && &buffer_ptr[3:0]) read_state <= RD_STATE_IDLE; + + // not done yet -> trigger read of next data byte + else buffer_ptr <= buffer_ptr + 1'd1; + end + end + + RD_STATE_WAIT_M: begin + if(last_bit) begin + wait_m_cnt <= wait_m_cnt + 1'd1; + if(&wait_m_cnt) begin + spi_buf <= spi_buf + 1'd1; + read_state <= RD_STATE_WAIT_IO; + end + end + end + endcase + + // ------------------ write support ---------------------- + // send write data response + if(write_state == WR_STATE_SEND_DRESP) miso <= WRITE_DATA_RESPONSE[~bit_cnt -:SZ]; + + // busy after write until the io controller sends ack + if(write_state == WR_STATE_BUSY) miso <= 0; + end + else if(~old_sck & sck) begin + + sbuf[6:0] <= {sbuf[5:0],mosi[0]}; + bit_cnt <= bit_cnt + SZ[2:0]; + + if(last_bit) begin + // finished reading one byte + // byte counter runs against 15 byte boundary + if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1; + + // byte_cnt > 6 -> complete command received + // first byte of valid command is 01xxxxxx + // don't accept new commands once a write or read command has been accepted + if(byte_cnt > 5 && + ((write_state == WR_STATE_IDLE && read_state == RD_STATE_IDLE && ibuf[7:6] == 1) || + (read_state != RD_STATE_IDLE && ibuf == 8'h4c))) begin + byte_cnt <= 0; + cmd <= ibuf[5:0]; + cmd55 <= (cmd == 55); // set cmd55 flag if previous command was 55 + if(ibuf[5:0] == 12) read_state <= RD_STATE_IDLE; + end + + // parse additional command bytes + if(byte_cnt == 0) arg[31:24] <= ibuf; + if(byte_cnt == 1) arg[23:16] <= ibuf; + if(byte_cnt == 2) arg[15:8] <= ibuf; + if(byte_cnt == 3) arg[7:0] <= ibuf; + + // last byte (crc) received, evaluate + if(byte_cnt == 4) begin + + // default: + reply <= 40'h04FFFFFFFF; // illegal command + + case(cmd) + // CMD0: GO_IDLE_STATE + 0: reply[39:32] <= 1; // ok, busy + + // CMD1: SEND_OP_COND + 1: reply[39:32] <= 0; + + // CMD8: SEND_IF_COND (V2 only) + 8: reply <= 40'h01000001AA; // ok, busy + + // CMD9: SEND_CSD + 9, + // CMD10: SEND_CID + 10: begin + reply[39:32] <= 0; + read_state <= RD_STATE_START; + end + + // CMD12: STOP_TRANSMISSION + 12: reply[39:32] <= 0; + + // CMD13: SEND_STATUS + 13: reply[39:24] <= 16'h0000; + + // CMD16: SET_BLOCKLEN + 16: reply[39:32] <= (arg == 512) ? 8'h00 : 8'h40; // we only support a block size of 512 + + // CMD17: READ_SINGLE_BLOCK + 17, + // CMD18: READ_MULTIPLE + 18: begin + reply[39:32] <= 0; + read_state <= RD_STATE_START; + spi_buf <= 0; + sd_buf <= 0; + sd_lba <= csd_sdhc ? arg : {9'd0, arg[31:9]}; + end + + // ACMD23: SET_WR_BLK_ERASE_COUNT + 23: reply[39:32] <= 0; + + // CMD24: WRITE_BLOCK + 24, + // CMD25: WRITE_MULTIPLE + 25: begin + reply[39:32] <= 0; + write_state <= WR_STATE_EXP_DTOKEN; // expect data token + spi_buf <= 0; + sd_buf <= 0; + sd_lba <= csd_sdhc ? arg : {9'd0, arg[31:9]}; + end + + // ACMD41: APP_SEND_OP_COND + 41: if(cmd55) reply[39:32] <= 0; // ok, not busy + + // CMD55: APP_COND + 55: reply[39:32] <= 1; // ok, busy + + // CMD58: READ_OCR + 58: reply <= { 8'h00, 1'b1, csd_sdhc, 30'd0 }; // bit 30 = 1 -> high capacity card + + // CMD59: CRC_ON_OFF + 59: reply[39:32] <= 0; + endcase + end + + // ---------- handle write ----------- + case(write_state) + // do nothing in idle state + WR_STATE_IDLE: ; + + // waiting for data token + WR_STATE_EXP_DTOKEN: begin + buffer_ptr <= 0; + if(cmd == 24) begin + if(ibuf == DATA_TOKEN) write_state <= WR_STATE_RECV_DATA; + end + else begin + if(ibuf == DATA_TOKEN_CMD25) write_state <= WR_STATE_RECV_DATA; + if(ibuf == STOP_TRAN) write_state <= WR_STATE_IDLE; + end + end + + // transfer 512 bytes + WR_STATE_RECV_DATA: begin + // push one byte into local buffer + buffer_wr <= 1; + buffer_din <= ibuf; + + // all bytes written? + if(&buffer_ptr) write_state <= WR_STATE_RECV_CRC0; + end + + // transfer 1st crc byte + WR_STATE_RECV_CRC0: + write_state <= WR_STATE_RECV_CRC1; + + // transfer 2nd crc byte + WR_STATE_RECV_CRC1: + write_state <= WR_STATE_SEND_DRESP; + + // send data response + WR_STATE_SEND_DRESP: + write_state <= WR_STATE_BUSY; + + // wait for io controller to accept data + WR_STATE_BUSY: + if(spi_buf == sd_buf) write_state <= (cmd == 25) ? WR_STATE_EXP_DTOKEN : WR_STATE_IDLE; + endcase + end + end + end +end + +endmodule diff --git a/sys/shadowmask.sv b/sys/shadowmask.sv new file mode 100644 index 0000000..572679c --- /dev/null +++ b/sys/shadowmask.sv @@ -0,0 +1,136 @@ +module shadowmask +( + input clk, + input clk_sys, + + input cmd_wr, + input [15:0] cmd_in, + + input [23:0] din, + input hs_in,vs_in, + input de_in, + input brd_in, + input enable, + + output reg [23:0] dout, + output reg hs_out,vs_out, + output reg de_out +); + + +reg [4:0] hmax; +reg [4:0] vmax; +reg [7:0] mask_idx; +reg mask_2x; +reg mask_rotate; +reg mask_enable; +reg [10:0] mask_lut[256]; + +always @(posedge clk) begin + reg [4:0] hcount; + reg [4:0] vcount; + reg [3:0] hindex; + reg [3:0] vindex; + reg [4:0] hmax2; + reg [4:0] vmax2; + reg [11:0] pcnt,pde; + reg old_hs, old_vs, old_brd; + reg next_v; + + old_hs <= hs_in; + old_vs <= vs_in; + old_brd<= brd_in; + + // hcount and vcount counts pixel rows and columns + // hindex and vindex half the value of the counters for double size patterns + // hindex2, vindex2 swap the h and v counters for drawing rotated masks + hindex <= mask_2x ? hcount[4:1] : hcount[3:0]; + vindex <= mask_2x ? vcount[4:1] : vcount[3:0]; + mask_idx <= mask_rotate ? {hindex,vindex} : {vindex,hindex}; + + // hmax and vmax store these sizes + // hmax2 and vmax2 swap the values to handle rotation + hmax2 <= ((mask_rotate ? vmax : hmax) << mask_2x) | mask_2x; + vmax2 <= ((mask_rotate ? hmax : vmax) << mask_2x) | mask_2x; + + pcnt <= pcnt+1'd1; + if(old_brd && ~brd_in) pde <= pcnt-4'd3; + + hcount <= hcount+1'b1; + if(hcount == hmax2 || pde == pcnt) hcount <= 0; + + if(~old_brd && brd_in) next_v <= 1; + if(old_vs && ~vs_in) vcount <= 0; + if(old_hs && ~hs_in) begin + vcount <= vcount + next_v; + next_v <= 0; + pcnt <= 0; + if (vcount == vmax2) vcount <= 0; + end +end + +reg [4:0] r_mul, g_mul, b_mul; // 1.4 fixed point multipliers +always @(posedge clk) begin + reg [10:0] lut; + + lut <= mask_lut[mask_idx]; + + r_mul <= 5'b10000; g_mul <= 5'b10000; b_mul <= 5'b10000; // default 100% to all channels + if (mask_enable) begin + r_mul <= lut[10] ? {1'b1,lut[7:4]} : {1'b0,lut[3:0]}; + g_mul <= lut[9] ? {1'b1,lut[7:4]} : {1'b0,lut[3:0]}; + b_mul <= lut[8] ? {1'b1,lut[7:4]} : {1'b0,lut[3:0]}; + end +end + +always @(posedge clk) begin + reg [11:0] vid; + reg [7:0] r1, g1, b1; + reg [7:0] r2, g2, b2; + reg [7:0] r3_x, g3_x, b3_x; // 6.25% + 12.5% + reg [8:0] r3_y, g3_y, b3_y; // 25% + 50% + 100% + reg [8:0] r4, g4, b4; + + // C1 - data input + {r1,g1,b1} <= din; + vid <= {vid[8:0],vs_in, hs_in, de_in}; + + // C2 - relax timings + {r2,g2,b2} <= {r1,g1,b1}; + + // C3 - perform multiplications + r3_x <= ({4{r_mul[0]}} & r2[7:4]) + ({8{r_mul[1]}} & r2[7:3]); + r3_y <= ({6{r_mul[2]}} & r2[7:2]) + ({7{r_mul[3]}} & r2[7:1]) + ({9{r_mul[4]}} & r2[7:0]); + g3_x <= ({4{g_mul[0]}} & g2[7:4]) + ({8{g_mul[1]}} & g2[7:3]); + g3_y <= ({6{g_mul[2]}} & g2[7:2]) + ({7{g_mul[3]}} & g2[7:1]) + ({9{g_mul[4]}} & g2[7:0]); + b3_x <= ({4{b_mul[0]}} & b2[7:4]) + ({8{b_mul[1]}} & b2[7:3]); + b3_y <= ({6{b_mul[2]}} & b2[7:2]) + ({7{b_mul[3]}} & b2[7:1]) + ({9{b_mul[4]}} & b2[7:0]); + + // C4 - combine results + r4 <= r3_x + r3_y; + g4 <= g3_x + g3_y; + b4 <= b3_x + b3_y; + + // C5 - clamp and output + dout <= {{8{r4[8]}} | r4[7:0], {8{g4[8]}} | g4[7:0], {8{b4[8]}} | b4[7:0]}; + {vs_out,hs_out,de_out} <= vid[11:9]; +end + +// clock in mask commands +always @(posedge clk_sys) begin + reg m_enable; + reg [7:0] idx; + + if (cmd_wr) begin + case(cmd_in[15:13]) + 3'b000: begin {m_enable, mask_rotate, mask_2x} <= cmd_in[3:1]; idx <= 0; end + 3'b001: vmax <= cmd_in[3:0]; + 3'b010: hmax <= cmd_in[3:0]; + 3'b011: begin mask_lut[idx] <= cmd_in[10:0]; idx <= idx + 1'd1; end + endcase + end + + mask_enable <= m_enable & enable; +end + +endmodule diff --git a/sys/spdif.v b/sys/spdif.v index d50c2da..eee2b08 100644 --- a/sys/spdif.v +++ b/sys/spdif.v @@ -67,6 +67,8 @@ reg spdif_out_q; reg [5:0] parity_count_q; +reg channel_status_bit_q; + //----------------------------------------------------------------- // Subframe Counter //----------------------------------------------------------------- @@ -142,19 +144,20 @@ assign subframe_w[28] = 1'b0; // Valid assign subframe_w[29] = 1'b0; // Timeslots 30 = Channel status bit -assign subframe_w[30] = 1'b0; +assign subframe_w[30] = channel_status_bit_q ; //was constant 1'b0 enabling copy-bit; // Timeslots 31 = Even Parity bit (31:4) assign subframe_w[31] = 1'b0; //----------------------------------------------------------------- -// Preamble +// Preamble and Channel status bit //----------------------------------------------------------------- -localparam PREAMBLE_Z = 8'b00010111; -localparam PREAMBLE_Y = 8'b00100111; -localparam PREAMBLE_X = 8'b01000111; +localparam PREAMBLE_Z = 8'b00010111; // "B" channel A data at start of block +localparam PREAMBLE_Y = 8'b00100111; // "W" channel B data +localparam PREAMBLE_X = 8'b01000111; // "M" channel A data not at start of block reg [7:0] preamble_r; +reg channel_status_bit_r; always @ * begin @@ -168,13 +171,30 @@ begin // Left Channel (but not start of block)? else preamble_r = PREAMBLE_X; // X(M) + + if (subframe_count_q[8:1] == 8'd2) // frame 2 => subframes 4 and 5 => 0 = copy inhibited, 1 = copy permitted + channel_status_bit_r = 1'b1; + else if (subframe_count_q[8:1] == 8'd15) // frame 15 => 0 = no indication, 1 = original media + channel_status_bit_r = 1'b1; + else if (subframe_count_q[8:1] == 8'd25) // frame 24 to 27 => sample frequency, 0100 = 48kHz, 0000 = 44kHz (l2r) + channel_status_bit_r = 1'b1; + else + channel_status_bit_r = 1'b0; // everything else defaults to 0 end always @ (posedge rst_i or posedge clk_i ) -if (rst_i == 1'b1) - preamble_q <= 8'h00; -else if (load_subframe_q) - preamble_q <= preamble_r; +begin + if (rst_i == 1'b1) + begin + preamble_q <= 8'h00; + channel_status_bit_q <= 1'b0; + end + else if (load_subframe_q) + begin + preamble_q <= preamble_r; + channel_status_bit_q <= channel_status_bit_r; + end +end //----------------------------------------------------------------- // Parity Counter diff --git a/sys/sys.qip b/sys/sys.qip index 9a28ae0..ced8e8b 100644 --- a/sys/sys.qip +++ b/sys/sys.qip @@ -3,15 +3,20 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) s set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ] set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) math.sv ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) shadowmask.sv ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) gamma_corr.sv ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_freak.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_freezer.sv ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) arcade_video.v ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) yc_out.sv ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ] @@ -20,9 +25,10 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) a set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) iir_filter.v ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ltc2308.sv ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mt32pi.sv ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mcp23009.sv ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) f2sdram_safe_terminator.sv ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr_svc.sv ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sd_card.sv ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ] +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hps_io.sv ] diff --git a/sys/sys.tcl b/sys/sys.tcl index 6e2b24b..93b6247 100644 --- a/sys/sys.tcl +++ b/sys/sys.tcl @@ -1,226 +1,220 @@ -set_global_assignment -name FAMILY "Cyclone V" -set_global_assignment -name DEVICE 5CSEBA6U23I7 -set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 - -#============================================================ -# ADC -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO -set_location_assignment PIN_U9 -to ADC_CONVST -set_location_assignment PIN_V10 -to ADC_SCK -set_location_assignment PIN_AC4 -to ADC_SDI -set_location_assignment PIN_AD4 -to ADC_SDO - -#============================================================ -# ARDUINO -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*] - -#============================================================ -# I2C LEDS/BUTTONS -#============================================================ -set_location_assignment PIN_U14 -to IO_SCL -set_location_assignment PIN_AG9 -to IO_SDA -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IO_S* -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IO_S* -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to IO_S* - -#============================================================ -# USER PORT -#============================================================ -set_location_assignment PIN_AF17 -to USER_IO[6] -set_location_assignment PIN_AF15 -to USER_IO[5] -set_location_assignment PIN_AG16 -to USER_IO[4] -set_location_assignment PIN_AH11 -to USER_IO[3] -set_location_assignment PIN_AH12 -to USER_IO[2] -set_location_assignment PIN_AH9 -to USER_IO[1] -set_location_assignment PIN_AG11 -to USER_IO[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_IO[*] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to USER_IO[*] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to USER_IO[*] - -#============================================================ -# SDIO_CD or SPDIF_OUT -#============================================================ -set_location_assignment PIN_AH7 -to SDCD_SPDIF -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCD_SPDIF -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCD_SPDIF -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDCD_SPDIF - -#============================================================ -# SDRAM -#============================================================ -set_location_assignment PIN_Y11 -to SDRAM_A[0] -set_location_assignment PIN_AA26 -to SDRAM_A[1] -set_location_assignment PIN_AA13 -to SDRAM_A[2] -set_location_assignment PIN_AA11 -to SDRAM_A[3] -set_location_assignment PIN_W11 -to SDRAM_A[4] -set_location_assignment PIN_Y19 -to SDRAM_A[5] -set_location_assignment PIN_AB23 -to SDRAM_A[6] -set_location_assignment PIN_AC23 -to SDRAM_A[7] -set_location_assignment PIN_AC22 -to SDRAM_A[8] -set_location_assignment PIN_C12 -to SDRAM_A[9] -set_location_assignment PIN_AB26 -to SDRAM_A[10] -set_location_assignment PIN_AD17 -to SDRAM_A[11] -set_location_assignment PIN_D12 -to SDRAM_A[12] -set_location_assignment PIN_Y17 -to SDRAM_BA[0] -set_location_assignment PIN_AB25 -to SDRAM_BA[1] -set_location_assignment PIN_E8 -to SDRAM_DQ[0] -set_location_assignment PIN_V12 -to SDRAM_DQ[1] -set_location_assignment PIN_D11 -to SDRAM_DQ[2] -set_location_assignment PIN_W12 -to SDRAM_DQ[3] -set_location_assignment PIN_AH13 -to SDRAM_DQ[4] -set_location_assignment PIN_D8 -to SDRAM_DQ[5] -set_location_assignment PIN_AH14 -to SDRAM_DQ[6] -set_location_assignment PIN_AF7 -to SDRAM_DQ[7] -set_location_assignment PIN_AE24 -to SDRAM_DQ[8] -set_location_assignment PIN_AD23 -to SDRAM_DQ[9] -set_location_assignment PIN_AE6 -to SDRAM_DQ[10] -set_location_assignment PIN_AE23 -to SDRAM_DQ[11] -set_location_assignment PIN_AG14 -to SDRAM_DQ[12] -set_location_assignment PIN_AD5 -to SDRAM_DQ[13] -set_location_assignment PIN_AF4 -to SDRAM_DQ[14] -set_location_assignment PIN_AH3 -to SDRAM_DQ[15] -set_location_assignment PIN_AG13 -to SDRAM_DQML -set_location_assignment PIN_AF13 -to SDRAM_DQMH -set_location_assignment PIN_AD20 -to SDRAM_CLK -set_location_assignment PIN_AG10 -to SDRAM_CKE -set_location_assignment PIN_AA19 -to SDRAM_nWE -set_location_assignment PIN_AA18 -to SDRAM_nCAS -set_location_assignment PIN_Y18 -to SDRAM_nCS -set_location_assignment PIN_W14 -to SDRAM_nRAS - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_* -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_* -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] -set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_* - -#============================================================ -# SPI SD -#============================================================ -set_location_assignment PIN_AE15 -to SD_SPI_CS -set_location_assignment PIN_AH8 -to SD_SPI_MISO -set_location_assignment PIN_AG8 -to SD_SPI_CLK -set_location_assignment PIN_U13 -to SD_SPI_MOSI -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD_SPI* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_SPI* -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_SPI* - - -#============================================================ -# CLOCK -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 -set_location_assignment PIN_V11 -to FPGA_CLK1_50 -set_location_assignment PIN_Y13 -to FPGA_CLK2_50 -set_location_assignment PIN_E11 -to FPGA_CLK3_50 - -#============================================================ -# HDMI -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_* -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_D[*] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_DE -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_HS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_VS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_CLK -set_location_assignment PIN_U10 -to HDMI_I2C_SCL -set_location_assignment PIN_AA4 -to HDMI_I2C_SDA -set_location_assignment PIN_T13 -to HDMI_I2S -set_location_assignment PIN_T11 -to HDMI_LRCLK -set_location_assignment PIN_U11 -to HDMI_MCLK -set_location_assignment PIN_T12 -to HDMI_SCLK -set_location_assignment PIN_AG5 -to HDMI_TX_CLK -set_location_assignment PIN_AD19 -to HDMI_TX_DE -set_location_assignment PIN_AD12 -to HDMI_TX_D[0] -set_location_assignment PIN_AE12 -to HDMI_TX_D[1] -set_location_assignment PIN_W8 -to HDMI_TX_D[2] -set_location_assignment PIN_Y8 -to HDMI_TX_D[3] -set_location_assignment PIN_AD11 -to HDMI_TX_D[4] -set_location_assignment PIN_AD10 -to HDMI_TX_D[5] -set_location_assignment PIN_AE11 -to HDMI_TX_D[6] -set_location_assignment PIN_Y5 -to HDMI_TX_D[7] -set_location_assignment PIN_AF10 -to HDMI_TX_D[8] -set_location_assignment PIN_Y4 -to HDMI_TX_D[9] -set_location_assignment PIN_AE9 -to HDMI_TX_D[10] -set_location_assignment PIN_AB4 -to HDMI_TX_D[11] -set_location_assignment PIN_AE7 -to HDMI_TX_D[12] -set_location_assignment PIN_AF6 -to HDMI_TX_D[13] -set_location_assignment PIN_AF8 -to HDMI_TX_D[14] -set_location_assignment PIN_AF5 -to HDMI_TX_D[15] -set_location_assignment PIN_AE4 -to HDMI_TX_D[16] -set_location_assignment PIN_AH2 -to HDMI_TX_D[17] -set_location_assignment PIN_AH4 -to HDMI_TX_D[18] -set_location_assignment PIN_AH5 -to HDMI_TX_D[19] -set_location_assignment PIN_AH6 -to HDMI_TX_D[20] -set_location_assignment PIN_AG6 -to HDMI_TX_D[21] -set_location_assignment PIN_AF9 -to HDMI_TX_D[22] -set_location_assignment PIN_AE8 -to HDMI_TX_D[23] -set_location_assignment PIN_T8 -to HDMI_TX_HS -set_location_assignment PIN_AF11 -to HDMI_TX_INT -set_location_assignment PIN_V13 -to HDMI_TX_VS - -#============================================================ -# KEY -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] -set_location_assignment PIN_AH17 -to KEY[0] -set_location_assignment PIN_AH16 -to KEY[1] - -#============================================================ -# LED -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] -set_location_assignment PIN_W15 -to LED[0] -set_location_assignment PIN_AA24 -to LED[1] -set_location_assignment PIN_V16 -to LED[2] -set_location_assignment PIN_V15 -to LED[3] -set_location_assignment PIN_AF26 -to LED[4] -set_location_assignment PIN_AE26 -to LED[5] -set_location_assignment PIN_Y16 -to LED[6] -set_location_assignment PIN_AA23 -to LED[7] - -#============================================================ -# SW -#============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] -set_location_assignment PIN_Y24 -to SW[0] -set_location_assignment PIN_W24 -to SW[1] -set_location_assignment PIN_W21 -to SW[2] -set_location_assignment PIN_W20 -to SW[3] - -set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi -set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart - -set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" - -set_global_assignment -name CDF_FILE jtag.cdf -set_global_assignment -name QIP_FILE sys/sys.qip - +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEBA6U23I7 +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 + +#============================================================ +# ADC +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO + +#============================================================ +# I2C LEDS/BUTTONS +#============================================================ +set_location_assignment PIN_U14 -to IO_SCL +set_location_assignment PIN_AG9 -to IO_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IO_S* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IO_S* +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to IO_S* + +#============================================================ +# USER PORT +#============================================================ +set_location_assignment PIN_AF17 -to USER_IO[6] +set_location_assignment PIN_AF15 -to USER_IO[5] +set_location_assignment PIN_AG16 -to USER_IO[4] +set_location_assignment PIN_AH11 -to USER_IO[3] +set_location_assignment PIN_AH12 -to USER_IO[2] +set_location_assignment PIN_AH9 -to USER_IO[1] +set_location_assignment PIN_AG11 -to USER_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_IO[*] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to USER_IO[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to USER_IO[*] + +#============================================================ +# SDIO_CD or SPDIF_OUT +#============================================================ +set_location_assignment PIN_AH7 -to SDCD_SPDIF +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCD_SPDIF +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCD_SPDIF +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDCD_SPDIF + +#============================================================ +# SDRAM +#============================================================ +set_location_assignment PIN_Y11 -to SDRAM_A[0] +set_location_assignment PIN_AA26 -to SDRAM_A[1] +set_location_assignment PIN_AA13 -to SDRAM_A[2] +set_location_assignment PIN_AA11 -to SDRAM_A[3] +set_location_assignment PIN_W11 -to SDRAM_A[4] +set_location_assignment PIN_Y19 -to SDRAM_A[5] +set_location_assignment PIN_AB23 -to SDRAM_A[6] +set_location_assignment PIN_AC23 -to SDRAM_A[7] +set_location_assignment PIN_AC22 -to SDRAM_A[8] +set_location_assignment PIN_C12 -to SDRAM_A[9] +set_location_assignment PIN_AB26 -to SDRAM_A[10] +set_location_assignment PIN_AD17 -to SDRAM_A[11] +set_location_assignment PIN_D12 -to SDRAM_A[12] +set_location_assignment PIN_Y17 -to SDRAM_BA[0] +set_location_assignment PIN_AB25 -to SDRAM_BA[1] +set_location_assignment PIN_E8 -to SDRAM_DQ[0] +set_location_assignment PIN_V12 -to SDRAM_DQ[1] +set_location_assignment PIN_D11 -to SDRAM_DQ[2] +set_location_assignment PIN_W12 -to SDRAM_DQ[3] +set_location_assignment PIN_AH13 -to SDRAM_DQ[4] +set_location_assignment PIN_D8 -to SDRAM_DQ[5] +set_location_assignment PIN_AH14 -to SDRAM_DQ[6] +set_location_assignment PIN_AF7 -to SDRAM_DQ[7] +set_location_assignment PIN_AE24 -to SDRAM_DQ[8] +set_location_assignment PIN_AD23 -to SDRAM_DQ[9] +set_location_assignment PIN_AE6 -to SDRAM_DQ[10] +set_location_assignment PIN_AE23 -to SDRAM_DQ[11] +set_location_assignment PIN_AG14 -to SDRAM_DQ[12] +set_location_assignment PIN_AD5 -to SDRAM_DQ[13] +set_location_assignment PIN_AF4 -to SDRAM_DQ[14] +set_location_assignment PIN_AH3 -to SDRAM_DQ[15] +set_location_assignment PIN_AG13 -to SDRAM_DQML +set_location_assignment PIN_AF13 -to SDRAM_DQMH +set_location_assignment PIN_AD20 -to SDRAM_CLK +set_location_assignment PIN_AG10 -to SDRAM_CKE +set_location_assignment PIN_AA19 -to SDRAM_nWE +set_location_assignment PIN_AA18 -to SDRAM_nCAS +set_location_assignment PIN_Y18 -to SDRAM_nCS +set_location_assignment PIN_W14 -to SDRAM_nRAS + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_* +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_* +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_* + +#============================================================ +# SPI SD +#============================================================ +set_location_assignment PIN_AE15 -to SD_SPI_CS +set_location_assignment PIN_AH8 -to SD_SPI_MISO +set_location_assignment PIN_AG8 -to SD_SPI_CLK +set_location_assignment PIN_U13 -to SD_SPI_MOSI +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SD_SPI* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_SPI* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_SPI* + + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 + +#============================================================ +# HDMI +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_D[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_DE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_HS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_VS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_CLK +set_location_assignment PIN_U10 -to HDMI_I2C_SCL +set_location_assignment PIN_AA4 -to HDMI_I2C_SDA +set_location_assignment PIN_T13 -to HDMI_I2S +set_location_assignment PIN_T11 -to HDMI_LRCLK +set_location_assignment PIN_U11 -to HDMI_MCLK +set_location_assignment PIN_T12 -to HDMI_SCLK +set_location_assignment PIN_AG5 -to HDMI_TX_CLK +set_location_assignment PIN_AD19 -to HDMI_TX_DE +set_location_assignment PIN_AD12 -to HDMI_TX_D[0] +set_location_assignment PIN_AE12 -to HDMI_TX_D[1] +set_location_assignment PIN_W8 -to HDMI_TX_D[2] +set_location_assignment PIN_Y8 -to HDMI_TX_D[3] +set_location_assignment PIN_AD11 -to HDMI_TX_D[4] +set_location_assignment PIN_AD10 -to HDMI_TX_D[5] +set_location_assignment PIN_AE11 -to HDMI_TX_D[6] +set_location_assignment PIN_Y5 -to HDMI_TX_D[7] +set_location_assignment PIN_AF10 -to HDMI_TX_D[8] +set_location_assignment PIN_Y4 -to HDMI_TX_D[9] +set_location_assignment PIN_AE9 -to HDMI_TX_D[10] +set_location_assignment PIN_AB4 -to HDMI_TX_D[11] +set_location_assignment PIN_AE7 -to HDMI_TX_D[12] +set_location_assignment PIN_AF6 -to HDMI_TX_D[13] +set_location_assignment PIN_AF8 -to HDMI_TX_D[14] +set_location_assignment PIN_AF5 -to HDMI_TX_D[15] +set_location_assignment PIN_AE4 -to HDMI_TX_D[16] +set_location_assignment PIN_AH2 -to HDMI_TX_D[17] +set_location_assignment PIN_AH4 -to HDMI_TX_D[18] +set_location_assignment PIN_AH5 -to HDMI_TX_D[19] +set_location_assignment PIN_AH6 -to HDMI_TX_D[20] +set_location_assignment PIN_AG6 -to HDMI_TX_D[21] +set_location_assignment PIN_AF9 -to HDMI_TX_D[22] +set_location_assignment PIN_AE8 -to HDMI_TX_D[23] +set_location_assignment PIN_T8 -to HDMI_TX_HS +set_location_assignment PIN_AF11 -to HDMI_TX_INT +set_location_assignment PIN_V13 -to HDMI_TX_VS + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_location_assignment PIN_AH17 -to KEY[0] +set_location_assignment PIN_AH16 -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_AA23 -to LED[7] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_location_assignment PIN_Y24 -to SW[0] +set_location_assignment PIN_W24 -to SW[1] +set_location_assignment PIN_W21 -to SW[2] +set_location_assignment PIN_W20 -to SW[3] + +set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi +set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart +set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALI2C_X52_Y60_N111 -entity sys_top -to hdmi_i2c + +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" + +set_global_assignment -name CDF_FILE jtag.cdf +set_global_assignment -name QIP_FILE sys/sys.qip + diff --git a/sys/sys_analog.tcl b/sys/sys_analog.tcl index 7ffb3ec..692043f 100644 --- a/sys/sys_analog.tcl +++ b/sys/sys_analog.tcl @@ -1,71 +1,71 @@ -#============================================================ -# SDIO -#============================================================ -set_location_assignment PIN_AF25 -to SDIO_DAT[0] -set_location_assignment PIN_AF23 -to SDIO_DAT[1] -set_location_assignment PIN_AD26 -to SDIO_DAT[2] -set_location_assignment PIN_AF28 -to SDIO_DAT[3] -set_location_assignment PIN_AF27 -to SDIO_CMD -set_location_assignment PIN_AH26 -to SDIO_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_* - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_* -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD - -#============================================================ -# VGA -#============================================================ -set_location_assignment PIN_AE17 -to VGA_R[0] -set_location_assignment PIN_AE20 -to VGA_R[1] -set_location_assignment PIN_AF20 -to VGA_R[2] -set_location_assignment PIN_AH18 -to VGA_R[3] -set_location_assignment PIN_AH19 -to VGA_R[4] -set_location_assignment PIN_AF21 -to VGA_R[5] - -set_location_assignment PIN_AE19 -to VGA_G[0] -set_location_assignment PIN_AG15 -to VGA_G[1] -set_location_assignment PIN_AF18 -to VGA_G[2] -set_location_assignment PIN_AG18 -to VGA_G[3] -set_location_assignment PIN_AG19 -to VGA_G[4] -set_location_assignment PIN_AG20 -to VGA_G[5] - -set_location_assignment PIN_AG21 -to VGA_B[0] -set_location_assignment PIN_AA20 -to VGA_B[1] -set_location_assignment PIN_AE22 -to VGA_B[2] -set_location_assignment PIN_AF22 -to VGA_B[3] -set_location_assignment PIN_AH23 -to VGA_B[4] -set_location_assignment PIN_AH21 -to VGA_B[5] - -set_location_assignment PIN_AH22 -to VGA_HS -set_location_assignment PIN_AG24 -to VGA_VS - -set_location_assignment PIN_AH27 -to VGA_EN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_* - -#============================================================ -# AUDIO -#============================================================ -set_location_assignment PIN_AC24 -to AUDIO_L -set_location_assignment PIN_AE25 -to AUDIO_R -set_location_assignment PIN_AG26 -to AUDIO_SPDIF -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_* -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_* - -#============================================================ -# I/O #1 -#============================================================ -set_location_assignment PIN_Y15 -to LED_USER -set_location_assignment PIN_AA15 -to LED_HDD -set_location_assignment PIN_AG28 -to LED_POWER - -set_location_assignment PIN_AH24 -to BTN_USER -set_location_assignment PIN_AG25 -to BTN_OSD -set_location_assignment PIN_AG23 -to BTN_RESET - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_* -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_* +#============================================================ +# SDIO +#============================================================ +set_location_assignment PIN_AF25 -to SDIO_DAT[0] +set_location_assignment PIN_AF23 -to SDIO_DAT[1] +set_location_assignment PIN_AD26 -to SDIO_DAT[2] +set_location_assignment PIN_AF28 -to SDIO_DAT[3] +set_location_assignment PIN_AF27 -to SDIO_CMD +set_location_assignment PIN_AH26 -to SDIO_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_* + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD + +#============================================================ +# VGA +#============================================================ +set_location_assignment PIN_AE17 -to VGA_R[0] +set_location_assignment PIN_AE20 -to VGA_R[1] +set_location_assignment PIN_AF20 -to VGA_R[2] +set_location_assignment PIN_AH18 -to VGA_R[3] +set_location_assignment PIN_AH19 -to VGA_R[4] +set_location_assignment PIN_AF21 -to VGA_R[5] + +set_location_assignment PIN_AE19 -to VGA_G[0] +set_location_assignment PIN_AG15 -to VGA_G[1] +set_location_assignment PIN_AF18 -to VGA_G[2] +set_location_assignment PIN_AG18 -to VGA_G[3] +set_location_assignment PIN_AG19 -to VGA_G[4] +set_location_assignment PIN_AG20 -to VGA_G[5] + +set_location_assignment PIN_AG21 -to VGA_B[0] +set_location_assignment PIN_AA20 -to VGA_B[1] +set_location_assignment PIN_AE22 -to VGA_B[2] +set_location_assignment PIN_AF22 -to VGA_B[3] +set_location_assignment PIN_AH23 -to VGA_B[4] +set_location_assignment PIN_AH21 -to VGA_B[5] + +set_location_assignment PIN_AH22 -to VGA_HS +set_location_assignment PIN_AG24 -to VGA_VS + +set_location_assignment PIN_AH27 -to VGA_EN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_* + +#============================================================ +# AUDIO +#============================================================ +set_location_assignment PIN_AC24 -to AUDIO_L +set_location_assignment PIN_AE25 -to AUDIO_R +set_location_assignment PIN_AG26 -to AUDIO_SPDIF +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_* +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_* + +#============================================================ +# I/O #1 +#============================================================ +set_location_assignment PIN_Y15 -to LED_USER +set_location_assignment PIN_AA15 -to LED_HDD +set_location_assignment PIN_AG28 -to LED_POWER + +set_location_assignment PIN_AH24 -to BTN_USER +set_location_assignment PIN_AG25 -to BTN_OSD +set_location_assignment PIN_AG23 -to BTN_RESET + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_* diff --git a/sys/sys_dual_sdram.tcl b/sys/sys_dual_sdram.tcl index 06124e7..cf90eab 100644 --- a/sys/sys_dual_sdram.tcl +++ b/sys/sys_dual_sdram.tcl @@ -1,50 +1,51 @@ -#============================================================ -# Secondary SDRAM -#============================================================ -set_location_assignment PIN_Y15 -to SDRAM2_DQ[0] -set_location_assignment PIN_AC24 -to SDRAM2_DQ[1] -set_location_assignment PIN_AA15 -to SDRAM2_DQ[2] -set_location_assignment PIN_AD26 -to SDRAM2_DQ[3] -set_location_assignment PIN_AG28 -to SDRAM2_DQ[4] -set_location_assignment PIN_AF28 -to SDRAM2_DQ[5] -set_location_assignment PIN_AE25 -to SDRAM2_DQ[6] -set_location_assignment PIN_AF27 -to SDRAM2_DQ[7] -set_location_assignment PIN_AG26 -to SDRAM2_DQ[14] -set_location_assignment PIN_AH27 -to SDRAM2_DQ[15] - -set_location_assignment PIN_AG25 -to SDRAM2_DQ[13] -set_location_assignment PIN_AH26 -to SDRAM2_DQ[12] -set_location_assignment PIN_AH24 -to SDRAM2_DQ[11] -set_location_assignment PIN_AF25 -to SDRAM2_DQ[10] -set_location_assignment PIN_AG23 -to SDRAM2_DQ[9] -set_location_assignment PIN_AF23 -to SDRAM2_DQ[8] -set_location_assignment PIN_AG24 -to SDRAM2_A[12] -set_location_assignment PIN_AH22 -to SDRAM2_CLK -set_location_assignment PIN_AH21 -to SDRAM2_A[9] -set_location_assignment PIN_AG21 -to SDRAM2_A[11] -set_location_assignment PIN_AH23 -to SDRAM2_A[7] -set_location_assignment PIN_AA20 -to SDRAM2_A[8] -set_location_assignment PIN_AF22 -to SDRAM2_A[5] -set_location_assignment PIN_AE22 -to SDRAM2_A[6] -set_location_assignment PIN_AG20 -to SDRAM2_nWE -set_location_assignment PIN_AF21 -to SDRAM2_A[4] - -set_location_assignment PIN_AG19 -to SDRAM2_nCAS -set_location_assignment PIN_AH19 -to SDRAM2_nRAS -set_location_assignment PIN_AG18 -to SDRAM2_nCS -set_location_assignment PIN_AH18 -to SDRAM2_BA[0] -set_location_assignment PIN_AF18 -to SDRAM2_BA[1] -set_location_assignment PIN_AF20 -to SDRAM2_A[10] -set_location_assignment PIN_AG15 -to SDRAM2_A[0] -set_location_assignment PIN_AE20 -to SDRAM2_A[1] -set_location_assignment PIN_AE19 -to SDRAM2_A[2] -set_location_assignment PIN_AE17 -to SDRAM2_A[3] - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM2_* -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM2_* -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_* -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM2_DQ[*] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM2_DQ[*] -set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM2_* - -set_global_assignment -name VERILOG_MACRO "DUAL_SDRAM=1" +#============================================================ +# Secondary SDRAM +#============================================================ +set_location_assignment PIN_Y15 -to SDRAM2_DQ[0] +set_location_assignment PIN_AC24 -to SDRAM2_DQ[1] +set_location_assignment PIN_AA15 -to SDRAM2_DQ[2] +set_location_assignment PIN_AD26 -to SDRAM2_DQ[3] +set_location_assignment PIN_AG28 -to SDRAM2_DQ[4] +set_location_assignment PIN_AF28 -to SDRAM2_DQ[5] +set_location_assignment PIN_AE25 -to SDRAM2_DQ[6] +set_location_assignment PIN_AF27 -to SDRAM2_DQ[7] +set_location_assignment PIN_AG26 -to SDRAM2_DQ[14] +set_location_assignment PIN_AH27 -to SDRAM2_DQ[15] + +set_location_assignment PIN_AG25 -to SDRAM2_DQ[13] +set_location_assignment PIN_AH26 -to SDRAM2_DQ[12] +set_location_assignment PIN_AH24 -to SDRAM2_DQ[11] +set_location_assignment PIN_AF25 -to SDRAM2_DQ[10] +set_location_assignment PIN_AG23 -to SDRAM2_DQ[9] +set_location_assignment PIN_AF23 -to SDRAM2_DQ[8] +set_location_assignment PIN_AG24 -to SDRAM2_A[12] +set_location_assignment PIN_AH22 -to SDRAM2_CLK +set_location_assignment PIN_AH21 -to SDRAM2_A[9] +set_location_assignment PIN_AG21 -to SDRAM2_A[11] +set_location_assignment PIN_AH23 -to SDRAM2_A[7] +set_location_assignment PIN_AA20 -to SDRAM2_A[8] +set_location_assignment PIN_AF22 -to SDRAM2_A[5] +set_location_assignment PIN_AE22 -to SDRAM2_A[6] +set_location_assignment PIN_AG20 -to SDRAM2_nWE +set_location_assignment PIN_AF21 -to SDRAM2_A[4] + +set_location_assignment PIN_AG19 -to SDRAM2_nCAS +set_location_assignment PIN_AH19 -to SDRAM2_nRAS +set_location_assignment PIN_AG18 -to SDRAM2_nCS +set_location_assignment PIN_AH18 -to SDRAM2_BA[0] +set_location_assignment PIN_AF18 -to SDRAM2_BA[1] +set_location_assignment PIN_AF20 -to SDRAM2_A[10] +set_location_assignment PIN_AG15 -to SDRAM2_A[0] +set_location_assignment PIN_AE20 -to SDRAM2_A[1] +set_location_assignment PIN_AE19 -to SDRAM2_A[2] +set_location_assignment PIN_AE17 -to SDRAM2_A[3] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM2_* +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM2_* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_* +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM2_DQ[*] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM2_DQ[*] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDRAM2_DQ[*] +set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM2_* + +set_global_assignment -name VERILOG_MACRO "MISTER_DUAL_SDRAM=1" diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc index 0954613..ac21334 100644 --- a/sys/sys_top.sdc +++ b/sys/sys_top.sdc @@ -1,54 +1,77 @@ -# Specify root clocks -create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50] -create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50] -create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50] -create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk] -create_clock -period "100.0 MHz" [get_pins -compatibility_mode spi|sclk_out] -name spi_sck - -derive_pll_clocks -derive_clock_uncertainty - -# Decouple different clock groups (to simplify routing) -set_clock_groups -exclusive \ - -group [get_clocks { *|pll|pll_inst|altera_pll_i|*[*].*|divclk}] \ - -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \ - -group [get_clocks { pll_audio|pll_audio_inst|altera_pll_i|*[0].*|divclk}] \ - -group [get_clocks { spi_sck}] \ - -group [get_clocks { *|h2f_user0_clk}] \ - -group [get_clocks { FPGA_CLK1_50 }] \ - -group [get_clocks { FPGA_CLK2_50 }] \ - -group [get_clocks { FPGA_CLK3_50 }] - -set_false_path -from [get_ports {KEY*}] -set_false_path -from [get_ports {BTN_*}] -set_false_path -to [get_ports {LED_*}] -set_false_path -to [get_ports {VGA_*}] -set_false_path -to [get_ports {AUDIO_SPDIF}] -set_false_path -to [get_ports {AUDIO_L}] -set_false_path -to [get_ports {AUDIO_R}] -set_false_path -to {cfg[*]} -set_false_path -from {cfg[*]} -set_false_path -from {VSET[*]} -set_false_path -to {wcalc[*] hcalc[*]} -set_false_path -to {width[*] height[*]} - -set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2 -set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1 -set_false_path -to {*_osd|v_cnt*} -set_false_path -to {*_osd|v_osd_start*} -set_false_path -to {*_osd|v_info_start*} -set_false_path -to {*_osd|h_osd_start*} -set_false_path -from {*_osd|v_osd_start*} -set_false_path -from {*_osd|v_info_start*} -set_false_path -from {*_osd|h_osd_start*} -set_false_path -from {*_osd|rot*} -set_false_path -from {*_osd|dsp_width*} -set_false_path -to {*_osd|half} - -set_false_path -to {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]} -set_false_path -from {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]} -set_false_path -to {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]} -set_false_path -from {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]} -set_false_path -to {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]} -set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]} -set_false_path -from {aflt_* acx* acy* areset*} +# Specify root clocks +create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50] +create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50] +create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50] +create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk] +create_clock -period "100.0 MHz" [get_pins -compatibility_mode spi|sclk_out] -name spi_sck +create_clock -period "10.0 MHz" [get_pins -compatibility_mode hdmi_i2c|out_clk] -name hdmi_sck + +derive_pll_clocks +derive_clock_uncertainty + +# Decouple different clock groups (to simplify routing) +set_clock_groups -exclusive \ + -group [get_clocks { *|pll|pll_inst|altera_pll_i|*[*].*|divclk}] \ + -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \ + -group [get_clocks { pll_audio|pll_audio_inst|altera_pll_i|*[0].*|divclk}] \ + -group [get_clocks { spi_sck}] \ + -group [get_clocks { hdmi_sck}] \ + -group [get_clocks { *|h2f_user0_clk}] \ + -group [get_clocks { FPGA_CLK1_50 }] \ + -group [get_clocks { FPGA_CLK2_50 }] \ + -group [get_clocks { FPGA_CLK3_50 }] + +set_false_path -from [get_ports {KEY*}] +set_false_path -from [get_ports {BTN_*}] +set_false_path -to [get_ports {LED_*}] +set_false_path -to [get_ports {VGA_*}] +set_false_path -from [get_ports {VGA_EN}] +set_false_path -to [get_ports {AUDIO_SPDIF}] +set_false_path -to [get_ports {AUDIO_L}] +set_false_path -to [get_ports {AUDIO_R}] +set_false_path -from {get_ports {SW[*]}} +set_false_path -to {cfg[*]} +set_false_path -from {cfg[*]} +set_false_path -from {VSET[*]} +set_false_path -to {wcalc[*] hcalc[*]} +set_false_path -to {hdmi_width[*] hdmi_height[*]} +set_false_path -to {deb_* btn_en btn_up} + +set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2 +set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1 + +set_false_path -to {*_osd|v_cnt*} +set_false_path -to {*_osd|v_osd_start*} +set_false_path -to {*_osd|v_info_start*} +set_false_path -to {*_osd|h_osd_start*} +set_false_path -from {*_osd|v_osd_start*} +set_false_path -from {*_osd|v_info_start*} +set_false_path -from {*_osd|h_osd_start*} +set_false_path -from {*_osd|rot*} +set_false_path -from {*_osd|dsp_width*} +set_false_path -to {*_osd|half} + +set_false_path -to {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]} +set_false_path -from {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]} +set_false_path -to {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]} +set_false_path -from {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]} +set_false_path -to {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]} +set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]} +set_false_path -from {aflt_* acx* acy* areset* arc*} +set_false_path -from {arx* ary*} +set_false_path -from {vs_line*} +set_false_path -from {ColorBurst_Range* PhaseInc* pal_en cvbs yc_en} + +set_false_path -from {ascal|o_ihsize*} +set_false_path -from {ascal|o_ivsize*} +set_false_path -from {ascal|o_format*} +set_false_path -from {ascal|o_hdown} +set_false_path -from {ascal|o_vdown} +set_false_path -from {ascal|o_hmin* ascal|o_hmax* ascal|o_vmin* ascal|o_vmax* ascal|o_vrrmax* ascal|o_vrr} +set_false_path -from {ascal|o_hdisp* ascal|o_vdisp*} +set_false_path -from {ascal|o_htotal* ascal|o_vtotal*} +set_false_path -from {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_vsend*} +set_false_path -from {ascal|o_hsize* ascal|o_vsize*} + +set_false_path -from {mcp23009|flg_*} +set_false_path -to {sysmem|fpga_interfaces|clocks_resets*} diff --git a/sys/sys_top.v b/sys/sys_top.v index c795a6b..d322d37 100644 --- a/sys/sys_top.v +++ b/sys/sys_top.v @@ -19,18 +19,6 @@ // //============================================================================ -`ifndef ARCADE_SYS - `define USE_DDRAM - `define USE_SDRAM -`endif - -`ifndef USE_DDRAM - `ifdef USE_FB - `define USE_DDRAM - `endif -`endif - - module sys_top ( /////////// CLOCK ////////// @@ -68,7 +56,7 @@ module sys_top output SDRAM_CLK, output SDRAM_CKE, -`ifdef DUAL_SDRAM +`ifdef MISTER_DUAL_SDRAM ////////// SDR #2 ////////// output [12:0] SDRAM2_A, inout [15:0] SDRAM2_DQ, @@ -84,7 +72,7 @@ module sys_top output [5:0] VGA_R, output [5:0] VGA_G, output [5:0] VGA_B, - inout VGA_HS, // VGA_HS is secondary SD card detect when VGA_EN = 1 (inactive) + inout VGA_HS, output VGA_VS, input VGA_EN, // active low @@ -137,34 +125,23 @@ module sys_top ); ////////////////////// Secondary SD /////////////////////////////////// -wire SD_CS, SD_CLK, SD_MOSI; +wire SD_CS, SD_CLK, SD_MOSI, SD_MISO, SD_CD; -`ifdef ARCADE_SYS - assign SD_CS = 1'bZ; - assign SD_CLK = 1'bZ; - assign SD_MOSI = 1'bZ; +`ifndef MISTER_DUAL_SDRAM + assign SD_CD = mcp_en ? mcp_sdcd : SDCD_SPDIF; + assign SD_MISO = SD_CD | (mcp_en ? SD_SPI_MISO : (VGA_EN | SDIO_DAT[0])); + assign SD_SPI_CS = mcp_en ? (mcp_sdcd ? 1'bZ : SD_CS) : (sog & ~cs1 & ~VGA_EN) ? 1'b1 : 1'bZ; + assign SD_SPI_CLK = (~mcp_en | mcp_sdcd) ? 1'bZ : SD_CLK; + assign SD_SPI_MOSI = (~mcp_en | mcp_sdcd) ? 1'bZ : SD_MOSI; + assign {SDIO_CLK,SDIO_CMD,SDIO_DAT} = av_dis ? 6'bZZZZZZ : (mcp_en | (SDCD_SPDIF & ~SW[2])) ? {vga_g,vga_r,vga_b} : {SD_CLK,SD_MOSI,SD_CS,3'bZZZ}; `else - `ifndef DUAL_SDRAM - wire sd_miso = SW[3] | SDIO_DAT[0]; - `else - wire sd_miso = 1; - `endif - wire SD_MISO = mcp_sdcd ? sd_miso : SD_SPI_MISO; + assign SD_CD = mcp_sdcd; + assign SD_MISO = mcp_sdcd | SD_SPI_MISO; + assign SD_SPI_CS = mcp_sdcd ? 1'bZ : SD_CS; + assign SD_SPI_CLK = mcp_sdcd ? 1'bZ : SD_CLK; + assign SD_SPI_MOSI = mcp_sdcd ? 1'bZ : SD_MOSI; `endif -`ifndef DUAL_SDRAM - assign SDIO_DAT[2:1]= 2'bZZ; - assign SDIO_DAT[3] = SW[3] ? 1'bZ : SD_CS; - assign SDIO_CLK = SW[3] ? 1'bZ : SD_CLK; - assign SDIO_CMD = SW[3] ? 1'bZ : SD_MOSI; - assign SD_SPI_CS = mcp_sdcd ? ((~VGA_EN & sog & ~cs1) ? 1'b1 : 1'bZ) : SD_CS; -`else - assign SD_SPI_CS = mcp_sdcd ? 1'bZ : SD_CS; -`endif - -assign SD_SPI_CLK = mcp_sdcd ? 1'bZ : SD_CLK; -assign SD_SPI_MOSI = mcp_sdcd ? 1'bZ : SD_MOSI; - ////////////////////// LEDs/Buttons /////////////////////////////////// reg [7:0] led_overtake = 0; @@ -175,36 +152,59 @@ wire led_d = led_disk[1] ? ~led_disk[0] : ~(led_disk[0] | gp_out[29]); wire led_u = ~led_user; wire led_locked; -`ifndef DUAL_SDRAM - assign LED_POWER = (SW[3] | led_p) ? 1'bZ : 1'b0; - assign LED_HDD = (SW[3] | led_d) ? 1'bZ : 1'b0; - assign LED_USER = (SW[3] | led_u) ? 1'bZ : 1'b0; -`endif - -//LEDs on main board +//LEDs on de10-nano board assign LED = (led_overtake & led_state) | (~led_overtake & {1'b0,led_locked,1'b0, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u}); -wire btn_r, btn_o, btn_u; -`ifdef DUAL_SDRAM - assign {btn_r,btn_o,btn_u} = {mcp_btn[1],mcp_btn[2],mcp_btn[0]}; -`else - assign {btn_r,btn_o,btn_u} = ~{BTN_RESET,BTN_OSD,BTN_USER} | {mcp_btn[1],mcp_btn[2],mcp_btn[0]}; -`endif - wire [2:0] mcp_btn; wire mcp_sdcd; +wire mcp_en; +wire mcp_mode; mcp23009 mcp23009 ( .clk(FPGA_CLK2_50), .btn(mcp_btn), .led({led_p, led_d, led_u}), - .sd_cd(mcp_sdcd), + .flg_sd_cd(mcp_sdcd), + .flg_present(mcp_en), + .flg_mode(mcp_mode), .scl(IO_SCL), .sda(IO_SDA) ); +wire io_dig = mcp_en ? mcp_mode : SW[3]; + +`ifndef MISTER_DUAL_SDRAM + wire av_dis = io_dig | VGA_EN; + assign LED_POWER = av_dis ? 1'bZ : mcp_en ? de1 : led_p ? 1'bZ : 1'b0; + assign LED_HDD = av_dis ? 1'bZ : mcp_en ? (sog & ~cs1) : led_d ? 1'bZ : 1'b0; + //assign LED_USER = av_dis ? 1'bZ : mcp_en ? ~vga_tx_clk : led_u ? 1'bZ : 1'b0; + assign LED_USER = VGA_TX_CLK; + wire BTN_DIS = VGA_EN; +`else + wire BTN_RESET = 1'b1; + wire BTN_OSD = 1'b1; + wire BTN_USER = 1'b1; + wire BTN_DIS = 1'b1; +`endif + +reg BTN_EN = 0; +reg [25:0] btn_timeout = 0; +initial btn_timeout = 0; +always @(posedge FPGA_CLK2_50) begin + reg btn_up = 0; + reg btn_en = 0; + + btn_up <= BTN_RESET & BTN_OSD & BTN_USER; + if(~reset & btn_up & ~&btn_timeout) btn_timeout <= btn_timeout + 1'd1; + btn_en <= ~BTN_DIS; + BTN_EN <= &btn_timeout & btn_en; +end + +wire btn_r = (mcp_en | SW[3]) ? mcp_btn[1] : (BTN_EN & ~BTN_RESET); +wire btn_o = (mcp_en | SW[3]) ? mcp_btn[2] : (BTN_EN & ~BTN_OSD ); +wire btn_u = (mcp_en | SW[3]) ? mcp_btn[0] : (BTN_EN & ~BTN_USER ); reg btn_user, btn_osd; always @(posedge FPGA_CLK2_50) begin @@ -230,21 +230,21 @@ end // gp_in[31] = 0 - quick flag that FPGA is initialized (HPS reads 1 when FPGA is not in user mode) // used to avoid lockups while JTAG loading -wire [31:0] gp_in = {1'b0, btn_user | btn[1], btn_osd | btn[0], SW[3], 8'd0, io_ver, io_ack, io_wide, io_dout}; +wire [31:0] gp_in = {1'b0, btn_user | btn[1], btn_osd | btn[0], io_dig, 8'd0, io_ver, io_ack, io_wide, io_dout | io_dout_sys}; wire [31:0] gp_out; -wire [1:0] io_ver = 1; // 0 - standard MiST I/O (for quick porting of complex MiST cores). 1 - optimized HPS I/O. 2,3 - reserved for future. +wire [1:0] io_ver = 1; // 0 - obsolete. 1 - optimized HPS I/O. 2,3 - reserved for future. wire io_wait; wire io_wide; -wire [15:0] io_dout; +wire [15:0] io_dout; wire [15:0] io_din = gp_outr[15:0]; wire io_clk = gp_outr[17]; wire io_ss0 = gp_outr[18]; wire io_ss1 = gp_outr[19]; wire io_ss2 = gp_outr[20]; -`ifndef DEBUG_NOHDMI -wire io_osd_hdmi = io_ss1 & ~io_ss0; +`ifndef MISTER_DEBUG_NOHDMI + wire io_osd_hdmi = io_ss1 & ~io_ss0; `endif wire io_fpga = ~io_ss1 & io_ss0; @@ -268,7 +268,7 @@ always @(posedge clk_sys) begin gp_outd <= gp_out; end -`ifdef DUAL_SDRAM +`ifdef MISTER_DUAL_SDRAM wire [7:0] core_type = 'hA8; // generic core, dual SDRAM. `else wire [7:0] core_type = 'hA4; // generic core. @@ -285,48 +285,53 @@ cyclonev_hps_interface_mpu_general_purpose h2f_gp reg [15:0] cfg; - reg cfg_set = 0; -wire vga_fb = cfg[12]; -wire [1:0] hdmi_limited = {cfg[11],cfg[8]}; -`ifdef DEBUG_NOHDMI -wire direct_video = 1; +`ifdef MISTER_DEBUG_NOHDMI + wire vga_fb = 0; + wire direct_video = 1; `else -wire direct_video = cfg[10]; + wire vga_fb = cfg[12] | vga_force_scaler; + wire direct_video = cfg[10]; `endif -wire dvi_mode = cfg[7]; wire audio_96k = cfg[6]; wire csync_en = cfg[3]; -wire ypbpr_en = cfg[5]; wire io_osd_vga = io_ss1 & ~io_ss2; -`ifndef DUAL_SDRAM +`ifndef MISTER_DUAL_SDRAM + wire ypbpr_en = cfg[5]; wire sog = cfg[9]; - wire vga_scaler = cfg[2]; + `ifdef MISTER_DEBUG_NOHDMI + wire vga_scaler = 0; + `else + wire vga_scaler = cfg[2] | vga_force_scaler; + `endif `endif reg cfg_custom_t = 0; reg [5:0] cfg_custom_p1; reg [31:0] cfg_custom_p2; -reg [4:0] vol_att = 0; +reg [4:0] vol_att; +initial vol_att = 5'b11111; -reg [6:0] coef_addr; -reg [8:0] coef_data; +reg [11:0] coef_addr; +reg [9:0] coef_data; reg coef_wr = 0; -wire [7:0] ARX, ARY; +wire[12:0] ARX, ARY; reg [11:0] VSET = 0, HSET = 0; reg FREESCALE = 0; reg [2:0] scaler_flt; reg lowlat = 0; -reg cfg_dis = 0; +reg cfg_done = 0; reg vs_wait = 0; reg [11:0] vs_line = 0; reg scaler_out = 0; +reg vrr_mode = 0; +wire hdmi_blackout; reg [31:0] aflt_rate = 7056000; reg [39:0] acx = 4258969; @@ -337,27 +342,37 @@ reg [23:0] acy0 = -24'd6216759; reg [23:0] acy1 = 24'd6143386; reg [23:0] acy2 = -24'd2023767; reg areset = 0; +reg [12:0] arc1x = 0; +reg [12:0] arc1y = 0; +reg [12:0] arc2x = 0; +reg [12:0] arc2y = 0; +reg [15:0] io_dout_sys; always@(posedge clk_sys) begin reg [7:0] cmd; reg has_cmd; - reg old_strobe; reg [7:0] cnt = 0; reg vs_d0,vs_d1,vs_d2; reg [4:0] acx_att; + reg [7:0] fb_crc; - old_strobe <= io_strobe; coef_wr <= 0; +`ifndef MISTER_DEBUG_NOHDMI + shadowmask_wr <= 0; +`endif + if(~io_uio) begin has_cmd <= 0; cmd <= 0; areset <= 0; acx_att <= 0; acx <= acx >> acx_att; + io_dout_sys <= 0; end else - if(~old_strobe & io_strobe) begin + if(io_strobe) begin + io_dout_sys <= 0; if(!has_cmd) begin has_cmd <= 1; cmd <= io_din[7:0]; @@ -374,8 +389,13 @@ always@(posedge clk_sys) begin acy2 <= -24'd2023767; areset <= 1; end + if(io_din[7:0] == 'h20) io_dout_sys <= 'b11; +`ifndef MISTER_DEBUG_NOHDMI + if(io_din[7:0] == 'h40) io_dout_sys <= fb_crc; +`endif end else begin + cnt <= cnt + 1'd1; if(cmd == 1) begin cfg <= io_din; cfg_set <= 1; @@ -383,19 +403,18 @@ always@(posedge clk_sys) begin end if(cmd == 'h20) begin cfg_set <= 0; - cnt <= cnt + 1'd1; if(cnt<8) begin case(cnt[2:0]) - 0: if(WIDTH != io_din[11:0]) WIDTH <= io_din[11:0]; - 1: if(HFP != io_din[11:0]) HFP <= io_din[11:0]; - 2: if(HS != io_din[11:0]) HS <= io_din[11:0]; - 3: if(HBP != io_din[11:0]) HBP <= io_din[11:0]; - 4: if(HEIGHT != io_din[11:0]) HEIGHT <= io_din[11:0]; - 5: if(VFP != io_din[11:0]) VFP <= io_din[11:0]; - 6: if(VS != io_din[11:0]) VS <= io_din[11:0]; - 7: if(VBP != io_din[11:0]) VBP <= io_din[11:0]; + 0: {HDMI_PR,vrr_mode,WIDTH} <= {io_din[15:14], io_din[11:0]}; + 1: HFP <= io_din[11:0]; + 2: HS <= {io_din[15], io_din[11:0]}; + 3: HBP <= io_din[11:0]; + 4: HEIGHT <= io_din[11:0]; + 5: VFP <= io_din[11:0]; + 6: VS <= {io_din[15],io_din[11:0]}; + 7: VBP <= io_din[11:0]; endcase -`ifndef DEBUG_NOHDMI +`ifndef MISTER_DEBUG_NOHDMI if(cnt == 1) begin cfg_custom_p1 <= 0; cfg_custom_p2 <= 0; @@ -410,12 +429,11 @@ always@(posedge clk_sys) begin cfg_custom_t <= ~cfg_custom_t; cnt[2:0] <= 3'b100; end - if(cnt == 8) {lowlat,cfg_dis} <= io_din[15:14]; + if(cnt == 8) {lowlat,cfg_done} <= {io_din[15],1'b1}; `endif end end if(cmd == 'h2F) begin - cnt <= cnt + 1'd1; case(cnt[3:0]) 0: {LFB_EN,LFB_FLT,LFB_FMT} <= {io_din[15], io_din[14], io_din[5:0]}; 1: LFB_BASE[15:0] <= io_din[15:0]; @@ -426,17 +444,20 @@ always@(posedge clk_sys) begin 6: LFB_HMAX <= io_din[11:0]; 7: LFB_VMIN <= io_din[11:0]; 8: LFB_VMAX <= io_din[11:0]; + 9: LFB_STRIDE <= io_din[13:0]; endcase end if(cmd == 'h25) {led_overtake, led_state} <= io_din; if(cmd == 'h26) vol_att <= io_din[4:0]; if(cmd == 'h27) VSET <= io_din[11:0]; - if(cmd == 'h2A) {coef_wr,coef_addr,coef_data} <= {1'b1,io_din}; + if(cmd == 'h2A) begin + if(cnt[0]) {coef_wr,coef_data} <= {1'b1,io_din[9:0]}; + else coef_addr <= io_din[11:0]; + end if(cmd == 'h2B) scaler_flt <= io_din[2:0]; if(cmd == 'h37) {FREESCALE,HSET} <= {io_din[15],io_din[11:0]}; if(cmd == 'h38) vs_line <= io_din[11:0]; if(cmd == 'h39) begin - cnt <= cnt + 1'd1; case(cnt[3:0]) 0: acx_att <= io_din[4:0]; 1: aflt_rate[15:0] <= io_din; @@ -455,9 +476,52 @@ always@(posedge clk_sys) begin 14: acy2[23:16] <= io_din[7:0]; endcase end + if(cmd == 'h3A) begin + case(cnt[3:0]) + 0: arc1x <= io_din[12:0]; + 1: arc1y <= io_din[12:0]; + 2: arc2x <= io_din[12:0]; + 3: arc2y <= io_din[12:0]; + endcase + end +`ifndef MISTER_DEBUG_NOHDMI + if(cmd == 'h3E) {shadowmask_wr,shadowmask_data} <= {1'b1, io_din}; + if(cmd == 'h40) begin + case(cnt[3:0]) + 0: io_dout_sys <= {arxy, arx}; + 1: io_dout_sys <= {arxy, ary}; + 2: io_dout_sys <= {LFB_EN, FB_EN, FB_FMT}; + 3: io_dout_sys <= FB_WIDTH; + 4: io_dout_sys <= FB_HEIGHT; + 5: io_dout_sys <= FB_BASE[15:0]; + 6: io_dout_sys <= FB_BASE[31:16]; + 7: io_dout_sys <= FB_STRIDE; + endcase + end +`endif +`ifndef MISTER_DISABLE_YC + if(cmd == 'h41) begin + case(cnt[3:0]) + 0: {pal_en,cvbs,yc_en} <= io_din[2:0]; + 1: PhaseInc[15:0] <= io_din; + 2: PhaseInc[31:16] <= io_din; + 3: PhaseInc[39:32] <= io_din[7:0]; + 4: ColorBurst_Range[15:0] <= io_din; + 5: ColorBurst_Range[16] <= io_din[0]; + endcase + end +`endif end end +`ifndef MISTER_DEBUG_NOHDMI + fb_crc <= {LFB_EN, FB_EN, FB_FMT} + ^ FB_WIDTH[7:0] ^ FB_WIDTH[11:8] + ^ FB_HEIGHT[7:0] ^ FB_HEIGHT[11:8] + ^ arx[7:0] ^ arx[11:8] ^ arxy + ^ ary[7:0] ^ ary[11:8]; +`endif + vs_d0 <= HDMI_TX_VS; if(vs_d0 == HDMI_TX_VS) vs_d1 <= vs_d0; @@ -467,9 +531,7 @@ end cyclonev_hps_interface_peripheral_uart uart ( - .ri(0) -`ifndef ARCADE_SYS - , + .ri(0), .dsr(uart_dsr), .dcd(uart_dsr), .dtr(uart_dtr), @@ -478,18 +540,6 @@ cyclonev_hps_interface_peripheral_uart uart .rts(uart_rts), .rxd(uart_rxd), .txd(uart_txd) -`endif -); - -wire aspi_sck,aspi_mosi,aspi_ss,aspi_miso; -cyclonev_hps_interface_peripheral_spi_master spi -( - .sclk_out(aspi_sck), - .txd(aspi_mosi), // mosi - .rxd(aspi_miso), // miso - - .ss_0_n(aspi_ss), - .ss_in_n(1) ); wire [63:0] f2h_irq = {video_sync,HDMI_TX_VS}; @@ -533,7 +583,6 @@ sysmem_lite sysmem //DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button. .reset_hps_cold_req(btn_r), -`ifdef USE_DDRAM //64-bit DDR3 RAM access .ram1_clk(ram_clk), .ram1_address(ram_address), @@ -545,7 +594,6 @@ sysmem_lite sysmem .ram1_writedata(ram_writedata), .ram1_byteenable(ram_byteenable), .ram1_write(ram_write), -`endif //64-bit DDR3 RAM access .ram2_clk(clk_audio), @@ -599,11 +647,13 @@ ddr_svc ddr_svc .ram_write(ram2_write), .ram_bcnt(ram2_bcnt), +`ifndef MISTER_DISABLE_ALSA .ch0_addr(alsa_address), .ch0_burst(1), .ch0_data(alsa_readdata), .ch0_req(alsa_req), .ch0_ready(alsa_ready), +`endif .ch1_addr(pal_addr), .ch1_burst(128), @@ -626,102 +676,125 @@ wire [15:0] vbuf_byteenable; wire vbuf_write; wire [23:0] hdmi_data; -wire hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl; +wire hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl, hdmi_brd; +wire freeze; -`ifndef DEBUG_NOHDMI -wire clk_hdmi = hdmi_clk_out; +`ifndef MISTER_DEBUG_NOHDMI + wire clk_hdmi = hdmi_clk_out; -ascal -#( - .RAMBASE(32'h20000000), -`ifndef USE_FB - .PALETTE2("false"), -`endif - .N_DW(128), - .N_AW(28) -) -ascal -( - .reset_na (~reset_req), - .run (1), - .freeze (0), + ascal + #( + .RAMBASE(32'h20000000), + `ifdef MISTER_SMALL_VBUF + .RAMSIZE(32'h00200000), + `else + .RAMSIZE(32'h00800000), + `endif + `ifndef MISTER_FB + .PALETTE2("false"), + `else + `ifndef MISTER_FB_PALETTE + .PALETTE2("false"), + `endif + `endif + `ifdef MISTER_DISABLE_ADAPTIVE + .ADAPTIVE("false"), + `endif + `ifdef MISTER_DOWNSCALE_NN + .DOWNSCALE_NN("true"), + `endif + .FRAC(8), + .N_DW(128), + .N_AW(28) + ) + ascal + ( + .reset_na (~reset_req), + .run (1), + .freeze (freeze), - .i_clk (clk_ihdmi), - .i_ce (ce_hpix), - .i_r (hr_out), - .i_g (hg_out), - .i_b (hb_out), - .i_hs (hhs_fix), - .i_vs (hvs_fix), - .i_fl (f1), - .i_de (hde_emu), - .iauto (1), - .himin (0), - .himax (0), - .vimin (0), - .vimax (0), + .i_clk (clk_ihdmi), + .i_ce (ce_hpix), + .i_r (hr_out), + .i_g (hg_out), + .i_b (hb_out), + .i_hs (hhs_fix), + .i_vs (hvs_fix), + .i_fl (f1), + .i_de (hde_emu), + .iauto (1), + .himin (0), + .himax (0), + .vimin (0), + .vimax (0), - .o_clk (clk_hdmi), - .o_ce (scaler_out), - .o_r (hdmi_data[23:16]), - .o_g (hdmi_data[15:8]), - .o_b (hdmi_data[7:0]), - .o_hs (hdmi_hs), - .o_vs (hdmi_vs), - .o_de (hdmi_de), - .o_vbl (hdmi_vbl), - .o_lltune (lltune), - .htotal (WIDTH + HFP + HBP + HS), - .hsstart (WIDTH + HFP), - .hsend (WIDTH + HFP + HS), - .hdisp (WIDTH), - .hmin (hmin), - .hmax (hmax), - .vtotal (HEIGHT + VFP + VBP + VS), - .vsstart (HEIGHT + VFP), - .vsend (HEIGHT + VFP + VS), - .vdisp (HEIGHT), - .vmin (vmin), - .vmax (vmax), + .o_clk (clk_hdmi), + .o_ce (scaler_out), + .o_r (hdmi_data[23:16]), + .o_g (hdmi_data[15:8]), + .o_b (hdmi_data[7:0]), + .o_hs (hdmi_hs), + .o_vs (hdmi_vs), + .o_de (hdmi_de), + .o_vbl (hdmi_vbl), + .o_brd (hdmi_brd), + .o_lltune (lltune), + .htotal (WIDTH + HFP + HBP + HS[11:0]), + .hsstart (WIDTH + HFP), + .hsend (WIDTH + HFP + HS[11:0]), + .hdisp (WIDTH), + .hmin (hmin), + .hmax (hmax), + .vtotal (HEIGHT + VFP + VBP + VS[11:0]), + .vsstart (HEIGHT + VFP), + .vsend (HEIGHT + VFP + VS[11:0]), + .vdisp (HEIGHT), + .vmin (vmin), + .vmax (vmax), + .vrr (vrr_mode), + .vrrmax (HEIGHT + VBP + VS[11:0] + 12'd1), + .swblack (hdmi_blackout), - .mode ({~lowlat,LFB_EN ? LFB_FLT : |scaler_flt,2'b00}), - .poly_clk (clk_sys), - .poly_a (coef_addr), - .poly_dw (coef_data), - .poly_wr (coef_wr), + .mode ({~lowlat,LFB_EN ? LFB_FLT : |scaler_flt,2'b00}), + .poly_clk (clk_sys), + .poly_a (coef_addr), + .poly_dw (coef_data), + .poly_wr (coef_wr), - .pal1_clk (clk_pal), - .pal1_dw (pal_d), - .pal1_a (pal_a), - .pal1_wr (pal_wr), + .pal1_clk (clk_pal), + .pal1_dw (pal_d), + .pal1_a (pal_a), + .pal1_wr (pal_wr), -`ifdef USE_FB - .pal2_clk (fb_pal_clk), - .pal2_dw (fb_pal_d), - .pal2_dr (fb_pal_q), - .pal2_a (fb_pal_a), - .pal2_wr (fb_pal_wr), - .pal_n (fb_en), -`endif + `ifdef MISTER_FB + `ifdef MISTER_FB_PALETTE + .pal2_clk (fb_pal_clk), + .pal2_dw (fb_pal_d), + .pal2_dr (fb_pal_q), + .pal2_a (fb_pal_a), + .pal2_wr (fb_pal_wr), + .pal_n (fb_en), + `endif + `endif - .o_fb_ena (FB_EN), - .o_fb_hsize (FB_WIDTH), - .o_fb_vsize (FB_HEIGHT), - .o_fb_format (FB_FMT), - .o_fb_base (FB_BASE), - .o_fb_stride (FB_STRIDE), + .o_fb_ena (FB_EN), + .o_fb_hsize (FB_WIDTH), + .o_fb_vsize (FB_HEIGHT), + .o_fb_format (FB_FMT), + .o_fb_base (FB_BASE), + .o_fb_stride (FB_STRIDE), - .avl_clk (clk_100m), - .avl_waitrequest (vbuf_waitrequest), - .avl_readdata (vbuf_readdata), - .avl_readdatavalid(vbuf_readdatavalid), - .avl_burstcount (vbuf_burstcount), - .avl_writedata (vbuf_writedata), - .avl_address (vbuf_address), - .avl_write (vbuf_write), - .avl_read (vbuf_read), - .avl_byteenable (vbuf_byteenable) -); + .avl_clk (clk_100m), + .avl_waitrequest (vbuf_waitrequest), + .avl_readdata (vbuf_readdata), + .avl_readdatavalid(vbuf_readdatavalid), + .avl_burstcount (vbuf_burstcount), + .avl_writedata (vbuf_writedata), + .avl_address (vbuf_address), + .avl_write (vbuf_write), + .avl_read (vbuf_read), + .avl_byteenable (vbuf_byteenable) + ); `endif reg LFB_EN = 0; @@ -734,6 +807,7 @@ reg [11:0] LFB_HMAX = 0; reg [11:0] LFB_VMIN = 0; reg [11:0] LFB_VMAX = 0; reg [31:0] LFB_BASE = 0; +reg [13:0] LFB_STRIDE = 0; reg FB_EN = 0; reg [5:0] FB_FMT = 0; @@ -749,7 +823,7 @@ always @(posedge clk_sys) begin FB_WIDTH <= LFB_WIDTH; FB_HEIGHT <= LFB_HEIGHT; FB_BASE <= LFB_BASE; - FB_STRIDE <= 0; + FB_STRIDE <= LFB_STRIDE; end else begin FB_FMT <= fb_fmt; @@ -760,77 +834,152 @@ always @(posedge clk_sys) begin end end -`ifdef USE_FB -reg fb_vbl; -always @(posedge clk_vid) fb_vbl <= hdmi_vbl; +`ifdef MISTER_FB + reg fb_vbl; + always @(posedge clk_vid) fb_vbl <= hdmi_vbl; `endif +reg ar_md_start; +wire ar_md_busy; +reg [11:0] ar_md_mul1, ar_md_mul2, ar_md_div; +wire [11:0] ar_md_res; + +sys_umuldiv #(12,12,12) ar_muldiv +( + .clk(clk_vid), + .start(ar_md_start), + .busy(ar_md_busy), + + .mul1(ar_md_mul1), + .mul2(ar_md_mul2), + .div(ar_md_div), + .result(ar_md_res) +); + reg [11:0] hmin; reg [11:0] hmax; reg [11:0] vmin; reg [11:0] vmax; +reg [11:0] hdmi_height; +reg [11:0] hdmi_width; + +reg [11:0] arx; +reg [11:0] ary; +reg arxy; always @(posedge clk_vid) begin - reg [31:0] wcalc; - reg [31:0] hcalc; + reg [11:0] hmini,hmaxi,vmini,vmaxi; + reg [11:0] wcalc,videow; + reg [11:0] hcalc,videoh; reg [2:0] state; - reg [11:0] videow; - reg [11:0] videoh; - reg [11:0] height; - reg [11:0] width; - height <= (VSET && (VSET < HEIGHT)) ? VSET : HEIGHT; - width <= (HSET && (HSET < WIDTH)) ? HSET : WIDTH; + hdmi_height <= (VSET && (VSET < HEIGHT)) ? VSET : HEIGHT; + hdmi_width <= (HSET && (HSET < WIDTH)) ? HSET << HDMI_PR : WIDTH << HDMI_PR; + if(!ARY) begin + if(ARX == 1) begin + arx <= arc1x[11:0]; + ary <= arc1y[11:0]; + arxy <= arc1x[12] | arc1y[12]; + end + else if(ARX == 2) begin + arx <= arc2x[11:0]; + ary <= arc2y[11:0]; + arxy <= arc2x[12] | arc2y[12]; + end + else begin + arx <= 0; + ary <= 0; + arxy <= 0; + end + end + else begin + arx <= ARX[11:0]; + ary <= ARY[11:0]; + arxy <= ARX[12] | ARY[12]; + end + + ar_md_start <= 0; state <= state + 1'd1; case(state) 0: if(LFB_EN) begin - hmin <= LFB_HMIN; - vmin <= LFB_VMIN; - hmax <= LFB_HMAX; - vmax <= LFB_VMAX; - state<= 0; + hmini <= LFB_HMIN; + vmini <= LFB_VMIN; + hmaxi <= LFB_HMAX; + vmaxi <= LFB_VMAX; + state <= 0; end - else if(ARX && ARY && !FREESCALE) begin - wcalc <= (height*ARX)/ARY; - hcalc <= (width*ARY)/ARX; + else if(FREESCALE || !arx || !ary) begin + wcalc <= hdmi_width; + hcalc <= hdmi_height; + state <= 6; end - else begin - wcalc <= width; - hcalc <= height; + else if(arxy) begin + wcalc <= arx; + hcalc <= ary; + state <= 6; end + + 1: begin + ar_md_mul1 <= hdmi_height; + ar_md_mul2 <= arx; + ar_md_div <= ary; + ar_md_start<= 1; + end + 2: begin + wcalc <= ar_md_res; + if(ar_md_start | ar_md_busy) state <= 2; + end + + 3: begin + ar_md_mul1 <= hdmi_width; + ar_md_mul2 <= ary; + ar_md_div <= arx; + ar_md_start<= 1; + end + 4: begin + hcalc <= ar_md_res; + if(ar_md_start | ar_md_busy) state <= 4; + end + 6: begin - videow <= (wcalc > width) ? width : wcalc[11:0]; - videoh <= (hcalc > height) ? height : hcalc[11:0]; + videow <= (wcalc > hdmi_width) ? (hdmi_width >> HDMI_PR) : (wcalc[11:0] >> HDMI_PR); + videoh <= (hcalc > hdmi_height) ? hdmi_height : hcalc[11:0]; end + 7: begin - hmin <= ((WIDTH - videow)>>1); - hmax <= ((WIDTH - videow)>>1) + videow - 1'd1; - vmin <= ((HEIGHT - videoh)>>1); - vmax <= ((HEIGHT - videoh)>>1) + videoh - 1'd1; + hmini <= ((WIDTH - videow)>>1); + hmaxi <= ((WIDTH - videow)>>1) + videow - 1'd1; + vmini <= ((HEIGHT - videoh)>>1); + vmaxi <= ((HEIGHT - videoh)>>1) + videoh - 1'd1; end endcase + + hmin <= hmini; + hmax <= hmaxi; + vmin <= vmini; + vmax <= vmaxi; end -`ifndef DEBUG_NOHDMI -wire [15:0] lltune; -pll_hdmi_adj pll_hdmi_adj -( - .clk(FPGA_CLK1_50), - .reset_na(~reset_req), +`ifndef MISTER_DEBUG_NOHDMI + wire [15:0] lltune; + pll_hdmi_adj pll_hdmi_adj + ( + .clk(FPGA_CLK1_50), + .reset_na(~reset_req), - .llena(lowlat), - .lltune({16{hdmi_config_done | cfg_dis}} & lltune), - .locked(led_locked), - .i_waitrequest(adj_waitrequest), - .i_write(adj_write), - .i_address(adj_address), - .i_writedata(adj_data), - .o_waitrequest(cfg_waitrequest), - .o_write(cfg_write), - .o_address(cfg_address), - .o_writedata(cfg_data) -); + .llena(lowlat), + .lltune({16{cfg_done}} & lltune), + .locked(led_locked), + .i_waitrequest(adj_waitrequest), + .i_write(adj_write), + .i_address(adj_address), + .i_writedata(adj_data), + .o_waitrequest(cfg_waitrequest), + .o_write(cfg_write), + .o_address(cfg_address), + .o_writedata(cfg_data) + ); `else assign led_locked = 0; `endif @@ -855,27 +1004,28 @@ end ///////////////////////// HDMI output ///////////////////////////////// -`ifndef DEBUG_NOHDMI -wire hdmi_clk_out; -pll_hdmi pll_hdmi -( - .refclk(FPGA_CLK1_50), - .rst(reset_req), - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll), - .outclk_0(hdmi_clk_out) -); +`ifndef MISTER_DEBUG_NOHDMI + wire hdmi_clk_out; + pll_hdmi pll_hdmi + ( + .refclk(FPGA_CLK1_50), + .rst(reset_req), + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll), + .outclk_0(hdmi_clk_out) + ); `endif //1920x1080@60 PCLK=148.5MHz CEA -reg [11:0] WIDTH = 1920; -reg [11:0] HFP = 88; -reg [11:0] HS = 48; -reg [11:0] HBP = 148; -reg [11:0] HEIGHT = 1080; -reg [11:0] VFP = 4; -reg [11:0] VS = 5; -reg [11:0] VBP = 36; +reg [11:0] WIDTH = 1920; +reg [11:0] HFP = 88; +reg [12:0] HS = 48; +reg [11:0] HBP = 148; +reg [11:0] HEIGHT = 1080; +reg [11:0] VFP = 4; +reg [12:0] VS = 5; +reg [11:0] VBP = 36; +reg HDMI_PR = 0; wire [63:0] reconfig_to_pll; wire [63:0] reconfig_from_pll; @@ -887,175 +1037,178 @@ reg adj_write; reg [5:0] adj_address; reg [31:0] adj_data; -`ifndef DEBUG_NOHDMI -pll_cfg pll_cfg -( - .mgmt_clk(FPGA_CLK1_50), - .mgmt_reset(reset_req), - .mgmt_waitrequest(cfg_waitrequest), - .mgmt_read(0), - .mgmt_readdata(), - .mgmt_write(cfg_write), - .mgmt_address(cfg_address), - .mgmt_writedata(cfg_data), - .reconfig_to_pll(reconfig_to_pll), - .reconfig_from_pll(reconfig_from_pll) -); +`ifndef MISTER_DEBUG_NOHDMI + pll_cfg_hdmi pll_cfg_hdmi + ( + .mgmt_clk(FPGA_CLK1_50), + .mgmt_reset(reset_req), + .mgmt_waitrequest(cfg_waitrequest), + .mgmt_write(cfg_write), + .mgmt_address(cfg_address), + .mgmt_writedata(cfg_data), + .reconfig_to_pll(reconfig_to_pll), + .reconfig_from_pll(reconfig_from_pll) + ); -reg cfg_got = 0; -always @(posedge clk_sys) begin - reg vsd, vsd2; - if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set; - else begin - vsd <= HDMI_TX_VS; - vsd2 <= vsd; - if(~vsd2 & vsd) cfg_got <= cfg_set; - end -end - -reg cfg_ready = 0; -always @(posedge FPGA_CLK1_50) begin - reg gotd = 0, gotd2 = 0; - reg custd = 0, custd2 = 0; - reg old_wait = 0; - - gotd <= cfg_got; - gotd2 <= gotd; - - adj_write <= 0; - - custd <= cfg_custom_t; - custd2 <= custd; - if(custd2 != custd & ~gotd) begin - adj_address <= cfg_custom_p1; - adj_data <= cfg_custom_p2; - adj_write <= 1; + reg cfg_got = 0; + always @(posedge clk_sys) begin + reg vsd, vsd2; + if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set; + else begin + vsd <= HDMI_TX_VS; + vsd2 <= vsd; + if(~vsd2 & vsd) cfg_got <= cfg_set; + end end - if(~gotd2 & gotd) begin - adj_address <= 2; - adj_data <= 0; - adj_write <= 1; + reg cfg_ready = 0; + always @(posedge FPGA_CLK1_50) begin + reg gotd = 0, gotd2 = 0; + reg custd = 0, custd2 = 0; + reg old_wait = 0; + + gotd <= cfg_got; + gotd2 <= gotd; + + adj_write <= 0; + + custd <= cfg_custom_t; + custd2 <= custd; + if(custd2 != custd & ~gotd) begin + adj_address <= cfg_custom_p1; + adj_data <= cfg_custom_p2; + adj_write <= 1; + end + + if(~gotd2 & gotd) begin + adj_address <= 2; + adj_data <= 0; + adj_write <= 1; + end + + old_wait <= adj_waitrequest; + if(old_wait & ~adj_waitrequest & gotd) cfg_ready <= 1; end - - old_wait <= adj_waitrequest; - if(old_wait & ~adj_waitrequest & gotd) cfg_ready <= 1; -end - `else - -wire cfg_ready = 1; - + wire cfg_ready = 1; `endif -wire hdmi_config_done; -hdmi_config hdmi_config +assign HDMI_I2C_SCL = hdmi_scl_en ? 1'b0 : 1'bZ; +assign HDMI_I2C_SDA = hdmi_sda_en ? 1'b0 : 1'bZ; + +wire hdmi_scl_en, hdmi_sda_en; +cyclonev_hps_interface_peripheral_i2c hdmi_i2c ( - .iCLK(FPGA_CLK1_50), - .iRST_N(cfg_ready & ~HDMI_TX_INT & ~cfg_dis), - .done(hdmi_config_done), - - .I2C_SCL(HDMI_I2C_SCL), - .I2C_SDA(HDMI_I2C_SDA), - - .dvi_mode(dvi_mode), - .audio_96k(audio_96k), - .limited(hdmi_limited), - .ypbpr(ypbpr_en & direct_video) + .out_clk(hdmi_scl_en), + .scl(HDMI_I2C_SCL), + .out_data(hdmi_sda_en), + .sda(HDMI_I2C_SDA) ); -`ifndef DEBUG_NOHDMI -wire [23:0] hdmi_data_sl; -wire hdmi_de_sl, hdmi_vs_sl, hdmi_hs_sl; +`ifndef MISTER_DEBUG_NOHDMI + `ifdef MISTER_FB + reg dis_output; + always @(posedge clk_hdmi) begin + reg dis; + dis <= fb_force_blank & ~LFB_EN; + dis_output <= dis; + end + `else + wire dis_output = 0; + `endif -`ifdef USE_FB -reg dis_output; -always @(posedge clk_hdmi) begin - reg dis; - dis <= fb_force_blank; - dis_output <= dis; -end -`else -wire dis_output = 0; + wire [23:0] hdmi_data_mask; + wire hdmi_de_mask, hdmi_vs_mask, hdmi_hs_mask; + + reg [15:0] shadowmask_data; + reg shadowmask_wr = 0; + + shadowmask HDMI_shadowmask + ( + .clk(clk_hdmi), + .clk_sys(clk_sys), + + .cmd_wr(shadowmask_wr), + .cmd_in(shadowmask_data), + + .din(dis_output ? 24'd0 : hdmi_data), + .hs_in(hdmi_hs), + .vs_in(hdmi_vs), + .de_in(hdmi_de), + .brd_in(hdmi_brd), + .enable(~LFB_EN), + + .dout(hdmi_data_mask), + .hs_out(hdmi_hs_mask), + .vs_out(hdmi_vs_mask), + .de_out(hdmi_de_mask) + ); + + wire [23:0] hdmi_data_osd; + wire hdmi_de_osd, hdmi_vs_osd, hdmi_hs_osd; + + osd hdmi_osd + ( + .clk_sys(clk_sys), + + .io_osd(io_osd_hdmi), + .io_strobe(io_strobe), + .io_din(io_din), + + .clk_video(clk_hdmi), + .din(hdmi_data_mask), + .hs_in(hdmi_hs_mask), + .vs_in(hdmi_vs_mask), + .de_in(hdmi_de_mask), + + .dout(hdmi_data_osd), + .hs_out(hdmi_hs_osd), + .vs_out(hdmi_vs_osd), + .de_out(hdmi_de_osd) + ); + + wire hdmi_cs_osd; + csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd); `endif -scanlines #(1) HDMI_scanlines -( - .clk(clk_hdmi), - - .scanlines(scanlines), - .din(dis_output ? 24'd0 : hdmi_data), - .hs_in(hdmi_hs), - .vs_in(hdmi_vs), - .de_in(hdmi_de), - - .dout(hdmi_data_sl), - .hs_out(hdmi_hs_sl), - .vs_out(hdmi_vs_sl), - .de_out(hdmi_de_sl) -); - -wire [23:0] hdmi_data_osd; -wire hdmi_de_osd, hdmi_vs_osd, hdmi_hs_osd; - -osd hdmi_osd -( - .clk_sys(clk_sys), - - .io_osd(io_osd_hdmi), - .io_strobe(io_strobe), - .io_din(io_din), - - .clk_video(clk_hdmi), - .din(hdmi_data_sl), - .hs_in(hdmi_hs_sl), - .vs_in(hdmi_vs_sl), - .de_in(hdmi_de_sl), - - .dout(hdmi_data_osd), - .hs_out(hdmi_hs_osd), - .vs_out(hdmi_vs_osd), - .de_out(hdmi_de_osd) -`ifndef ARCADE_SYS - , - .osd_status(osd_status) -`endif -); -`endif - -wire hdmi_cs_osd; -csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd); - reg [23:0] dv_data; reg dv_hs, dv_vs, dv_de; +wire [23:0] dv_data_osd; +wire dv_hs_osd, dv_vs_osd, dv_cs_osd; + always @(posedge clk_vid) begin reg [23:0] dv_d1, dv_d2; reg dv_de1, dv_de2, dv_hs1, dv_hs2, dv_vs1, dv_vs2; - reg [12:0] vsz, vcnt; + reg [12:0] vsz, vcnt, vcnt_l, vcnt_ll; reg old_hs, old_vs; reg vde; reg [3:0] hss; if(ce_pix) begin - hss <= (hss << 1) | vga_hs_osd; + hss <= (hss << 1) | dv_hs_osd; - old_hs <= vga_hs_osd; - if(~old_hs && vga_hs_osd) begin - old_vs <= vga_vs_osd; + old_hs <= dv_hs_osd; + if(~old_hs && dv_hs_osd) begin + old_vs <= dv_vs_osd; if(~&vcnt) vcnt <= vcnt + 1'd1; - if(~old_vs & vga_vs_osd & ~f1) vsz <= vcnt; - if(old_vs & ~vga_vs_osd) vcnt <= 0; + if(~old_vs & dv_vs_osd) begin + if (vcnt != vcnt_ll || vcnt < vcnt_l) vsz <= vcnt; + vcnt_l <= vcnt; + vcnt_ll <= vcnt_l; + end + if(old_vs & ~dv_vs_osd) vcnt <= 0; if(vcnt == 1) vde <= 1; if(vcnt == vsz - 3) vde <= 0; end - dv_de1 <= !{hss,vga_hs_osd} && vde; - dv_hs1 <= csync_en ? vga_cs_osd : vga_hs_osd; - dv_vs1 <= vga_vs_osd; + dv_de1 <= !{hss,dv_hs_osd} && vde; end - dv_d1 <= vga_data_osd; + dv_d1 <= dv_data_osd; + dv_hs1 <= csync_en ? dv_cs_osd : dv_hs_osd; + dv_vs1 <= dv_vs_osd; + dv_d2 <= dv_d1; dv_de2 <= dv_de1; dv_hs2 <= dv_hs1; @@ -1067,16 +1220,22 @@ always @(posedge clk_vid) begin dv_vs <= dv_vs2; end -wire hdmi_tx_clk; -`ifndef DEBUG_NOHDMI -cyclonev_clkselect hdmi_clk_sw -( - .clkselect({1'b1, ~vga_fb & direct_video}), - .inclk({clk_vid, hdmi_clk_out, 2'b00}), - .outclk(hdmi_tx_clk) -); +`ifndef MISTER_DISABLE_YC + assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = ~yc_en ? {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd } : {yc_o, yc_hs, yc_vs, yc_cs }; `else -assign hdmi_tx_clk = clk_vid; + assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd }; +`endif + +wire hdmi_tx_clk; +`ifndef MISTER_DEBUG_NOHDMI + cyclonev_clkselect hdmi_clk_sw + ( + .clkselect({1'b1, ~vga_fb & direct_video}), + .inclk({clk_vid, hdmi_clk_out, 2'b00}), + .outclk(hdmi_tx_clk) + ); +`else + assign hdmi_tx_clk = clk_vid; `endif altddio_out @@ -1110,13 +1269,28 @@ reg hdmi_out_de; reg [23:0] hdmi_out_d; always @(posedge hdmi_tx_clk) begin + reg [23:0] hdmi_dv_data; + reg hdmi_dv_hs, hdmi_dv_vs, hdmi_dv_de; + reg hs,vs,de; reg [23:0] d; - hs <= (~vga_fb & direct_video) ? dv_hs : (direct_video & csync_en) ? hdmi_cs_osd : hdmi_hs_osd; - vs <= (~vga_fb & direct_video) ? dv_vs : hdmi_vs_osd; - de <= (~vga_fb & direct_video) ? dv_de : hdmi_de_osd; - d <= (~vga_fb & direct_video) ? dv_data : hdmi_data_osd; + hdmi_dv_data <= dv_data; + hdmi_dv_hs <= dv_hs; + hdmi_dv_vs <= dv_vs; + hdmi_dv_de <= dv_de; + +`ifndef MISTER_DEBUG_NOHDMI + hs <= (~vga_fb & direct_video) ? hdmi_dv_hs : (direct_video & csync_en) ? hdmi_cs_osd : hdmi_hs_osd; + vs <= (~vga_fb & direct_video) ? hdmi_dv_vs : hdmi_vs_osd; + de <= (~vga_fb & direct_video) ? hdmi_dv_de : hdmi_de_osd; + d <= (~vga_fb & direct_video) ? hdmi_dv_data : hdmi_data_osd; +`else + hs <= hdmi_dv_hs; + vs <= hdmi_dv_vs; + de <= hdmi_dv_de; + d <= hdmi_dv_data; +`endif hdmi_out_hs <= hs; hdmi_out_vs <= vs; @@ -1131,8 +1305,48 @@ assign HDMI_TX_D = hdmi_out_d; ///////////////////////// VGA output ////////////////////////////////// +`ifndef MISTER_DUAL_SDRAM + wire vga_tx_clk; + `ifndef MISTER_DEBUG_NOHDMI + cyclonev_clkselect vga_clk_sw + ( + .clkselect({1'b1, ~vga_fb & ~vga_scaler}), + .inclk({clk_vid, hdmi_clk_out, 2'b00}), + .outclk(vga_tx_clk) + ); + `else + assign vga_tx_clk = clk_vid; + `endif + + wire VGA_TX_CLK; + altddio_out + #( + .extend_oe_disable("OFF"), + .intended_device_family("Cyclone V"), + .invert_output("OFF"), + .lpm_hint("UNUSED"), + .lpm_type("altddio_out"), + .oe_reg("UNREGISTERED"), + .power_up_high("OFF"), + .width(1) + ) + vgaclk_ddr + ( + .datain_h(1'b0), + .datain_l(1'b1), + .outclock(vga_tx_clk), + .dataout(VGA_TX_CLK), + .aclr(~mcp_en & ~av_dis), + .aset(1'b0), + .oe(~av_dis & (mcp_en | ~led_u)), + .outclocken(1'b1), + .sclr(1'b0), + .sset(1'b0) + ); +`endif + wire [23:0] vga_data_sl; -wire vga_de_sl, vga_vs_sl, vga_hs_sl; +wire vga_de_sl, vga_ce_sl, vga_vs_sl, vga_hs_sl; scanlines #(0) VGA_scanlines ( .clk(clk_vid), @@ -1142,15 +1356,17 @@ scanlines #(0) VGA_scanlines .hs_in(hs_fix), .vs_in(vs_fix), .de_in(de_emu), + .ce_in(ce_pix), .dout(vga_data_sl), .hs_out(vga_hs_sl), .vs_out(vga_vs_sl), - .de_out(vga_de_sl) + .de_out(vga_de_sl), + .ce_out(vga_ce_sl) ); wire [23:0] vga_data_osd; -wire vga_vs_osd, vga_hs_osd; +wire vga_vs_osd, vga_hs_osd, vga_de_osd; osd vga_osd ( .clk_sys(clk_sys), @@ -1158,6 +1374,7 @@ osd vga_osd .io_osd(io_osd_vga), .io_strobe(io_strobe), .io_din(io_din), + .osd_status(osd_status), .clk_video(clk_vid), .din(vga_data_sl), @@ -1167,31 +1384,104 @@ osd vga_osd .dout(vga_data_osd), .hs_out(vga_hs_osd), - .vs_out(vga_vs_osd) + .vs_out(vga_vs_osd), + .de_out(vga_de_osd) ); wire vga_cs_osd; csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd); -`ifndef DUAL_SDRAM - wire [23:0] vga_o; +`ifndef MISTER_DISABLE_YC + reg pal_en; + reg yc_en; + reg cvbs; + reg [16:0] ColorBurst_Range; + reg [39:0] PhaseInc; + wire [23:0] yc_o; + wire yc_hs, yc_vs, yc_cs, yc_de; + + yc_out yc_out + ( + .clk(clk_vid), + .PAL_EN(pal_en), + .CVBS(cvbs), + .PHASE_INC(PhaseInc), + .COLORBURST_RANGE(ColorBurst_Range), + .hsync(vga_hs_osd), + .vsync(vga_vs_osd), + .csync(vga_cs_osd), + .de(vga_de_osd), + .dout(yc_o), + .din(vga_data_osd), + .hsync_o(yc_hs), + .vsync_o(yc_vs), + .csync_o(yc_cs), + .de_o(yc_de) + ); +`endif + +`ifndef MISTER_DUAL_SDRAM + wire VGA_DISABLE; + wire [23:0] vgas_o; + wire vgas_hs, vgas_vs, vgas_cs, vgas_de; + `ifndef MISTER_DEBUG_NOHDMI + vga_out vga_scaler_out + ( + .clk(clk_hdmi), + .ypbpr_en(ypbpr_en), + .hsync(hdmi_hs_osd), + .vsync(hdmi_vs_osd), + .csync(hdmi_cs_osd), + .de(hdmi_de_osd), + .dout(vgas_o), + .din({24{hdmi_de_osd}} & hdmi_data_osd), + .hsync_o(vgas_hs), + .vsync_o(vgas_vs), + .csync_o(vgas_cs), + .de_o(vgas_de) + ); + `else + assign {vgas_o, vgas_hs, vgas_vs, vgas_cs, vgas_de} = 0; + `endif + + wire [23:0] vga_o, vga_o_t; + wire vga_hs, vga_vs, vga_cs, vga_de, vga_hs_t, vga_vs_t, vga_cs_t, vga_de_t; vga_out vga_out ( - .ypbpr_full(0), + .clk(clk_vid), .ypbpr_en(ypbpr_en), - .dout(vga_o), - .din((vga_fb | vga_scaler) ? {24{hdmi_de_osd}} & hdmi_data_osd : vga_data_osd) + .hsync(vga_hs_osd), + .vsync(vga_vs_osd), + .csync(vga_cs_osd), + .de(vga_de_osd), + .dout(vga_o_t), + .din(vga_data_osd), + .hsync_o(vga_hs_t), + .vsync_o(vga_vs_t), + .csync_o(vga_cs_t), + .de_o(vga_de_t) ); - wire vs1 = (vga_fb | vga_scaler) ? hdmi_vs_osd : vga_vs_osd; - wire hs1 = (vga_fb | vga_scaler) ? hdmi_hs_osd : vga_hs_osd; - wire cs1 = (vga_fb | vga_scaler) ? hdmi_cs_osd : vga_cs_osd; + `ifndef MISTER_DISABLE_YC + assign {vga_o, vga_hs, vga_vs, vga_cs, vga_de } = ~yc_en ? {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t, vga_de_t } : {yc_o, yc_hs, yc_vs, yc_cs, yc_de }; + `else + assign {vga_o, vga_hs, vga_vs, vga_cs, vga_de } = {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t, vga_de_t } ; + `endif - assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ : csync_en ? 1'b1 : ~vs1; - assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ : csync_en ? ~cs1 : ~hs1; - assign VGA_R = (VGA_EN | SW[3]) ? 6'bZZZZZZ : vga_o[23:18]; - assign VGA_G = (VGA_EN | SW[3]) ? 6'bZZZZZZ : vga_o[15:10]; - assign VGA_B = (VGA_EN | SW[3]) ? 6'bZZZZZZ : vga_o[7:2]; + wire vgas_en = vga_fb | vga_scaler; + + wire cs1 = vgas_en ? vgas_cs : vga_cs; + wire de1 = vgas_en ? vgas_de : vga_de; + + assign VGA_VS = av_dis ? 1'bZ : ((vgas_en ? (~vgas_vs ^ VS[12]) : VGA_DISABLE ? 1'd1 : ~vga_vs) | csync_en); + assign VGA_HS = av_dis ? 1'bZ : (vgas_en ? ((csync_en ? ~vgas_cs : ~vgas_hs) ^ HS[12]) : VGA_DISABLE ? 1'd1 : (csync_en ? ~vga_cs : ~vga_hs)); + assign VGA_R = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[23:18] : VGA_DISABLE ? 6'd0 : vga_o[23:18]; + assign VGA_G = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[15:10] : VGA_DISABLE ? 6'd0 : vga_o[15:10]; + assign VGA_B = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[7:2] : VGA_DISABLE ? 6'd0 : vga_o[7:2] ; + + wire [1:0] vga_r = vgas_en ? vgas_o[17:16] : VGA_DISABLE ? 2'd0 : vga_o[17:16]; + wire [1:0] vga_g = vgas_en ? vgas_o[9:8] : VGA_DISABLE ? 2'd0 : vga_o[9:8]; + wire [1:0] vga_b = vgas_en ? vgas_o[1:0] : VGA_DISABLE ? 2'd0 : vga_o[1:0]; `endif reg video_sync = 0; @@ -1221,14 +1511,14 @@ end ///////////////////////// Audio output //////////////////////////////// -assign SDCD_SPDIF =(SW[3] & ~spdif) ? 1'b0 : 1'bZ; +assign SDCD_SPDIF = (mcp_en & ~spdif) ? 1'b0 : 1'bZ; -`ifndef DUAL_SDRAM +`ifndef MISTER_DUAL_SDRAM wire analog_l, analog_r; - assign AUDIO_SPDIF = SW[3] ? 1'bZ : SW[0] ? HDMI_LRCLK : spdif; - assign AUDIO_R = SW[3] ? 1'bZ : SW[0] ? HDMI_I2S : analog_r; - assign AUDIO_L = SW[3] ? 1'bZ : SW[0] ? HDMI_SCLK : analog_l; + assign AUDIO_SPDIF = av_dis ? 1'bZ : (SW[0] | mcp_en) ? HDMI_LRCLK : spdif; + assign AUDIO_R = av_dis ? 1'bZ : (SW[0] | mcp_en) ? HDMI_I2S : analog_r; + assign AUDIO_L = av_dis ? 1'bZ : (SW[0] | mcp_en) ? HDMI_SCLK : analog_l; `endif assign HDMI_MCLK = clk_audio; @@ -1264,13 +1554,15 @@ audio_out audio_out .core_l(audio_l), .core_r(audio_r), +`ifndef MISTER_DISABLE_ALSA .alsa_l(alsa_l), .alsa_r(alsa_r), +`endif .i2s_bclk(HDMI_SCLK), .i2s_lrclk(HDMI_LRCLK), .i2s_data(HDMI_I2S), -`ifndef DUAL_SDRAM +`ifndef MISTER_DUAL_SDRAM .dac_l(analog_l), .dac_r(analog_r), `endif @@ -1278,32 +1570,45 @@ audio_out audio_out ); -wire [28:0] alsa_address; -wire [63:0] alsa_readdata; -wire alsa_ready; -wire alsa_req; -wire alsa_late; +`ifndef MISTER_DISABLE_ALSA + wire aspi_sck,aspi_mosi,aspi_ss,aspi_miso; + cyclonev_hps_interface_peripheral_spi_master spi + ( + .sclk_out(aspi_sck), + .txd(aspi_mosi), // mosi + .rxd(aspi_miso), // miso -wire [15:0] alsa_l, alsa_r; + .ss_0_n(aspi_ss), + .ss_in_n(1) + ); -alsa alsa -( - .reset(reset), - .clk(clk_audio), + wire [28:0] alsa_address; + wire [63:0] alsa_readdata; + wire alsa_ready; + wire alsa_req; + wire alsa_late; - .ram_address(alsa_address), - .ram_data(alsa_readdata), - .ram_req(alsa_req), - .ram_ready(alsa_ready), + wire [15:0] alsa_l, alsa_r; - .spi_ss(aspi_ss), - .spi_sck(aspi_sck), - .spi_mosi(aspi_mosi), - .spi_miso(aspi_miso), + alsa alsa + ( + .reset(reset), + .clk(clk_audio), - .pcm_l(alsa_l), - .pcm_r(alsa_r) -); + .ram_address(alsa_address), + .ram_data(alsa_readdata), + .ram_req(alsa_req), + .ram_ready(alsa_ready), + + .spi_ss(aspi_ss), + .spi_sck(aspi_sck), + .spi_mosi(aspi_mosi), + .spi_miso(aspi_miso), + + .pcm_l(alsa_l), + .pcm_r(alsa_r) + ); +`endif //////////////// User I/O (USB 3.0 connector) ///////////////////////// @@ -1335,19 +1640,18 @@ wire [7:0] r_out, g_out, b_out, hr_out, hg_out, hb_out; wire vs_fix, hs_fix, de_emu, vs_emu, hs_emu, f1; wire hvs_fix, hhs_fix, hde_emu; wire clk_vid, ce_pix, clk_ihdmi, ce_hpix; +wire vga_force_scaler; -`ifdef USE_DDRAM - wire ram_clk; - wire [28:0] ram_address; - wire [7:0] ram_burstcount; - wire ram_waitrequest; - wire [63:0] ram_readdata; - wire ram_readdatavalid; - wire ram_read; - wire [63:0] ram_writedata; - wire [7:0] ram_byteenable; - wire ram_write; -`endif +wire ram_clk; +wire [28:0] ram_address; +wire [7:0] ram_burstcount; +wire ram_waitrequest; +wire [63:0] ram_readdata; +wire ram_readdatavalid; +wire ram_read; +wire [63:0] ram_writedata; +wire [7:0] ram_byteenable; +wire ram_write; wire led_user; wire [1:0] led_power; @@ -1359,32 +1663,23 @@ sync_fix sync_h(clk_vid, hs_emu, hs_fix); wire [6:0] user_out, user_in; -`ifndef USE_SDRAM -assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = {39'bZ}; -`endif - assign clk_ihdmi= clk_vid; -assign ce_hpix = ce_pix; -assign hr_out = r_out; -assign hg_out = g_out; -assign hb_out = b_out; -assign hhs_fix = hs_fix; -assign hvs_fix = vs_fix; -assign hde_emu = de_emu; +assign ce_hpix = vga_ce_sl; +assign hr_out = vga_data_sl[23:16]; +assign hg_out = vga_data_sl[15:8]; +assign hb_out = vga_data_sl[7:0]; +assign hhs_fix = vga_hs_sl; +assign hvs_fix = vga_vs_sl; +assign hde_emu = vga_de_sl; -`ifdef ARCADE_SYS - assign audio_mix = 0; - assign {ADC_SCK, ADC_SDI, ADC_CONVST} = 0; - assign btn = 0; -`else - wire uart_dtr; - wire uart_dsr; - wire uart_cts; - wire uart_rts; - wire uart_rxd; - wire uart_txd; - wire osd_status; -`endif +wire uart_dtr; +wire uart_dsr; +wire uart_cts; +wire uart_rts; +wire uart_rxd; +wire uart_txd; + +wire osd_status; wire fb_en; wire [4:0] fb_fmt; @@ -1393,13 +1688,16 @@ wire [11:0] fb_height; wire [31:0] fb_base; wire [13:0] fb_stride; -`ifdef USE_FB - wire fb_pal_clk; - wire [7:0] fb_pal_a; - wire [23:0] fb_pal_d; - wire [23:0] fb_pal_q; - wire fb_pal_wr; - wire fb_force_blank; + +`ifdef MISTER_FB + `ifdef MISTER_FB_PALETTE + wire fb_pal_clk; + wire [7:0] fb_pal_a; + wire [23:0] fb_pal_d; + wire [23:0] fb_pal_q; + wire fb_pal_wr; + `endif + wire fb_force_blank; `else assign fb_en = 0; assign fb_fmt = 0; @@ -1409,11 +1707,18 @@ wire [13:0] fb_stride; assign fb_stride = 0; `endif +reg [1:0] sl_r; +wire [1:0] sl = sl_r; +always @(posedge clk_sys) sl_r <= FB_EN ? 2'b00 : scanlines; + emu emu ( .CLK_50M(FPGA_CLK2_50), .RESET(reset), - .HPS_BUS({f1, HDMI_TX_VS, clk_100m, clk_ihdmi, ce_hpix, hde_emu, hhs_fix, hvs_fix, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}), + .HPS_BUS({fb_en, sl, f1, HDMI_TX_VS, + clk_100m, clk_ihdmi, + ce_hpix, hde_emu, hhs_fix, hvs_fix, + io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}), .VGA_R(r_out), .VGA_G(g_out), @@ -1422,6 +1727,16 @@ emu emu .VGA_VS(vs_emu), .VGA_DE(de_emu), .VGA_F1(f1), + .VGA_SCALER(vga_force_scaler), + +`ifndef MISTER_DUAL_SDRAM + .VGA_DISABLE(VGA_DISABLE), +`endif + + .HDMI_WIDTH(direct_video ? 12'd0 : hdmi_width), + .HDMI_HEIGHT(direct_video ? 12'd0 : hdmi_height), + .HDMI_FREEZE(freeze), + .HDMI_BLACKOUT(hdmi_blackout), .CLK_VIDEO(clk_vid), .CE_PIXEL(ce_pix), @@ -1429,7 +1744,7 @@ emu emu .VIDEO_ARX(ARX), .VIDEO_ARY(ARY), -`ifdef USE_FB +`ifdef MISTER_FB .FB_EN(fb_en), .FB_FORMAT(fb_fmt), .FB_WIDTH(fb_width), @@ -1440,11 +1755,14 @@ emu emu .FB_LL(lowlat), .FB_FORCE_BLANK(fb_force_blank), +`ifdef MISTER_FB_PALETTE .FB_PAL_CLK (fb_pal_clk), .FB_PAL_ADDR(fb_pal_a), .FB_PAL_DOUT(fb_pal_d), .FB_PAL_DIN (fb_pal_q), .FB_PAL_WR (fb_pal_wr), +`endif + `endif .LED_USER(led_user), @@ -1455,13 +1773,10 @@ emu emu .AUDIO_L(audio_l), .AUDIO_R(audio_r), .AUDIO_S(audio_s), - -`ifndef ARCADE_SYS .AUDIO_MIX(audio_mix), - .ADC_BUS({ADC_SCK,ADC_SDO,ADC_SDI,ADC_CONVST}), -`endif -`ifdef USE_DDRAM + .ADC_BUS({ADC_SCK,ADC_SDO,ADC_SDI,ADC_CONVST}), + .DDRAM_CLK(ram_clk), .DDRAM_ADDR(ram_address), .DDRAM_BURSTCNT(ram_burstcount), @@ -1472,9 +1787,7 @@ emu emu .DDRAM_DIN(ram_writedata), .DDRAM_BE(ram_byteenable), .DDRAM_WE(ram_write), -`endif -`ifdef USE_SDRAM .SDRAM_DQ(SDRAM_DQ), .SDRAM_A(SDRAM_A), .SDRAM_DQML(SDRAM_DQML), @@ -1486,9 +1799,8 @@ emu emu .SDRAM_nCAS(SDRAM_nCAS), .SDRAM_CLK(SDRAM_CLK), .SDRAM_CKE(SDRAM_CKE), -`endif -`ifdef DUAL_SDRAM +`ifdef MISTER_DUAL_SDRAM .SDRAM2_DQ(SDRAM2_DQ), .SDRAM2_A(SDRAM2_A), .SDRAM2_BA(SDRAM2_BA), @@ -1497,21 +1809,17 @@ emu emu .SDRAM2_nRAS(SDRAM2_nRAS), .SDRAM2_nCAS(SDRAM2_nCAS), .SDRAM2_CLK(SDRAM2_CLK), - .SDRAM2_EN(SW[3]), + .SDRAM2_EN(io_dig), `endif -`ifndef ARCADE_SYS .BUTTONS(btn), .OSD_STATUS(osd_status), + .SD_SCK(SD_CLK), .SD_MOSI(SD_MOSI), .SD_MISO(SD_MISO), .SD_CS(SD_CS), -`ifdef DUAL_SDRAM - .SD_CD(mcp_sdcd), -`else - .SD_CD(mcp_sdcd & (SW[0] ? VGA_HS : (SW[3] | SDCD_SPDIF))), -`endif + .SD_CD(SD_CD), .UART_CTS(uart_rts), .UART_RTS(uart_cts), @@ -1519,7 +1827,6 @@ emu emu .UART_TXD(uart_rxd), .UART_DTR(uart_dsr), .UART_DSR(uart_dtr), -`endif .USER_OUT(user_out), .USER_IN(user_in) @@ -1541,19 +1848,17 @@ assign sync_out = sync_in ^ pol; reg pol; always @(posedge clk) begin - integer pos = 0, neg = 0, cnt = 0; + reg [31:0] cnt; reg s1,s2; s1 <= sync_in; s2 <= s1; + cnt <= s2 ? (cnt - 1) : (cnt + 1); - if(~s2 & s1) neg <= cnt; - if(s2 & ~s1) pos <= cnt; - - cnt <= cnt + 1; - if(s2 != s1) cnt <= 0; - - pol <= pos > neg; + if(~s2 & s1) begin + cnt <= 0; + pol <= cnt[31]; + end end endmodule diff --git a/sys/sysmem.sv b/sys/sysmem.sv index c90395e..8c17e86 100644 --- a/sys/sysmem.sv +++ b/sys/sysmem.sv @@ -44,41 +44,182 @@ module sysmem_lite assign reset_out = ~init_reset_n | ~hps_h2f_reset_n | reset_core_req; +//////////////////////////////////////////////////////// +//// f2sdram_safe_terminator_ram1 //// +//////////////////////////////////////////////////////// +wire [28:0] f2h_ram1_address; +wire [7:0] f2h_ram1_burstcount; +wire f2h_ram1_waitrequest; +wire [63:0] f2h_ram1_readdata; +wire f2h_ram1_readdatavalid; +wire f2h_ram1_read; +wire [63:0] f2h_ram1_writedata; +wire [7:0] f2h_ram1_byteenable; +wire f2h_ram1_write; + +(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram1_reset_0 = 1'b1; +(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram1_reset_1 = 1'b1; +always @(posedge ram1_clk) begin + ram1_reset_0 <= reset_out; + ram1_reset_1 <= ram1_reset_0; +end + +f2sdram_safe_terminator #(64, 8) f2sdram_safe_terminator_ram1 +( + .clk (ram1_clk), + .rst_req_sync (ram1_reset_1), + + .waitrequest_slave (ram1_waitrequest), + .burstcount_slave (ram1_burstcount), + .address_slave (ram1_address), + .readdata_slave (ram1_readdata), + .readdatavalid_slave (ram1_readdatavalid), + .read_slave (ram1_read), + .writedata_slave (ram1_writedata), + .byteenable_slave (ram1_byteenable), + .write_slave (ram1_write), + + .waitrequest_master (f2h_ram1_waitrequest), + .burstcount_master (f2h_ram1_burstcount), + .address_master (f2h_ram1_address), + .readdata_master (f2h_ram1_readdata), + .readdatavalid_master (f2h_ram1_readdatavalid), + .read_master (f2h_ram1_read), + .writedata_master (f2h_ram1_writedata), + .byteenable_master (f2h_ram1_byteenable), + .write_master (f2h_ram1_write) +); + +//////////////////////////////////////////////////////// +//// f2sdram_safe_terminator_ram2 //// +//////////////////////////////////////////////////////// +wire [28:0] f2h_ram2_address; +wire [7:0] f2h_ram2_burstcount; +wire f2h_ram2_waitrequest; +wire [63:0] f2h_ram2_readdata; +wire f2h_ram2_readdatavalid; +wire f2h_ram2_read; +wire [63:0] f2h_ram2_writedata; +wire [7:0] f2h_ram2_byteenable; +wire f2h_ram2_write; + +(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram2_reset_0 = 1'b1; +(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg ram2_reset_1 = 1'b1; +always @(posedge ram2_clk) begin + ram2_reset_0 <= reset_out; + ram2_reset_1 <= ram2_reset_0; +end + +f2sdram_safe_terminator #(64, 8) f2sdram_safe_terminator_ram2 +( + .clk (ram2_clk), + .rst_req_sync (ram2_reset_1), + + .waitrequest_slave (ram2_waitrequest), + .burstcount_slave (ram2_burstcount), + .address_slave (ram2_address), + .readdata_slave (ram2_readdata), + .readdatavalid_slave (ram2_readdatavalid), + .read_slave (ram2_read), + .writedata_slave (ram2_writedata), + .byteenable_slave (ram2_byteenable), + .write_slave (ram2_write), + + .waitrequest_master (f2h_ram2_waitrequest), + .burstcount_master (f2h_ram2_burstcount), + .address_master (f2h_ram2_address), + .readdata_master (f2h_ram2_readdata), + .readdatavalid_master (f2h_ram2_readdatavalid), + .read_master (f2h_ram2_read), + .writedata_master (f2h_ram2_writedata), + .byteenable_master (f2h_ram2_byteenable), + .write_master (f2h_ram2_write) +); + +//////////////////////////////////////////////////////// +//// f2sdram_safe_terminator_vbuf //// +//////////////////////////////////////////////////////// +wire [27:0] f2h_vbuf_address; +wire [7:0] f2h_vbuf_burstcount; +wire f2h_vbuf_waitrequest; +wire [127:0] f2h_vbuf_readdata; +wire f2h_vbuf_readdatavalid; +wire f2h_vbuf_read; +wire [127:0] f2h_vbuf_writedata; +wire [15:0] f2h_vbuf_byteenable; +wire f2h_vbuf_write; + +(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg vbuf_reset_0 = 1'b1; +(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS"} *) reg vbuf_reset_1 = 1'b1; +always @(posedge vbuf_clk) begin + vbuf_reset_0 <= reset_out; + vbuf_reset_1 <= vbuf_reset_0; +end + +f2sdram_safe_terminator #(128, 8) f2sdram_safe_terminator_vbuf +( + .clk (vbuf_clk), + .rst_req_sync (vbuf_reset_1), + + .waitrequest_slave (vbuf_waitrequest), + .burstcount_slave (vbuf_burstcount), + .address_slave (vbuf_address), + .readdata_slave (vbuf_readdata), + .readdatavalid_slave (vbuf_readdatavalid), + .read_slave (vbuf_read), + .writedata_slave (vbuf_writedata), + .byteenable_slave (vbuf_byteenable), + .write_slave (vbuf_write), + + .waitrequest_master (f2h_vbuf_waitrequest), + .burstcount_master (f2h_vbuf_burstcount), + .address_master (f2h_vbuf_address), + .readdata_master (f2h_vbuf_readdata), + .readdatavalid_master (f2h_vbuf_readdatavalid), + .read_master (f2h_vbuf_read), + .writedata_master (f2h_vbuf_writedata), + .byteenable_master (f2h_vbuf_byteenable), + .write_master (f2h_vbuf_write) +); + +//////////////////////////////////////////////////////// +//// HPS <> FPGA interfaces //// +//////////////////////////////////////////////////////// sysmem_HPS_fpga_interfaces fpga_interfaces ( .f2h_cold_rst_req_n (~reset_hps_cold_req), .f2h_warm_rst_req_n (~reset_hps_warm_req), .h2f_user0_clk (clock), .h2f_rst_n (hps_h2f_reset_n), .f2h_sdram0_clk (vbuf_clk), - .f2h_sdram0_ADDRESS (vbuf_address), - .f2h_sdram0_BURSTCOUNT (vbuf_burstcount), - .f2h_sdram0_WAITREQUEST (vbuf_waitrequest), - .f2h_sdram0_READDATA (vbuf_readdata), - .f2h_sdram0_READDATAVALID (vbuf_readdatavalid), - .f2h_sdram0_READ (vbuf_read), - .f2h_sdram0_WRITEDATA (vbuf_writedata), - .f2h_sdram0_BYTEENABLE (vbuf_byteenable), - .f2h_sdram0_WRITE (vbuf_write), + .f2h_sdram0_ADDRESS (f2h_vbuf_address), + .f2h_sdram0_BURSTCOUNT (f2h_vbuf_burstcount), + .f2h_sdram0_WAITREQUEST (f2h_vbuf_waitrequest), + .f2h_sdram0_READDATA (f2h_vbuf_readdata), + .f2h_sdram0_READDATAVALID (f2h_vbuf_readdatavalid), + .f2h_sdram0_READ (f2h_vbuf_read), + .f2h_sdram0_WRITEDATA (f2h_vbuf_writedata), + .f2h_sdram0_BYTEENABLE (f2h_vbuf_byteenable), + .f2h_sdram0_WRITE (f2h_vbuf_write), .f2h_sdram1_clk (ram1_clk), - .f2h_sdram1_ADDRESS (ram1_address), - .f2h_sdram1_BURSTCOUNT (ram1_burstcount), - .f2h_sdram1_WAITREQUEST (ram1_waitrequest), - .f2h_sdram1_READDATA (ram1_readdata), - .f2h_sdram1_READDATAVALID (ram1_readdatavalid), - .f2h_sdram1_READ (ram1_read), - .f2h_sdram1_WRITEDATA (ram1_writedata), - .f2h_sdram1_BYTEENABLE (ram1_byteenable), - .f2h_sdram1_WRITE (ram1_write), + .f2h_sdram1_ADDRESS (f2h_ram1_address), + .f2h_sdram1_BURSTCOUNT (f2h_ram1_burstcount), + .f2h_sdram1_WAITREQUEST (f2h_ram1_waitrequest), + .f2h_sdram1_READDATA (f2h_ram1_readdata), + .f2h_sdram1_READDATAVALID (f2h_ram1_readdatavalid), + .f2h_sdram1_READ (f2h_ram1_read), + .f2h_sdram1_WRITEDATA (f2h_ram1_writedata), + .f2h_sdram1_BYTEENABLE (f2h_ram1_byteenable), + .f2h_sdram1_WRITE (f2h_ram1_write), .f2h_sdram2_clk (ram2_clk), - .f2h_sdram2_ADDRESS (ram2_address), - .f2h_sdram2_BURSTCOUNT (ram2_burstcount), - .f2h_sdram2_WAITREQUEST (ram2_waitrequest), - .f2h_sdram2_READDATA (ram2_readdata), - .f2h_sdram2_READDATAVALID (ram2_readdatavalid), - .f2h_sdram2_READ (ram2_read), - .f2h_sdram2_WRITEDATA (ram2_writedata), - .f2h_sdram2_BYTEENABLE (ram2_byteenable), - .f2h_sdram2_WRITE (ram2_write) + .f2h_sdram2_ADDRESS (f2h_ram2_address), + .f2h_sdram2_BURSTCOUNT (f2h_ram2_burstcount), + .f2h_sdram2_WAITREQUEST (f2h_ram2_waitrequest), + .f2h_sdram2_READDATA (f2h_ram2_readdata), + .f2h_sdram2_READDATAVALID (f2h_ram2_readdatavalid), + .f2h_sdram2_READ (f2h_ram2_read), + .f2h_sdram2_WRITEDATA (f2h_ram2_writedata), + .f2h_sdram2_BYTEENABLE (f2h_ram2_byteenable), + .f2h_sdram2_WRITE (f2h_ram2_write) ); wire hps_h2f_reset_n; diff --git a/sys/vga_out.sv b/sys/vga_out.sv index e316000..4160635 100644 --- a/sys/vga_out.sv +++ b/sys/vga_out.sv @@ -1,65 +1,73 @@ module vga_out ( - input ypbpr_full, + input clk, input ypbpr_en, + input hsync, + input vsync, + input csync, + input de, + input [23:0] din, - output [23:0] dout + output [23:0] dout, + + output reg hsync_o, + output reg vsync_o, + output reg csync_o, + output reg de_o ); -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -wire [5:0] red = din[23:18]; -wire [5:0] green = din[15:10]; -wire [5:0] blue = din[7:2]; +wire [7:0] red = din[23:16]; +wire [7:0] green = din[15:8]; +wire [7:0] blue = din[7:0]; // http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; +// Y = 0.301*R + 0.586*G + 0.113*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.168*R - 0.332*G + 0.500*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.500*R - 0.418*G - 0.082*B (Pr = 0.500*R - 0.419*G - 0.081*B) -assign dout[23:16] = ypbpr_en ? {(ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]), 2'b00} : din[23:16]; -assign dout[15:8] = ypbpr_en ? {(ypbpr_full ? yuv_full[y -8'd16] : y[7:2]), 2'b00} : din[15:8]; -assign dout[7:0] = ypbpr_en ? {(ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]), 2'b00} : din[7:0]; +reg [7:0] y, pb, pr; +reg [23:0] rgb; +always @(posedge clk) begin + reg [18:0] y_1r, pb_1r, pr_1r; + reg [18:0] y_1g, pb_1g, pr_1g; + reg [18:0] y_1b, pb_1b, pr_1b; + reg [18:0] y_2, pb_2, pr_2; + reg [23:0] din1, din2; + reg hsync2, vsync2, csync2, de2; + reg hsync1, vsync1, csync1, de1; + y_1r <= {red, 6'd0} + {red, 3'd0} + {red, 2'd0} + red; + pb_1r <= 19'd32768 - ({red, 5'd0} + {red, 3'd0} + {red, 1'd0}); + pr_1r <= 19'd32768 + {red, 7'd0}; + + y_1g <= {green, 7'd0} + {green, 4'd0} + {green, 2'd0} + {green, 1'd0}; + pb_1g <= {green, 6'd0} + {green, 4'd0} + {green, 2'd0} + green; + pr_1g <= {green, 6'd0} + {green, 5'd0} + {green, 3'd0} + {green, 1'd0}; + + y_1b <= {blue, 4'd0} + {blue, 3'd0} + {blue, 2'd0} + blue; + pb_1b <= {blue, 7'd0}; + pr_1b <= {blue, 4'd0} + {blue, 2'd0} + blue; + + y_2 <= y_1r + y_1g + y_1b; + pb_2 <= pb_1r - pb_1g + pb_1b; + pr_2 <= pr_1r - pr_1g - pr_1b; + + y <= y_2[18] ? 8'd0 : y_2[16] ? 8'd255 : y_2[15:8]; + pb <= pb_2[18] ? 8'd0 : pb_2[16] ? 8'd255 : pb_2[15:8]; + pr <= pr_2[18] ? 8'd0 : pr_2[16] ? 8'd255 : pr_2[15:8]; + + hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync; + vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync; + csync_o <= csync2; csync2 <= csync1; csync1 <= csync; + de_o <= de2; de2 <= de1; de1 <= de; + + rgb <= din2; din2 <= din1; din1 <= din; +end + +assign dout = ypbpr_en ? {pr, y, pb} : rgb; endmodule diff --git a/sys/video_cleaner.sv b/sys/video_cleaner.sv index a99894c..4c057a8 100644 --- a/sys/video_cleaner.sv +++ b/sys/video_cleaner.sv @@ -1,99 +1,108 @@ -// -// -// Copyright (c) 2018 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -module video_cleaner -( - input clk_vid, - input ce_pix, - - input [7:0] R, - input [7:0] G, - input [7:0] B, - - input HSync, - input VSync, - input HBlank, - input VBlank, - - //optional de - input DE_in, - - // video output signals - output reg [7:0] VGA_R, - output reg [7:0] VGA_G, - output reg [7:0] VGA_B, - output reg VGA_VS, - output reg VGA_HS, - output VGA_DE, - - // optional aligned blank - output reg HBlank_out, - output reg VBlank_out, - - // optional aligned de - output reg DE_out -); - -wire hs, vs; -s_fix sync_v(clk_vid, HSync, hs); -s_fix sync_h(clk_vid, VSync, vs); - -wire hbl = hs | HBlank; -wire vbl = vs | VBlank; - -assign VGA_DE = ~(HBlank_out | VBlank_out); - -always @(posedge clk_vid) begin - if(ce_pix) begin - HBlank_out <= hbl; - - VGA_HS <= hs; - if(~VGA_HS & hs) VGA_VS <= vs; - - VGA_R <= R; - VGA_G <= G; - VGA_B <= B; - DE_out <= DE_in; - - if(HBlank_out & ~hbl) VBlank_out <= vbl; - end -end - -endmodule - -module s_fix -( - input clk, - - input sync_in, - output sync_out -); - -assign sync_out = sync_in ^ pol; - -reg pol; -always @(posedge clk) begin - integer pos = 0, neg = 0, cnt = 0; - reg s1,s2; - - s1 <= sync_in; - s2 <= s1; - - if(~s2 & s1) neg <= cnt; - if(s2 & ~s1) pos <= cnt; - - cnt <= cnt + 1; - if(s2 != s1) cnt <= 0; - - pol <= pos > neg; -end - -endmodule +// +// +// Copyright (c) 2018 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +module video_cleaner +( + input clk_vid, + input ce_pix, + + input [7:0] R, + input [7:0] G, + input [7:0] B, + + input HSync, + input VSync, + input HBlank, + input VBlank, + + //optional de + input DE_in, + + //optional interlace support + input interlace, + input f1, + + // video output signals + output reg [7:0] VGA_R, + output reg [7:0] VGA_G, + output reg [7:0] VGA_B, + output reg VGA_VS, + output reg VGA_HS, + output VGA_DE, + + // optional aligned blank + output reg HBlank_out, + output reg VBlank_out, + + // optional aligned de + output reg DE_out +); + +wire hs, vs; +s_fix sync_v(clk_vid, HSync, hs); +s_fix sync_h(clk_vid, VSync, vs); + +wire hbl = hs | HBlank; +wire vbl = vs | VBlank; + +assign VGA_DE = ~(HBlank_out | VBlank_out); + +always @(posedge clk_vid) begin + if(ce_pix) begin + HBlank_out <= hbl; + + VGA_HS <= hs; + + VGA_R <= R; + VGA_G <= G; + VGA_B <= B; + DE_out <= DE_in; + + if (interlace & f1) begin + VGA_VS <= vs; + VBlank_out <= vbl; + end else begin + if(~VGA_HS & hs) VGA_VS <= vs; + if(HBlank_out & ~hbl) VBlank_out <= vbl; + end + end +end + +endmodule + +module s_fix +( + input clk, + + input sync_in, + output sync_out +); + +assign sync_out = sync_in ^ pol; + +reg pol; +always @(posedge clk) begin + integer pos = 0, neg = 0, cnt = 0; + reg s1,s2; + + s1 <= sync_in; + s2 <= s1; + + if(~s2 & s1) neg <= cnt; + if(s2 & ~s1) pos <= cnt; + + cnt <= cnt + 1; + if(s2 != s1) cnt <= 0; + + pol <= pos > neg; +end + +endmodule diff --git a/sys/video_freak.sv b/sys/video_freak.sv new file mode 100644 index 0000000..65375cd --- /dev/null +++ b/sys/video_freak.sv @@ -0,0 +1,329 @@ +// +// +// Video crop +// Copyright (c) 2020 Grabulosaure, (c) 2021 Alexey Melnikov +// +// Integer scaling +// Copyright (c) 2021 Alexey Melnikov +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +module video_freak +( + input CLK_VIDEO, + input CE_PIXEL, + input VGA_VS, + input [11:0] HDMI_WIDTH, + input [11:0] HDMI_HEIGHT, + output VGA_DE, + output reg [12:0] VIDEO_ARX, + output reg [12:0] VIDEO_ARY, + + input VGA_DE_IN, + input [11:0] ARX, + input [11:0] ARY, + input [11:0] CROP_SIZE, + input [4:0] CROP_OFF, // -16...+15 + input [2:0] SCALE //0 - normal, 1 - V-integer, 2 - HV-Integer-, 3 - HV-Integer+, 4 - HV-Integer +); + +reg mul_start; +wire mul_run; +reg [11:0] mul_arg1, mul_arg2; +wire [23:0] mul_res; +sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res); + +reg vde; +reg [11:0] arxo,aryo; +reg [11:0] vsize; +reg [11:0] hsize; + +always @(posedge CLK_VIDEO) begin + reg old_de, old_vs,ovde; + reg [11:0] vtot,vcpt,vcrop,voff; + reg [11:0] hcpt; + reg [11:0] vadj; + reg [23:0] ARXG,ARYG; + reg [11:0] arx,ary; + reg [1:0] vcalc; + + if (CE_PIXEL) begin + old_de <= VGA_DE_IN; + old_vs <= VGA_VS; + if (VGA_VS & ~old_vs) begin + vcpt <= 0; + vtot <= vcpt; + vcalc <= 1; + vcrop <= (CROP_SIZE >= vcpt) ? 12'd0 : CROP_SIZE; + end + + if (VGA_DE_IN) hcpt <= hcpt + 1'd1; + if (~VGA_DE_IN & old_de) begin + vcpt <= vcpt + 1'd1; + if(!vcpt) hsize <= hcpt; + hcpt <= 0; + end + end + + arx <= ARX; + ary <= ARY; + + vsize <= vcrop ? vcrop : vtot; + + mul_start <= 0; + + if(!vcrop || !ary || !arx) begin + arxo <= arx; + aryo <= ary; + end + else if (vcalc) begin + if(~mul_start & ~mul_run) begin + vcalc <= vcalc + 1'd1; + case(vcalc) + 1: begin + mul_arg1 <= arx; + mul_arg2 <= vtot; + mul_start <= 1; + end + + 2: begin + ARXG <= mul_res; + mul_arg1 <= ary; + mul_arg2 <= vcrop; + mul_start <= 1; + end + + 3: begin + ARYG <= mul_res; + end + endcase + end + end + else if (ARXG[23] | ARYG[23]) begin + arxo <= ARXG[23:12]; + aryo <= ARYG[23:12]; + end + else begin + ARXG <= ARXG << 1; + ARYG <= ARYG << 1; + end + + vadj <= (vtot-vcrop) + {{6{CROP_OFF[4]}},CROP_OFF,1'b0}; + voff <= vadj[11] ? 12'd0 : ((vadj[11:1] + vcrop) > vtot) ? vtot-vcrop : vadj[11:1]; + ovde <= ((vcpt >= voff) && (vcpt < (vcrop + voff))) || !vcrop; + vde <= ovde; +end + +assign VGA_DE = vde & VGA_DE_IN; + +video_scale_int scale +( + .CLK_VIDEO(CLK_VIDEO), + .HDMI_WIDTH(HDMI_WIDTH), + .HDMI_HEIGHT(HDMI_HEIGHT), + .SCALE(SCALE), + .hsize(hsize), + .vsize(vsize), + .arx_i(arxo), + .ary_i(aryo), + .arx_o(VIDEO_ARX), + .ary_o(VIDEO_ARY) +); + +endmodule + + +module video_scale_int +( + input CLK_VIDEO, + + input [11:0] HDMI_WIDTH, + input [11:0] HDMI_HEIGHT, + + input [2:0] SCALE, + + input [11:0] hsize, + input [11:0] vsize, + + input [11:0] arx_i, + input [11:0] ary_i, + + output reg [12:0] arx_o, + output reg [12:0] ary_o +); + +reg div_start; +wire div_run; +reg [23:0] div_num; +reg [11:0] div_den; +wire [23:0] div_res; +sys_udiv #(24,12) div(CLK_VIDEO,div_start,div_run, div_num,div_den,div_res); + +reg mul_start; +wire mul_run; +reg [11:0] mul_arg1, mul_arg2; +wire [23:0] mul_res; +sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res); + +always @(posedge CLK_VIDEO) begin + reg [11:0] oheight,htarget,wres,hinteger,wideres; + reg [12:0] arxf,aryf; + reg [3:0] cnt; + reg narrow; + + div_start <= 0; + mul_start <= 0; + + if (!SCALE || (!ary_i && arx_i)) begin + arxf <= arx_i; + aryf <= ary_i; + end + else if(~div_start & ~div_run & ~mul_start & ~mul_run) begin + cnt <= cnt + 1'd1; + case(cnt) + // example ideal and non-ideal cases: + // [1] 720x400 4:3 VGA 80x25 text-mode (non-square pixels) + // [2] 640x480 4:3 VGA graphics mode (square pixels) + // [3] 512x512 4:3 X68000 graphics mode (non-square pixels) + 0: begin + div_num <= HDMI_HEIGHT; + div_den <= vsize; + div_start <= 1; + end + // [1] 1080 / 400 -> 2 + // [2] 1080 / 480 -> 2 + // [3] 1080 / 512 -> 2 + + 1: if(!div_res[11:0]) begin + // screen resolution is lower than video resolution. + // Integer scaling is impossible. + arxf <= arx_i; + aryf <= ary_i; + cnt <= 0; + end + else begin + mul_arg1 <= vsize; + mul_arg2 <= div_res[11:0]; + mul_start <= 1; + end + // [1] 1080 / 400 * 400 -> 800 + // [2] 1080 / 480 * 480 -> 960 + // [3] 1080 / 512 * 512 -> 1024 + + 2: begin + oheight <= mul_res[11:0]; + if(!ary_i) begin + cnt <= 8; + end + end + + 3: begin + mul_arg1 <= mul_res[11:0]; + mul_arg2 <= arx_i; + mul_start <= 1; + end + // [1] 1080 / 400 * 400 * 4 -> 3200 + // [2] 1080 / 480 * 480 * 4 -> 3840 + // [3] 1080 / 512 * 512 * 4 -> 4096 + + 4: begin + div_num <= mul_res; + div_den <= ary_i; + div_start <= 1; + end + // [1] 1080 / 480 * 480 * 4 / 3 -> 1066 + // [2] 1080 / 480 * 480 * 4 / 3 -> 1280 + // [3] 1080 / 512 * 512 * 4 / 3 -> 1365 + // saved as htarget + + 5: begin + htarget <= div_res[11:0]; + div_num <= div_res; + div_den <= hsize; + div_start <= 1; + end + // computes wide scaling factor as a ceiling division + // [1] 1080 / 400 * 400 * 4 / 3 / 720 -> 1 + // [2] 1080 / 480 * 480 * 4 / 3 / 640 -> 2 + // [3] 1080 / 512 * 512 * 4 / 3 / 512 -> 2 + + 6: begin + mul_arg1 <= hsize; + mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1; + mul_start <= 1; + end + // [1] 1080 / 400 * 400 * 4 / 3 / 720 * 720 -> 720 + // [2] 1080 / 480 * 480 * 4 / 3 / 640 * 640 -> 1280 + // [3] 1080 / 512 * 512 * 4 / 3 / 512 * 512 -> 1024 + + 7: if(mul_res <= HDMI_WIDTH) begin + hinteger = mul_res[11:0]; + cnt <= 12; + end + + 8: begin + div_num <= HDMI_WIDTH; + div_den <= hsize; + div_start <= 1; + end + // [1] 1920 / 720 -> 2 + // [2] 1920 / 640 -> 3 + // [3] 1920 / 512 -> 3 + + 9: begin + mul_arg1 <= hsize; + mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1; + mul_start <= 1; + end + // [1] 1920 / 720 * 720 -> 1440 + // [2] 1920 / 640 * 640 -> 1920 + // [3] 1920 / 512 * 512 -> 1536 + + 10: begin + hinteger <= mul_res[11:0]; + mul_arg1 <= vsize; + mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1; + mul_start <= 1; + end + + 11: begin + oheight <= mul_res[11:0]; + end + + 12: begin + wideres <= hinteger + hsize; + narrow <= ((htarget - hinteger) <= (wideres - htarget)) || (wideres > HDMI_WIDTH); + wres <= hinteger == htarget ? hinteger : wideres; + end + // [1] 1066 - 720 = 346 <= 1440 - 1066 = 374 || 1440 > 1920 -> true + // [2] 1280 - 1280 = 0 <= 1920 - 1280 = 640 || 1920 > 1920 -> true + // [3] 1365 - 1024 = 341 <= 1536 - 1365 = 171 || 1536 > 1920 -> false + // 1. narrow flag is true when mul_res[11:0] narrow width is closer to + // htarget aspect ratio target width or when wideres wider width + // does not fit to the screen. + // 2. wres becomes wideres only when mul_res[11:0] narrow width not equal + // to target width, meaning it is not optimal for source aspect ratio. + // otherwise it is set to narrow width that is optimal. + + 13: begin + case(SCALE) + 2: arxf <= {1'b1, hinteger}; + 3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? hinteger : wres}; + 4: arxf <= {1'b1, narrow ? hinteger : wres}; + default: arxf <= {1'b1, div_num[11:0]}; + endcase + aryf <= {1'b1, oheight}; + end + endcase + end + + arx_o <= arxf; + ary_o <= aryf; +end + +endmodule diff --git a/sys/video_freezer.sv b/sys/video_freezer.sv new file mode 100644 index 0000000..24d2c65 --- /dev/null +++ b/sys/video_freezer.sv @@ -0,0 +1,143 @@ +// +// video freeze with sync +// (C) Alexey Melnikov +// +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + + +module video_freezer +( + input clk, + + output sync, + input freeze, + + input hs_in, + input vs_in, + input hbl_in, + input vbl_in, + + output hs_out, + output vs_out, + output hbl_out, + output vbl_out +); + +sync_lock #(33) vs_lock +( + .clk(clk), + .sync_in(vs_in), + .sync_out(vs_out), + .de_in(vbl_in), + .de_out(vbl_out), + .freeze(freeze) +); + +wire sync_pt; +sync_lock #(21) hs_lock +( + .clk(clk), + .sync_in(hs_in), + .sync_out(hs_out), + .de_in(hbl_in), + .de_out(hbl_out), + .freeze(freeze), + .sync_pt(sync_pt) +); + +reg sync_o; +always @(posedge clk) begin + reg old_hs, old_vs; + reg vs_sync; + + old_vs <= vs_out; + + if(~old_vs & vs_out) vs_sync <= 1; + if(sync_pt & vs_sync) begin + vs_sync <= 0; + sync_o <= ~sync_o; + end +end + +assign sync = sync_o; + +endmodule + + +module sync_lock #(parameter WIDTH) +( + input clk, + + input sync_in, + input de_in, + + output sync_out, + output de_out, + + input freeze, + output sync_pt, + output valid +); + +reg [WIDTH-1:0] f_len, s_len, de_start, de_end; +reg sync_valid; + +reg old_sync; +always @(posedge clk) old_sync <= sync_in; + +always @(posedge clk) begin + reg [WIDTH-1:0] cnti; + reg f_valid; + reg old_de; + + cnti <= cnti + 1'd1; + if(~old_sync & sync_in) begin + if(sync_valid) f_len <= cnti; + f_valid <= 1; + sync_valid <= f_valid; + cnti <= 0; + end + + if(old_sync & ~sync_in & sync_valid) s_len <= cnti; + + old_de <= de_in; + if(~old_de & de_in & sync_valid) de_start <= cnti; + if(old_de & ~de_in & sync_valid) de_end <= cnti; + + if(freeze) {f_valid, sync_valid} <= 0; +end + +reg sync_o, de_o, sync_o_pre; +always @(posedge clk) begin + reg [WIDTH-1:0] cnto; + + cnto <= cnto + 1'd1; + if(old_sync & ~sync_in & sync_valid) cnto <= s_len + 2'd2; + if(cnto == f_len) cnto <= 0; + + sync_o_pre <= (cnto == (s_len>>1)); // middle in sync + if(cnto == f_len) sync_o <= 1; + if(cnto == s_len) sync_o <= 0; + if(cnto == de_start) de_o <= 1; + if(cnto == de_end) de_o <= 0; +end + +assign sync_out = freeze ? sync_o : sync_in; +assign valid = sync_valid; +assign sync_pt = sync_o_pre; +assign de_out = freeze ? de_o : de_in; + +endmodule diff --git a/sys/video_mixer.sv b/sys/video_mixer.sv index 82c9e51..e53e1c0 100644 --- a/sys/video_mixer.sv +++ b/sys/video_mixer.sv @@ -1,238 +1,219 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 4 bits per component -// For half depth 8 bits monochrome is available with -// mono signal enabled and color = {G, R} -// -// altera message_off 10720 -// altera message_off 12161 - -module video_mixer -#( - parameter LINE_LENGTH = 768, - parameter HALF_DEPTH = 0, - parameter GAMMA = 0 -) -( - // video clock - // it should be multiple by (ce_pix*4). - input clk_vid, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - output ce_pix_out, - - input scandoubler, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // High quality 2x scaling - input hq2x, - - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - inout [21:0] gamma_bus, - - // Positive pulses. - input HSync, - input VSync, - input HBlank, - input VBlank, - - // video output signals - output reg [7:0] VGA_R, - output reg [7:0] VGA_G, - output reg [7:0] VGA_B, - output reg VGA_VS, - output reg VGA_HS, - output reg VGA_DE -); - -localparam DWIDTH = HALF_DEPTH ? 3 : 7; -localparam DWIDTH_SD = GAMMA ? 7 : DWIDTH; -localparam HALF_DEPTH_SD = GAMMA ? 0 : HALF_DEPTH; - -generate - if(GAMMA && HALF_DEPTH) begin - wire [7:0] R_in = mono ? {G,R} : {R,R}; - wire [7:0] G_in = mono ? {G,R} : {G,G}; - wire [7:0] B_in = mono ? {G,R} : {B,B}; - end else begin - wire [DWIDTH:0] R_in = R; - wire [DWIDTH:0] G_in = G; - wire [DWIDTH:0] B_in = B; - end -endgenerate - - -wire hs_g, vs_g; -wire hb_g, vb_g; -wire [DWIDTH_SD:0] R_gamma, G_gamma, B_gamma; - -generate - if(GAMMA) begin - assign gamma_bus[21] = 1; - gamma_corr gamma( - .clk_sys(gamma_bus[20]), - .clk_vid(clk_vid), - .ce_pix(ce_pix), - - .gamma_en(gamma_bus[19]), - .gamma_wr(gamma_bus[18]), - .gamma_wr_addr(gamma_bus[17:8]), - .gamma_value(gamma_bus[7:0]), - - .HSync(HSync), - .VSync(VSync), - .HBlank(HBlank), - .VBlank(VBlank), - .RGB_in({R_in,G_in,B_in}), - - .HSync_out(hs_g), - .VSync_out(vs_g), - .HBlank_out(hb_g), - .VBlank_out(vb_g), - .RGB_out({R_gamma,G_gamma,B_gamma}) - ); - end else begin - assign gamma_bus[21] = 0; - assign {R_gamma,G_gamma,B_gamma} = {R_in,G_in,B_in}; - assign {hs_g, vs_g, hb_g, vb_g} = {HSync, VSync, HBlank, VBlank}; - end -endgenerate - - -wire [DWIDTH_SD:0] R_sd; -wire [DWIDTH_SD:0] G_sd; -wire [DWIDTH_SD:0] B_sd; -wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH_SD)) sd -( - .*, - .hs_in(hs_g), - .vs_in(vs_g), - .hb_in(hb_g), - .vb_in(vb_g), - .r_in(R_gamma), - .g_in(G_gamma), - .b_in(B_gamma), - - .ce_pix_out(ce_pix_sd), - .hs_out(hs_sd), - .vs_out(vs_sd), - .hb_out(hb_sd), - .vb_out(vb_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH_SD:0] rt = (scandoubler ? R_sd : R_gamma); -wire [DWIDTH_SD:0] gt = (scandoubler ? G_sd : G_gamma); -wire [DWIDTH_SD:0] bt = (scandoubler ? B_sd : B_gamma); - -generate - if(!GAMMA && HALF_DEPTH) begin - wire [7:0] r = mono ? {gt,rt} : {rt,rt}; - wire [7:0] g = mono ? {gt,rt} : {gt,gt}; - wire [7:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [7:0] r = rt; - wire [7:0] g = gt; - wire [7:0] b = bt; - end -endgenerate - -wire hs = (scandoubler ? hs_sd : hs_g); -wire vs = (scandoubler ? vs_sd : vs_g); - -assign ce_pix_out = scandoubler ? ce_pix_sd : ce_pix; - - -reg scanline = 0; -always @(posedge clk_vid) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire hde = scandoubler ? ~hb_sd : ~hb_g; -wire vde = scandoubler ? ~vb_sd : ~vb_g; - -reg [7:0] v_r,v_g,v_b; -reg v_vs,v_hs,v_de; -always @(posedge clk_vid) begin - reg old_hde; - - if(ce_pix_out) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - v_r <= {1'b0, r[7:1]} + {2'b00, r[7:2]}; - v_g <= {1'b0, g[7:1]} + {2'b00, g[7:2]}; - v_b <= {1'b0, b[7:1]} + {2'b00, b[7:2]}; - end - - 2: begin // reduce 50% = 1/2 - v_r <= {1'b0, r[7:1]}; - v_g <= {1'b0, g[7:1]}; - v_b <= {1'b0, b[7:1]}; - end - - 3: begin // reduce 75% = 1/4 - v_r <= {2'b00, r[7:2]}; - v_g <= {2'b00, g[7:2]}; - v_b <= {2'b00, b[7:2]}; - end - - default: begin - v_r <= r; - v_g <= g; - v_b <= b; - end - endcase - - v_vs <= vs; - v_hs <= hs; - - old_hde <= hde; - if(~old_hde && hde) v_de <= vde; - if(old_hde && ~hde) v_de <= 0; - end -end - -always @(posedge clk_vid) if(ce_pix_out) begin - VGA_R <= v_r; - VGA_G <= v_g; - VGA_B <= v_b; - VGA_HS <= v_hs; - VGA_VS <= v_vs; - VGA_DE <= v_de; -end - -endmodule +// +// +// Copyright (c) 2017,2021 Alexey Melnikov +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels when HBlank = 0; +// HALF_DEPTH: If =1 then color dept is 4 bits per component +// +// altera message_off 10720 +// altera message_off 12161 + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0, + parameter GAMMA = 0 +) +( + input CLK_VIDEO, // should be multiple by (ce_pix*4) + output reg CE_PIXEL, // output pixel clock enable + + input ce_pix, // input pixel clock or clock_enable + + input scandoubler, + input hq2x, // high quality 2x scaling + + inout [21:0] gamma_bus, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Positive pulses. + input HSync, + input VSync, + input HBlank, + input VBlank, + + // Freeze engine + // HDMI: displays last frame + // VGA: black screen with HSync and VSync + input HDMI_FREEZE, + output freeze_sync, + + // video output signals + output reg [7:0] VGA_R, + output reg [7:0] VGA_G, + output reg [7:0] VGA_B, + output reg VGA_VS, + output reg VGA_HS, + output reg VGA_DE +); + +localparam DWIDTH = HALF_DEPTH ? 3 : 7; +localparam DWIDTH_SD = GAMMA ? 7 : DWIDTH; +localparam HALF_DEPTH_SD = GAMMA ? 0 : HALF_DEPTH; + +wire frz_hs, frz_vs; +wire frz_hbl, frz_vbl; +video_freezer freezer +( + .clk(CLK_VIDEO), + .freeze(HDMI_FREEZE), + .hs_in(HSync), + .vs_in(VSync), + .hbl_in(HBlank), + .vbl_in(VBlank), + .sync(freeze_sync), + .hs_out(frz_hs), + .vs_out(frz_vs), + .hbl_out(frz_hbl), + .vbl_out(frz_vbl) +); + +reg frz; +always @(posedge CLK_VIDEO) begin + reg frz1; + + frz1 <= HDMI_FREEZE; + frz <= frz1; +end + +generate + if(GAMMA && HALF_DEPTH) begin + wire [7:0] R_in = frz ? 8'd0 : {R,R}; + wire [7:0] G_in = frz ? 8'd0 : {G,G}; + wire [7:0] B_in = frz ? 8'd0 : {B,B}; + end else begin + wire [DWIDTH:0] R_in = frz ? 1'd0 : R; + wire [DWIDTH:0] G_in = frz ? 1'd0 : G; + wire [DWIDTH:0] B_in = frz ? 1'd0 : B; + end +endgenerate + +wire hs_g, vs_g; +wire hb_g, vb_g; +wire [DWIDTH_SD:0] R_gamma, G_gamma, B_gamma; + +generate + if(GAMMA) begin + assign gamma_bus[21] = 1; + gamma_corr gamma( + .clk_sys(gamma_bus[20]), + .clk_vid(CLK_VIDEO), + .ce_pix(ce_pix), + + .gamma_en(gamma_bus[19]), + .gamma_wr(gamma_bus[18]), + .gamma_wr_addr(gamma_bus[17:8]), + .gamma_value(gamma_bus[7:0]), + + .HSync(frz_hs), + .VSync(frz_vs), + .HBlank(frz_hbl), + .VBlank(frz_vbl), + .RGB_in({R_in,G_in,B_in}), + + .HSync_out(hs_g), + .VSync_out(vs_g), + .HBlank_out(hb_g), + .VBlank_out(vb_g), + .RGB_out({R_gamma,G_gamma,B_gamma}) + ); + end else begin + assign gamma_bus[21] = 0; + assign {R_gamma,G_gamma,B_gamma} = {R_in,G_in,B_in}; + assign {hs_g, vs_g, hb_g, vb_g} = {frz_hs, frz_vs, frz_hbl, frz_vbl}; + end +endgenerate + +wire [DWIDTH_SD:0] R_sd; +wire [DWIDTH_SD:0] G_sd; +wire [DWIDTH_SD:0] B_sd; +wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH_SD)) sd +( + .clk_vid(CLK_VIDEO), + .hq2x(hq2x), + + .ce_pix(ce_pix), + .hs_in(hs_g), + .vs_in(vs_g), + .hb_in(hb_g), + .vb_in(vb_g), + .r_in(R_gamma), + .g_in(G_gamma), + .b_in(B_gamma), + + .ce_pix_out(ce_pix_sd), + .hs_out(hs_sd), + .vs_out(vs_sd), + .hb_out(hb_sd), + .vb_out(vb_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH_SD:0] rt = (scandoubler ? R_sd : R_gamma); +wire [DWIDTH_SD:0] gt = (scandoubler ? G_sd : G_gamma); +wire [DWIDTH_SD:0] bt = (scandoubler ? B_sd : B_gamma); + +always @(posedge CLK_VIDEO) begin + reg [7:0] r,g,b; + reg hde,vde,hs,vs, old_vs; + reg old_hde; + reg old_ce; + reg ce_osc, fs_osc; + + old_ce <= ce_pix; + ce_osc <= ce_osc | (old_ce ^ ce_pix); + + old_vs <= vs; + if(~old_vs & vs) begin + fs_osc <= ce_osc; + ce_osc <= 0; + end + + CE_PIXEL <= scandoubler ? ce_pix_sd : fs_osc ? (~old_ce & ce_pix) : ce_pix; + + if(!GAMMA && HALF_DEPTH) begin + r <= {rt,rt}; + g <= {gt,gt}; + b <= {bt,bt}; + end + else begin + r <= rt; + g <= gt; + b <= bt; + end + + hde <= scandoubler ? ~hb_sd : ~hb_g; + vde <= scandoubler ? ~vb_sd : ~vb_g; + vs <= scandoubler ? vs_sd : vs_g; + hs <= scandoubler ? hs_sd : hs_g; + + if(CE_PIXEL) begin + VGA_R <= r; + VGA_G <= g; + VGA_B <= b; + + VGA_VS <= vs; + VGA_HS <= hs; + + old_hde <= hde; + if(old_hde ^ hde) VGA_DE <= vde & hde; + end +end + +endmodule diff --git a/sys/yc_out.sv b/sys/yc_out.sv new file mode 100644 index 0000000..984fc37 --- /dev/null +++ b/sys/yc_out.sv @@ -0,0 +1,233 @@ +//============================================================================ +// YC - Luma / Chroma Generation +// Copyright (C) 2022 Mike Simone +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +//============================================================================ +/* +Colorspace +Y 0.299R' + 0.587G' + 0.114B' +U 0.492(B' - Y) = 504 (X 1024) +V 0.877(R' - Y) = 898 (X 1024) +*/ +////////////////////////////////////////////////////////// + +module yc_out +( + input clk, + input [39:0] PHASE_INC, + input PAL_EN, + input CVBS, + input [16:0] COLORBURST_RANGE, + + input hsync, + input vsync, + input csync, + input de, + + input [23:0] din, + output [23:0] dout, + + output reg hsync_o, + output reg vsync_o, + output reg csync_o, + output reg de_o +); + +wire [7:0] red = din[23:16]; +wire [7:0] green = din[15:8]; +wire [7:0] blue = din[7:0]; + +logic [9:0] red_1, blue_1, green_1, red_2, blue_2, green_2; + +logic signed [20:0] yr = 0, yb = 0, yg = 0; + +typedef struct { + logic signed [20:0] y; + logic signed [20:0] c; + logic signed [20:0] u; + logic signed [20:0] v; + logic hsync; + logic vsync; + logic csync; + logic de; +} phase_t; + +localparam MAX_PHASES = 7'd8; + +phase_t phase[MAX_PHASES]; +reg unsigned [7:0] Y, C, c, U, V; + + +reg [10:0] cburst_phase; // colorburst counter +reg unsigned [7:0] vref = 'd128; // Voltage reference point (Used for Chroma) +logic [7:0] chroma_LUT_COS; // Chroma cos LUT reference +logic [7:0] chroma_LUT_SIN; // Chroma sin LUT reference +logic [7:0] chroma_LUT_BURST; // Chroma colorburst LUT reference +logic [7:0] chroma_LUT = 8'd0; + +/* +THe following LUT table was calculated by Sin(2*pi*t/2^8) where t: 0 - 255 +*/ + +/************************************* + 8 bit Sine look up Table +**************************************/ +wire signed [10:0] chroma_SIN_LUT[256] = '{ + 11'h000, 11'h006, 11'h00C, 11'h012, 11'h018, 11'h01F, 11'h025, 11'h02B, 11'h031, 11'h037, 11'h03D, 11'h044, 11'h04A, 11'h04F, + 11'h055, 11'h05B, 11'h061, 11'h067, 11'h06D, 11'h072, 11'h078, 11'h07D, 11'h083, 11'h088, 11'h08D, 11'h092, 11'h097, 11'h09C, + 11'h0A1, 11'h0A6, 11'h0AB, 11'h0AF, 11'h0B4, 11'h0B8, 11'h0BC, 11'h0C1, 11'h0C5, 11'h0C9, 11'h0CC, 11'h0D0, 11'h0D4, 11'h0D7, + 11'h0DA, 11'h0DD, 11'h0E0, 11'h0E3, 11'h0E6, 11'h0E9, 11'h0EB, 11'h0ED, 11'h0F0, 11'h0F2, 11'h0F4, 11'h0F5, 11'h0F7, 11'h0F8, + 11'h0FA, 11'h0FB, 11'h0FC, 11'h0FD, 11'h0FD, 11'h0FE, 11'h0FE, 11'h0FE, 11'h0FF, 11'h0FE, 11'h0FE, 11'h0FE, 11'h0FD, 11'h0FD, + 11'h0FC, 11'h0FB, 11'h0FA, 11'h0F8, 11'h0F7, 11'h0F5, 11'h0F4, 11'h0F2, 11'h0F0, 11'h0ED, 11'h0EB, 11'h0E9, 11'h0E6, 11'h0E3, + 11'h0E0, 11'h0DD, 11'h0DA, 11'h0D7, 11'h0D4, 11'h0D0, 11'h0CC, 11'h0C9, 11'h0C5, 11'h0C1, 11'h0BC, 11'h0B8, 11'h0B4, 11'h0AF, + 11'h0AB, 11'h0A6, 11'h0A1, 11'h09C, 11'h097, 11'h092, 11'h08D, 11'h088, 11'h083, 11'h07D, 11'h078, 11'h072, 11'h06D, 11'h067, + 11'h061, 11'h05B, 11'h055, 11'h04F, 11'h04A, 11'h044, 11'h03D, 11'h037, 11'h031, 11'h02B, 11'h025, 11'h01F, 11'h018, 11'h012, + 11'h00C, 11'h006, 11'h000, 11'h7F9, 11'h7F3, 11'h7ED, 11'h7E7, 11'h7E0, 11'h7DA, 11'h7D4, 11'h7CE, 11'h7C8, 11'h7C2, 11'h7BB, + 11'h7B5, 11'h7B0, 11'h7AA, 11'h7A4, 11'h79E, 11'h798, 11'h792, 11'h78D, 11'h787, 11'h782, 11'h77C, 11'h777, 11'h772, 11'h76D, + 11'h768, 11'h763, 11'h75E, 11'h759, 11'h754, 11'h750, 11'h74B, 11'h747, 11'h743, 11'h73E, 11'h73A, 11'h736, 11'h733, 11'h72F, + 11'h72B, 11'h728, 11'h725, 11'h722, 11'h71F, 11'h71C, 11'h719, 11'h716, 11'h714, 11'h712, 11'h70F, 11'h70D, 11'h70B, 11'h70A, + 11'h708, 11'h707, 11'h705, 11'h704, 11'h703, 11'h702, 11'h702, 11'h701, 11'h701, 11'h701, 11'h701, 11'h701, 11'h701, 11'h701, + 11'h702, 11'h702, 11'h703, 11'h704, 11'h705, 11'h707, 11'h708, 11'h70A, 11'h70B, 11'h70D, 11'h70F, 11'h712, 11'h714, 11'h716, + 11'h719, 11'h71C, 11'h71F, 11'h722, 11'h725, 11'h728, 11'h72B, 11'h72F, 11'h733, 11'h736, 11'h73A, 11'h73E, 11'h743, 11'h747, + 11'h74B, 11'h750, 11'h754, 11'h759, 11'h75E, 11'h763, 11'h768, 11'h76D, 11'h772, 11'h777, 11'h77C, 11'h782, 11'h787, 11'h78D, + 11'h792, 11'h798, 11'h79E, 11'h7A4, 11'h7AA, 11'h7B0, 11'h7B5, 11'h7BB, 11'h7C2, 11'h7C8, 11'h7CE, 11'h7D4, 11'h7DA, 11'h7E0, + 11'h7E7, 11'h7ED, 11'h7F3, 11'h7F9 +}; + +logic [39:0] phase_accum; +logic PAL_FLIP = 1'd0; +logic PAL_line_count = 1'd0; + +/************************************** + Generate Luma and Chroma Signals +***************************************/ + +always_ff @(posedge clk) begin + for (logic [3:0] x = 0; x < (MAX_PHASES - 1'd1); x = x + 1'd1) begin + phase[x + 1] <= phase[x]; + end + + // delay red / blue signals to align luma with U/V calculation (Fixes colorbleeding) + red_1 <= red; + blue_1 <= blue; + red_2 <= red_1; + blue_2 <= blue_1; + + // Calculate Luma signal + yr <= {red, 8'd0} + {red, 5'd0}+ {red, 4'd0} + {red, 1'd0}; + yg <= {green, 9'd0} + {green, 6'd0} + {green, 4'd0} + {green, 3'd0} + green; + yb <= {blue, 6'd0} + {blue, 5'd0} + {blue, 4'd0} + {blue, 2'd0} + blue; + phase[0].y <= yr + yg + yb; + + // Generate the LUT values using the phase accumulator reference. + phase_accum <= phase_accum + PHASE_INC; + chroma_LUT <= phase_accum[39:32]; + + // Adjust SINE carrier reference for PAL (Also adjust for PAL Switch) + if (PAL_EN) begin + if (PAL_FLIP) + chroma_LUT_BURST <= chroma_LUT + 8'd160; + else + chroma_LUT_BURST <= chroma_LUT + 8'd96; + end else // Adjust SINE carrier reference for NTSC + chroma_LUT_BURST <= chroma_LUT + 8'd128; + + // Prepare LUT values for sin / cos (+90 degress) + chroma_LUT_SIN <= chroma_LUT; + chroma_LUT_COS <= chroma_LUT + 8'd64; + + // Calculate for U, V - Bit Shift Multiple by u = by * 1024 x 0.492 = 504, v = ry * 1024 x 0.877 = 898 + phase[0].u <= $signed({2'b0 ,(blue_2)}) - $signed({2'b0 ,phase[0].y[17:10]}); + phase[0].v <= $signed({2'b0 , (red_2)}) - $signed({2'b0 ,phase[0].y[17:10]}); + phase[1].u <= 21'($signed({phase[0].u, 8'd0}) + $signed({phase[0].u, 7'd0}) + $signed({phase[0].u, 6'd0}) + $signed({phase[0].u, 5'd0}) + $signed({phase[0].u, 4'd0}) + $signed({phase[0].u, 3'd0})); + phase[1].v <= 21'($signed({phase[0].v, 9'd0}) + $signed({phase[0].v, 8'd0}) + $signed({phase[0].v, 7'd0}) + $signed({phase[0].v, 1'd0})); + + phase[0].c <= vref; + phase[1].c <= phase[0].c; + phase[2].c <= phase[1].c; + phase[3].c <= phase[2].c; + + if (hsync) begin // Reset colorburst counter, as well as the calculated cos / sin values. + cburst_phase <= 'd0; + phase[2].u <= 21'b0; + phase[2].v <= 21'b0; + phase[4].c <= phase[3].c; + + if (PAL_line_count) begin + PAL_FLIP <= ~PAL_FLIP; + PAL_line_count <= ~PAL_line_count; + end + end + else begin // Generate Colorburst for 9 cycles + if (cburst_phase >= COLORBURST_RANGE[16:10] && cburst_phase <= COLORBURST_RANGE[9:0]) begin // Start the color burst signal at 40 samples or 0.9 us + // COLORBURST SIGNAL GENERATION (9 CYCLES ONLY or between count 40 - 240) + phase[2].u <= $signed({chroma_SIN_LUT[chroma_LUT_BURST],5'd0}); + phase[2].v <= 21'b0; + + // Division to scale down the results to fit 8 bit. + if (PAL_EN) + phase[3].u <= $signed(phase[2].u[20:8]) + $signed(phase[2].u[20:10]) + $signed(phase[2].u[20:14]); + else + phase[3].u <= $signed(phase[2].u[20:8]) + $signed(phase[2].u[20:11]) + $signed(phase[2].u[20:12]) + $signed(phase[2].u[20:13]); + + phase[3].v <= phase[2].v; + end else begin // MODULATE U, V for chroma + /* + U,V are both multiplied by 1024 earlier to scale for the decimals in the YUV colorspace conversion. + U and V are both divided by 2^10 which introduce chroma subsampling of 4:1:1 (25% or from 8 bit to 6 bit) + */ + phase[2].u <= $signed((phase[1].u)>>>10) * $signed(chroma_SIN_LUT[chroma_LUT_SIN]); + phase[2].v <= $signed((phase[1].v)>>>10) * $signed(chroma_SIN_LUT[chroma_LUT_COS]); + + // Divide U*sin(wt) and V*cos(wt) to fit results to 8 bit + phase[3].u <= $signed(phase[2].u[20:9]) + $signed(phase[2].u[20:10]) + $signed(phase[2].u[20:14]); + phase[3].v <= $signed(phase[2].v[20:9]) + $signed(phase[2].v[20:10]) + $signed(phase[2].u[20:14]); + end + + // Stop the colorburst timer as its only needed for the initial pulse + if (cburst_phase <= COLORBURST_RANGE[9:0]) + cburst_phase <= cburst_phase + 9'd1; + + // Calculate for chroma (Note: "PAL SWITCH" routine flips V * COS(Wt) every other line) + if (PAL_EN) begin + if (PAL_FLIP) + phase[4].c <= vref + phase[3].u - phase[3].v; + else + phase[4].c <= vref + phase[3].u + phase[3].v; + PAL_line_count <= 1'd1; + end else + phase[4].c <= vref + phase[3].u + phase[3].v; + end + + // Adjust sync timing correctly + phase[1].hsync <= hsync; phase[1].vsync <= vsync; phase[1].csync <= csync; phase[1].de <= de; + phase[2].hsync <= phase[1].hsync; phase[2].vsync <= phase[1].vsync; phase[2].csync <= phase[1].csync; phase[2].de <= phase[1].de; + phase[3].hsync <= phase[2].hsync; phase[3].vsync <= phase[2].vsync; phase[3].csync <= phase[2].csync; phase[3].de <= phase[2].de; + phase[4].hsync <= phase[3].hsync; phase[4].vsync <= phase[3].vsync; phase[4].csync <= phase[3].csync; phase[4].de <= phase[3].de; + hsync_o <= phase[4].hsync; vsync_o <= phase[4].vsync; csync_o <= phase[4].csync; de_o <= phase[4].de; + + phase[1].y <= phase[0].y; phase[2].y <= phase[1].y; phase[3].y <= phase[2].y; phase[4].y <= phase[3].y; phase[5].y <= phase[4].y; + + // Set Chroma / Luma output + C <= CVBS ? 8'd0 : phase[4].c[7:0]; + Y <= CVBS ? ({1'b0, phase[5].y[17:11]} + {1'b0, phase[4].c[7:1]}) : phase[5].y[17:10]; +end + +assign dout = {C, Y, 8'd0}; + +endmodule +