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17 lines
240 B
Verilog
17 lines
240 B
Verilog
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module lfsr(
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output [N-1:0] rnd
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);
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parameter N = 63;
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lcell lc0((rnd[N - 1] ^ rnd[N - 10]), rnd[0]);
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generate
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genvar i;
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for (i = 0; i <= N - 2; i = i + 1) begin : lcn
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lcell lc(rnd[i], rnd[i + 1]);
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end
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endgenerate
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endmodule
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