From b0883ca62dd362abd33bc934fda201f156c96d62 Mon Sep 17 00:00:00 2001 From: sorgelig Date: Tue, 26 Feb 2019 18:11:32 +0800 Subject: [PATCH] Update sys. Dim the screen if inactive. More color patterns. --- menu.qsf | 35 ++-- menu.sv | 23 ++- sys/hdmi_lite.sv | 395 --------------------------------------------- sys/hps_io.v | 22 ++- sys/lpf48k.sv | 100 ------------ sys/pattern_vg.v | 176 +++++++++++++------- sys/reset_source.v | 50 ------ sys/scandoubler.v | 160 +++++++++--------- sys/spdif.v | 43 +++-- sys/sys.qip | 2 - sys/sys_top.sdc | 6 +- sys/sys_top.v | 317 ++++++++++++++++++++++++++---------- sys/sysmem.sv | 171 ++++++++++---------- 13 files changed, 602 insertions(+), 898 deletions(-) delete mode 100644 sys/hdmi_lite.sv delete mode 100644 sys/lpf48k.sv delete mode 100644 sys/reset_source.v diff --git a/menu.qsf b/menu.qsf index 37b8be8..d818707 100644 --- a/menu.qsf +++ b/menu.qsf @@ -76,19 +76,6 @@ set_location_assignment PIN_AD4 -to ADC_SDO #============================================================ # ARDUINO #============================================================ -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] set_location_assignment PIN_AG9 -to ARDUINO_IO[3] set_location_assignment PIN_U14 -to ARDUINO_IO[4] set_location_assignment PIN_U13 -to ARDUINO_IO[5] @@ -96,12 +83,22 @@ set_location_assignment PIN_AG8 -to ARDUINO_IO[6] set_location_assignment PIN_AH8 -to ARDUINO_IO[7] set_location_assignment PIN_AF17 -to ARDUINO_IO[8] set_location_assignment PIN_AE15 -to ARDUINO_IO[9] -set_location_assignment PIN_AF15 -to ARDUINO_IO[10] -set_location_assignment PIN_AG16 -to ARDUINO_IO[11] -set_location_assignment PIN_AH11 -to ARDUINO_IO[12] -set_location_assignment PIN_AH12 -to ARDUINO_IO[13] -set_location_assignment PIN_AH9 -to ARDUINO_IO[14] -set_location_assignment PIN_AG11 -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*] + +#============================================================ +# USER PORT +#============================================================ +set_location_assignment PIN_AF15 -to USER_IO[5] +set_location_assignment PIN_AG16 -to USER_IO[4] +set_location_assignment PIN_AH11 -to USER_IO[3] +set_location_assignment PIN_AH12 -to USER_IO[2] +set_location_assignment PIN_AH9 -to USER_IO[1] +set_location_assignment PIN_AG11 -to USER_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_IO[*] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to USER_IO[*] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to USER_IO[*] #============================================================ # SDIO diff --git a/menu.sv b/menu.sv index 947118f..9c1bdd3 100644 --- a/menu.sv +++ b/menu.sv @@ -73,6 +73,7 @@ module emu input SD_CD, output [2:0] PATTERN, + output reg DIM, //High latency DDR3 RAM interface //Use for non-critical time purposes @@ -140,6 +141,7 @@ localparam CONF_STR = { wire forced_scandoubler; wire [1:0] buttons; wire [31:0] status; +wire [10:0] ps2_key; hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io ( @@ -151,14 +153,29 @@ hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io .buttons(buttons), .status(status), - - .ps2_kbd_led_use(0), - .ps2_kbd_led_status(0) + + .ps2_key(ps2_key) ); assign RESET_OUT = buttons[1]; assign PATTERN = status[3:1]; +always @(posedge CLK_50M) begin + integer sec, to; + reg old_stb; + + sec <= sec + 1; + if(sec >= 50000000) begin + sec <= 0; + to <= to + 1; + end + + DIM <= (to >= 120); + + old_stb <= ps2_key[10]; + if((old_stb ^ ps2_key[10]) || status[0] || buttons[1]) to <= 0; +end + //////////////////// CLOCKS /////////////////// wire locked, clk_sys; diff --git a/sys/hdmi_lite.sv b/sys/hdmi_lite.sv deleted file mode 100644 index 96eb441..0000000 --- a/sys/hdmi_lite.sv +++ /dev/null @@ -1,395 +0,0 @@ -//============================================================================ -// -// HDMI Lite output module -// Copyright (C) 2017 Sorgelig -// -// This program is free software; you can redistribute it and/or modify it -// under the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 of the License, or (at your option) -// any later version. -// -//============================================================================ - - -module hdmi_lite -( - input reset, - - input clk_video, - input ce_pixel, - input video_vs, - input video_de, - input [23:0] video_d, - - input clk_hdmi, - input hdmi_hde, - input hdmi_vde, - output reg hdmi_de, - output [23:0] hdmi_d, - - input [11:0] screen_w, - input [11:0] screen_h, - input quadbuf, - - // 0-3 => scale 1-4 - input [1:0] scale_x, - input [1:0] scale_y, - input scale_auto, - - input clk_vbuf, - output [27:0] vbuf_address, - input [127:0] vbuf_readdata, - output [127:0] vbuf_writedata, - output [7:0] vbuf_burstcount, - output [15:0] vbuf_byteenable, - input vbuf_waitrequest, - input vbuf_readdatavalid, - output reg vbuf_read, - output reg vbuf_write -); - -localparam [7:0] burstsz = 64; - -reg [1:0] nbuf = 0; -wire [27:0] read_buf = {4'd2, 3'b000, (quadbuf ? nbuf-2'd1 : 2'b00), 19'd0}; -wire [27:0] write_buf = {4'd2, 3'b000, (quadbuf ? nbuf+2'd1 : 2'b00), 19'd0}; - -assign vbuf_address = vbuf_write ? vbuf_waddress : vbuf_raddress; -assign vbuf_burstcount = vbuf_write ? vbuf_wburstcount : vbuf_rburstcount; - -wire [95:0] hf_out; -wire [7:0] hf_usedw; -reg hf_reset = 0; - -vbuf_fifo out_fifo -( - .aclr(hf_reset), - - .wrclk(clk_vbuf), - .wrreq(vbuf_readdatavalid), - .data({vbuf_readdata[96+:24],vbuf_readdata[64+:24],vbuf_readdata[32+:24],vbuf_readdata[0+:24]}), - .wrusedw(hf_usedw), - - .rdclk(~clk_hdmi), - .rdreq(hf_rdreq), - .q(hf_out) -); - -reg [11:0] rd_stride; -wire [7:0] rd_burst = (burstsz < rd_stride) ? burstsz : rd_stride[7:0]; - -reg [27:0] vbuf_raddress; -reg [7:0] vbuf_rburstcount; -always @(posedge clk_vbuf) begin - reg [18:0] rdcnt; - reg [7:0] bcnt; - reg vde1, vde2; - reg [1:0] mcnt; - reg [1:0] my; - reg [18:0] fsz; - reg [11:0] strd; - - vde1 <= hdmi_vde; - vde2 <= vde1; - - if(vbuf_readdatavalid) begin - rdcnt <= rdcnt + 1'd1; - if(bcnt) bcnt <= bcnt - 1'd1; - vbuf_raddress <= vbuf_raddress + 1'd1; - end - - if(!bcnt && reading) reading <= 0; - - vbuf_read <= 0; - if(~vbuf_waitrequest) begin - if(!hf_reset && rdcnt=off_x) && (x<(vh_width+off_x)) && (y>=off_y) && (y<(vh_height+off_y)) && !hload && !pcnt; -wire de_in = hdmi_hde & hdmi_vde; - -always @(posedge clk_hdmi) begin - reg [71:0] px_out; - reg [1:0] mx; - reg vde; - - vde <= hdmi_vde; - - if(vde & ~hdmi_vde) begin - off_x <= (screen_w>v_width) ? (screen_w - v_width)>>1 : 12'd0; - off_y <= (screen_h>v_height) ? (screen_h - v_height)>>1 : 12'd0; - vh_height <= v_height; - vh_width <= v_width; - mx <= mult_x; - end - - pcnt <= pcnt + 1'd1; - if(pcnt == mx) begin - pcnt <= 0; - hload <= hload + 1'd1; - end - - if(~de_in || x (screen_h/2)) ? 2'b00 : (video_y > (screen_h/3)) ? 2'b01 : (video_y > (screen_h/4)) ? 2'b10 : 2'b11; -wire [1:0] tm_x = (l1_width > (screen_w/2)) ? 2'b00 : (l1_width > (screen_w/3)) ? 2'b01 : (l1_width > (screen_w/4)) ? 2'b10 : 2'b11; -wire [1:0] tm_xy = (tm_x < tm_y) ? tm_x : tm_y; -wire [1:0] tmf_y = scale_auto ? tm_xy : scale_y; -wire [1:0] tmf_x = scale_auto ? tm_xy : scale_x; -wire [11:0] t_height = video_y + (tmf_y[0] ? video_y : 12'd0) + (tmf_y[1] ? video_y<<1 : 12'd0); -wire [11:0] t_width = l1_width + (tmf_x[0] ? l1_width : 12'd0) + (tmf_x[1] ? l1_width<<1 : 12'd0); -wire [23:0] t_fsz = l1_stride * t_height; - -reg [11:0] l1_width; -reg [11:0] l1_stride; -always @(posedge clk_video) begin - reg [7:0] loaded = 0; - reg [11:0] strd = 0; - reg old_de = 0; - reg old_vs = 0; - - old_vs <= video_vs; - if(~old_vs & video_vs) begin - cur_addr<= write_buf; - video_x <= 0; - video_y <= 0; - loaded <= 0; - strd <= 0; - nbuf <= nbuf + 1'd1; - - stride <= l1_stride; - framesz <= t_fsz[18:0]; - v_height<= t_height; - v_width <= t_width; - mult_x <= tmf_x; - mult_y <= tmf_y; - end - - if(pix_wr) begin - case(video_x[1:0]) - 0: pix_acc <= video_d; // zeroes upper bits too - 1: pix_acc[47:24] <= video_d; - 2: pix_acc[71:48] <= video_d; - 3: loaded <= loaded + 1'd1; - endcase - if(video_x= burstsz) || (old_de & ~video_de)) begin - if(loaded + infifo_tail) begin - flush_size <= loaded + infifo_tail; - flush_addr <= cur_addr; - flush_req <= ~flush_req; - loaded <= 0; - strd <= strd + loaded; - end - - cur_addr <= cur_addr + loaded + infifo_tail; - if(~video_de) begin - if(video_y= rnd_reg) ? {cos_g - rnd_reg, 2'b00} : 8'd0; reg [9:0] vvc = 0; -always @(negedge clk_in) begin - reg div; - reg [Y_BITS-1:0] x1; - reg [X_BITS-1:0] y1; - - div <= ~div; - - if(!div) begin - x1 <= x; - y1 <= y; - if(pattern[0]) begin - bar <= ~den_out ? 1'b0 : {y1,3'b000}/total_active_lines; - ramp <= {x1,8'h00}/total_active_pix; - end else begin - bar <= ~den_out ? 1'b0 : {x1,3'b000}/total_active_pix; - ramp <= ~({y1,8'h00}/total_active_lines); - end - end - - cosx <= vvc + ({y,10'd0}/total_active_lines); -end +always @(posedge clk_in) cosx <= vvc + ({y,10'd0}/height); always @(posedge clk_in) begin - if(!x && !y && dn_in) vvc <= vvc + 9'd6; + reg [X_BITS-1:0] acc_x,step_x,add_x; + reg [Y_BITS-1:0] acc_y,step_y,add_y; + reg old_hs; + + if(vs_in) begin + add_x <= pattern[1] ? 10'd14 : 10'd255; + add_y <= pattern[1] ? 10'd255 : 10'd14; + end + + ramp_x <= step_x; + ramp_y <= step_y; + + acc_x = acc_x + add_x; + if(acc_x >= width) begin + acc_x = acc_x - width; + step_x <= step_x + 1'd1; + end + + if(!x) begin + acc_x = 0; + step_x <= 0; + ramp_x <= 0; + end + + old_hs <= hs_in; + if(old_hs & ~hs_in) begin + acc_y = acc_y + add_y; + if(acc_y >= height) begin + acc_y = acc_y - height; + step_y <= step_y + 1'd1; + end + + if(!y) begin + acc_y = 0; + step_y <= 0; + ramp_y <= 0; + end + end +end + +wire [X_BITS-1:0] inv_ramp_x = 8'd13 - ramp_x; +wire [Y_BITS-1:0] inv_ramp_y = 8'd13 - ramp_y; + +always @(posedge clk_in) begin + if(!x && !y && de_in) vvc <= vvc + 9'd6; if(!x) cos_g <= {1'b1, cos_out[7:3]}; if(x[1:0] == 0) rnd_reg <= rnd_c; - vn_out <= vn_in; - hn_out <= hn_in; - den_out <= dn_in; + vs_out <= vs_in; + hs_out <= hs_in; + de_out <= de_in; case(pattern) // TV noise 0: if(&x[1:0]) begin - r_out <= noise; - g_out <= noise; - b_out <= noise; + r <= noise; + g <= noise; + b <= noise; end // black 1: begin - r_out <= 0; - g_out <= 0; - b_out <= 0; + r <= 0; + g <= 0; + b <= 0; end // border - 2: if (dn_in && ((y == 12'b0) || (x == 12'b0) || (x == total_active_pix - 1) || (y == total_active_lines - 1))) + 2: if (de_in && ((y == 12'b0) || (x == 12'b0) || (x == width - 1) || (y == height - 1))) begin - r_out <= 8'hFF; - g_out <= 8'hFF; - b_out <= 8'hFF; + r <= 8'hFF; + g <= 8'hFF; + b <= 8'hFF; end else - if (dn_in && ((y == 12'b0+20) || (x == 12'b0+20) || (x == total_active_pix - 1 - 20) || (y == total_active_lines - 1 - 20))) + if (de_in && ((y == 12'b0+20) || (x == 12'b0+20) || (x == width - 1 - 20) || (y == height - 1 - 20))) begin - r_out <= 8'h80; - g_out <= 8'h80; - b_out <= 8'h80; + r <= 8'h80; + g <= 8'h80; + b <= 8'h80; end else begin - r_out <= 0; - g_out <= 0; - b_out <= 0; + r <= 0; + g <= 0; + b <= 0; end // stripes - 3: if ((dn_in) && y[2]) + 3: if ((de_in) && y[2]) begin - r_out <= 8'h80; - g_out <= 8'h80; - b_out <= 8'h80; + r <= 8'h80; + g <= 8'h80; + b <= 8'h80; end else begin - r_out <= 8'hC0; - g_out <= 8'hC0; - b_out <= 8'hC0; + r <= 8'hC0; + g <= 8'hC0; + b <= 8'hC0; end - // Simple RAMPs - 4,5: begin - r_out <= (bar[0]) ? ramp[7:0] : 8'h00; - g_out <= (bar[1]) ? ramp[7:0] : 8'h00; - b_out <= (bar[2]) ? ramp[7:0] : 8'h00; + 4: begin + if(~ramp_y[0]) begin + r <= ramp_y[1] ? 8'h00 : ramp_x[7:0]; + g <= ramp_y[2] ? 8'h00 : ramp_x[7:0]; + b <= ramp_y[3] ? 8'h00 : ramp_x[7:0]; + end + else begin + r <= inv_ramp_y[1] ? 8'h00 : ~ramp_x[7:0]; + g <= inv_ramp_y[2] ? 8'h00 : ~ramp_x[7:0]; + b <= inv_ramp_y[3] ? 8'h00 : ~ramp_x[7:0]; + end end + 5: begin + r <= ramp_y[1] ? 8'h00 : ~ramp_x[7:0]; + g <= ramp_y[2] ? 8'h00 : ~ramp_x[7:0]; + b <= ramp_y[3] ? 8'h00 : ~ramp_x[7:0]; + end + + 6: begin + if(~ramp_x[0]) begin + r <= ramp_x[1] ? 8'h00 : ramp_y[7:0]; + g <= ramp_x[2] ? 8'h00 : ramp_y[7:0]; + b <= ramp_x[3] ? 8'h00 : ramp_y[7:0]; + end + else begin + r <= inv_ramp_x[1] ? 8'h00 : ~ramp_y[7:0]; + g <= inv_ramp_x[2] ? 8'h00 : ~ramp_y[7:0]; + b <= inv_ramp_x[3] ? 8'h00 : ~ramp_y[7:0]; + end + end + + 7: begin + r <= ramp_x[1] ? 8'h00 : ~ramp_y[7:0]; + g <= ramp_x[2] ? 8'h00 : ~ramp_y[7:0]; + b <= ramp_x[3] ? 8'h00 : ~ramp_y[7:0]; + end endcase end diff --git a/sys/reset_source.v b/sys/reset_source.v deleted file mode 100644 index 1b81394..0000000 --- a/sys/reset_source.v +++ /dev/null @@ -1,50 +0,0 @@ -// reset_source.v - -// This file was auto-generated as a prototype implementation of a module -// created in component editor. It ties off all outputs to ground and -// ignores all inputs. It needs to be edited to make it do something -// useful. -// -// This file will not be automatically regenerated. You should check it in -// to your version control system if you want to keep it. - -`timescale 1 ps / 1 ps -module reset_source -( - input wire clk, // clock.clk - input wire reset_hps, // reset_hps.reset - output wire reset_sys, // reset_sys.reset - output wire reset_cold, // reset_cold.reset - input wire cold_req, // reset_ctl.cold_req - output wire reset, // .reset - input wire reset_req, // .reset_req - input wire reset_vip, // .reset_vip - input wire warm_req, // .warm_req - output wire reset_warm // reset_warm.reset -); - -assign reset_cold = cold_req; -assign reset_warm = warm_req; - -wire reset_m = sys_reset | reset_hps | reset_req; -assign reset = reset_m; -assign reset_sys = reset_m | reset_vip; - -reg sys_reset = 1; -always @(posedge clk) begin - integer timeout = 0; - reg reset_lock = 0; - - reset_lock <= reset_lock | cold_req; - - if(timeout < 2000000) begin - sys_reset <= 1; - timeout <= timeout + 1; - reset_lock <= 0; - end - else begin - sys_reset <= reset_lock; - end -end - -endmodule diff --git a/sys/scandoubler.v b/sys/scandoubler.v index 46274f5..9997cf6 100644 --- a/sys/scandoubler.v +++ b/sys/scandoubler.v @@ -2,7 +2,7 @@ // scandoubler.v // // Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig +// Copyright (c) 2017-2019 Sorgelig // // This source file is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published @@ -56,42 +56,51 @@ assign vs_out = vso[3]; assign ce_pix_out = hq2x ? ce_x4 : ce_x2; //Compensate picture shift after HQ2x -assign vb_out = vbo[2]; +assign vb_out = vbo[3]; assign hb_out = hbo[6]; reg [7:0] pix_len = 0; +reg [7:0] pix_cnt = 0; wire [7:0] pl = pix_len + 1'b1; +wire [7:0] pc = pix_cnt + 1'b1; -reg ce_x1, ce_x4, ce_x2; +reg ce_x4, ce_x2, ce_x1; always @(negedge clk_sys) begin - reg old_ce; + reg old_ce, valid, hs; reg [2:0] ce_cnt; - reg [7:0] pixsz2, pixsz4 = 0; + reg [7:0] pixsz, pixsz2, pixsz4 = 0; - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; + if(~&pix_len) pix_len <= pl; + if(~&pix_cnt) pix_cnt <= pc; ce_x4 <= 0; ce_x2 <= 0; ce_x1 <= 0; - // use such odd comparison to place ce_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - ce_x4 <= 1; - end - - if(pl == pixsz2) begin - ce_x2 <= 1; - end + // use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4. + if((pc == pixsz4) || (pc == pixsz2) || (pc == (pixsz2+pixsz4))) ce_x4 <= 1; + if( pc == pixsz2) ce_x2 <= 1; + old_ce <= ce_pix; if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; + if(valid & ~hb_in & ~vb_in) begin + pixsz <= pl; + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + end + pix_len <= 0; + valid <= 1; + end + + if(hb_in | vb_in) valid <= 0; + + hs <= hs_out; + if((~hs & hs_out) || (pc >= pixsz)) begin ce_x2 <= 1; ce_x4 <= 1; - pix_len <= 0; + ce_x1 <= 1; + pix_cnt <= 0; end end @@ -102,88 +111,85 @@ Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x .inputpixel({b_d,g_d,r_d}), .mono(mono), .disable_hq2x(~hq2x), - .reset_frame(vs_in), + .reset_frame(vb_in), .reset_line(req_line_reset), .read_y(sd_line), - .hblank(hbo[0]&hbo[4]), + .hblank(hbo[0]&hbo[8]), .outpixel({b_out,g_out,r_out}) ); -reg [1:0] sd_line; -reg [2:0] vbo; -reg [6:0] hbo; - reg [DWIDTH:0] r_d; reg [DWIDTH:0] g_d; reg [DWIDTH:0] b_d; +reg [1:0] sd_line; +reg [3:0] vbo; reg [3:0] vso; +reg [8:0] hbo; reg req_line_reset; always @(posedge clk_sys) begin - reg [11:0] hs_max,hs_rise; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - reg [11:0] hde_start, hde_end; + reg [31:0] hcnt; + reg [30:0] sd_hcnt; + reg [30:0] hs_start, hs_end; + reg [30:0] hde_start, hde_end; - reg hs, hs2, vs, hb; + reg hs, hb; + + if(ce_x4) begin + hbo[8:1] <= hbo[7:0]; + end + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + if(sd_hcnt == hde_start) begin + sd_hcnt <= 0; + vbo[3:1] <= vbo[2:0]; + end + + if(sd_hcnt == hs_end) begin + sd_line <= sd_line + 1'd1; + if(&vbo[3:2]) sd_line <= 1; + vso[3:1] <= vso[2:0]; + end + + if(sd_hcnt == hde_start)hbo[0] <= 0; + if(sd_hcnt == hde_end) hbo[0] <= 1; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_end) hs_out <= 0; + if(sd_hcnt == hs_start) hs_out <= 1; + + hs <= hs_in; + hb <= hb_in; if(ce_x1) begin - hs <= hs_in; - hb <= hb_in; - req_line_reset <= hb_in; - r_d <= r_in; g_d <= g_in; b_d <= b_in; - - if(hb && !hb_in) begin - hde_start <= {hcnt,1'b0}; - vbo <= {vbo[1:0], vb_in}; - end - if(!hb && hb_in) hde_end <= {hcnt,1'b0}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - vso <= (vso<<1) | vs_in; - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; end - if(ce_x4) begin - hs2 <= hs_in; - hbo[6:1] <= hbo[5:0]; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - - //prepare to read in advance - if(sd_hcnt == (hde_start-2)) begin - sd_line <= sd_line + 1'd1; - end - - if(sd_hcnt == hde_start) hbo[0] <= 0; - if(sd_hcnt == hde_end) hbo[0] <= 1; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; + hcnt <= hcnt + 1'd1; + if(hb && !hb_in) begin + hde_start <= hcnt[31:1]; + hbo[0] <= 0; + hcnt <= 0; + sd_hcnt <= 0; + vbo <= {vbo[2:0],vb_in}; end + + if(!hb && hb_in) hde_end <= hcnt[31:1]; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_end <= hcnt[31:1]; + vso[0] <= vs_in; + end + + // save position of rising edge + if(!hs && hs_in) hs_start <= hcnt[31:1]; end endmodule diff --git a/sys/spdif.v b/sys/spdif.v index 671dcb2..add51d3 100644 --- a/sys/spdif.v +++ b/sys/spdif.v @@ -63,34 +63,27 @@ module spdif ); reg lpf_ce; -always @(negedge clk_i) begin - reg [3:0] div; - - div <= div + 1'd1; - if(div == 13) div <= 0; +always @(posedge clk_i) begin + reg [2:0] div; + if(bit_clk_q) div <= div + 1'd1; lpf_ce <= !div; end wire [15:0] al, ar; -lpf48k #(15) lpf_l +lpf_spdif lpf_l ( - .RESET(rst_i), .CLK(clk_i), .CE(lpf_ce), - .ENABLE(1), - .IDATA(audio_l), .ODATA(al) ); -lpf48k #(15) lpf_r +lpf_spdif lpf_r ( - .RESET(rst_i), .CLK(clk_i), .CE(lpf_ce), - .ENABLE(1), .IDATA(audio_r), .ODATA(ar) @@ -424,3 +417,29 @@ else assign spdif_o = spdif_out_q; endmodule + +module lpf_spdif +( + input CLK, + input CE, + input [15:0] IDATA, + output reg [15:0] ODATA +); + +reg [511:0] acc; +reg [20:0] sum; + +always @(*) begin + integer i; + sum = 0; + for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]}; +end + +always @(posedge CLK) begin + if(CE) begin + acc <= {acc[495:0], IDATA}; + ODATA <= sum[20:5]; + end +end + +endmodule diff --git a/sys/sys.qip b/sys/sys.qip index 9034beb..9ba5d56 100644 --- a/sys/sys.qip +++ b/sys/sys.qip @@ -17,10 +17,8 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) a set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) spdif.v ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ] -set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) lpf48k.sv ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ] set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ] -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) reset_source.v ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ] set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc index f48d369..7dfcc51 100644 --- a/sys/sys_top.sdc +++ b/sys/sys_top.sdc @@ -14,17 +14,13 @@ create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|alt create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \ -name HDMI_CLK [get_ports HDMI_TX_CLK] + derive_clock_uncertainty - # Set acceptable delays for SDRAM chip (See correspondent chip datasheet) set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]] set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]] -set_multicycle_path -from [get_clocks {SDRAM_CLK}] \ - -to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \ - -setup 2 - set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] # Decouple different clock groups (to simplify routing) diff --git a/sys/sys_top.v b/sys/sys_top.v index 85bbaef..23de6f2 100644 --- a/sys/sys_top.v +++ b/sys/sys_top.v @@ -90,7 +90,10 @@ module sys_top input [3:0] SW, ////////// MB LED /////////// - output [7:0] LED + output [7:0] LED, + + ///////// USER IO /////////// + inout [5:0] USER_IO ); @@ -342,19 +345,19 @@ sync_vg #(.X_BITS(12), .Y_BITS(12)) sync_vg .h_sync(HS), .vde_out(vde), .hde_out(hde), - .vs_out(vs_hdmi), + .vs_out(hdmi_vs), .x_out(x), .y_out(y), - .hs_out(hs_hdmi) + .hs_out(hdmi_hs) ); wire vde, hde; -wire vs_hdmi; -wire hs_hdmi; +wire hdmi_vs,hdmi_vs2; +wire hdmi_hs,hdmi_hs2; pattern_vg #( - .B(8), // Bits per channel + .B(8), .X_BITS(12), .Y_BITS(12) ) @@ -364,17 +367,17 @@ pattern_vg .clk_in(clk_hdmi), .x(x), .y(y), - .vn_in(vs_hdmi), - .hn_in(hs_hdmi), - .dn_in(vde & hde), - .vn_out(HDMI_TX_VS), - .hn_out(HDMI_TX_HS), - .den_out(hdmi_de), - .r_out(hdmi_data[23:16]), - .g_out(hdmi_data[15:8]), - .b_out(hdmi_data[7:0]), - .total_active_pix(WIDTH), - .total_active_lines(HEIGHT), + .vs_in(hdmi_vs), + .hs_in(hdmi_hs), + .de_in(vde & hde), + .vs_out(hdmi_vs2), + .hs_out(hdmi_hs2), + .de_out(hdmi_de), + .r(hdmi_data[23:16]), + .g(hdmi_data[15:8]), + .b(hdmi_data[7:0]), + .width(WIDTH), + .height(HEIGHT), .pattern(patt) ); @@ -382,15 +385,14 @@ wire reset; sysmem_lite sysmem ( //Reset/Clock - .reset_reset_req(reset_req), - .reset_reset(reset), - .ctl_clock(clk_100m), + .reset_core_req(reset_req), + .reset_out(reset), + .clock(clk_100m), - .reset_cold_req(~btn_reset), - .reset_warm_req(0), + .reset_hps_cold_req(~btn_reset), //64-bit DDR3 RAM access - .ramclk1_clk(ram_clk), + .ram1_clk(ram_clk), .ram1_address(ram_address), .ram1_burstcount(ram_burstcount), .ram1_waitrequest(ram_waitrequest), @@ -402,7 +404,7 @@ sysmem_lite sysmem .ram1_write(ram_write), //64-bit DDR3 RAM access - .ramclk2_clk(clk_audio), + .ram2_clk(clk_audio), .ram2_address(aram_address), .ram2_burstcount(aram_burstcount), .ram2_waitrequest(aram_waitrequest), @@ -512,8 +514,8 @@ hdmi_config hdmi_config .audio_96k(audio_96k) ); -wire [23:0] hdmi_data; -wire hdmi_de; +wire [23:0] hdmi_data,hdmi_data2; +wire hdmi_de,hdmi_de2; osd hdmi_osd ( @@ -525,31 +527,38 @@ osd hdmi_osd .clk_video(clk_hdmi), .din(hdmi_data), - .dout(HDMI_TX_D), + .dout(hdmi_data2), .de_in(hdmi_de), - .de_out(HDMI_TX_DE) + .de_out(hdmi_de2) ); -assign HDMI_MCLK = 0; -i2s i2s + +vid_dim hdmi_dim ( - .reset(~cfg_ready), - .clk_sys(clk_audio), - .half_rate(~audio_96k), + .clk(clk_hdmi), - .sclk(HDMI_SCLK), - .lrclk(HDMI_LRCLK), - .sdata(HDMI_I2S), + .r_in(hdmi_data2[23:16]), + .g_in(hdmi_data2[15:8]), + .b_in(hdmi_data2[7:0]), + .de_in(hdmi_de2), + .hs_in(hdmi_hs2), + .vs_in(hdmi_vs2), - //Could inverse the MSB but it will shift 0 level to -MAX level - .left_chan (audio_l), - .right_chan(audio_r) + .r_out(HDMI_TX_D[23:16]), + .g_out(HDMI_TX_D[15:8]), + .b_out(HDMI_TX_D[7:0]), + .de_out(HDMI_TX_DE), + .hs_out(HDMI_TX_HS), + .vs_out(HDMI_TX_VS), + + .dim(dim) ); ///////////////////////// VGA output ////////////////////////////////// -wire [23:0] vga_q; +wire [23:0] vga_q, vga_q2; +wire hs2,vs2; osd vga_osd ( .clk_sys(clk_sys), @@ -564,18 +573,36 @@ osd vga_osd .de_in(de) ); -wire [23:0] vga_o; +vid_dim vga_dim +( + .clk(clk_vid), + .r_in(vga_q[23:16]), + .g_in(vga_q[15:8]), + .b_in(vga_q[7:0]), + .hs_in(hs), + .vs_in(vs), + + .r_out(vga_q2[23:16]), + .g_out(vga_q2[15:8]), + .b_out(vga_q2[7:0]), + .hs_out(hs2), + .vs_out(vs2), + + .dim(dim) +); + +wire [23:0] vga_o; vga_out vga_out ( .ypbpr_full(1), .ypbpr_en(ypbpr_en), .dout(vga_o), - .din(vga_scaler ? {24{HDMI_TX_DE}} & HDMI_TX_D : vga_q) + .din(vga_scaler ? (HDMI_TX_DE ? HDMI_TX_D : 24'd0) : vga_q2) ); -wire vs1 = vga_scaler ? HDMI_TX_VS : vs; -wire hs1 = vga_scaler ? HDMI_TX_HS : hs; +wire vs1 = vga_scaler ? HDMI_TX_VS : vs2; +wire hs1 = vga_scaler ? HDMI_TX_HS : hs2; assign VGA_VS = VGA_EN ? 1'bZ : csync ? 1'b1 : ~vs1; assign VGA_HS = VGA_EN ? 1'bZ : csync ? ~(vs1 ^ hs1) : ~hs1; @@ -586,7 +613,27 @@ assign VGA_B = VGA_EN ? 6'bZZZZZZ : vga_o[7:2]; ///////////////////////// Audio output //////////////////////////////// -wire anl, anr, aspdif; +assign AUDIO_SPDIF = SW[0] ? HDMI_LRCLK : aspdif; +assign AUDIO_R = SW[0] ? HDMI_I2S : anr; +assign AUDIO_L = SW[0] ? HDMI_SCLK : anl; + +assign HDMI_MCLK = 0; +i2s i2s +( + .clk_sys(clk_audio), + .reset(reset), + + .half_rate(~audio_96k), + + .sclk(HDMI_SCLK), + .lrclk(HDMI_LRCLK), + .sdata(HDMI_I2S), + + .left_chan (audio_l), + .right_chan(audio_r) +); + +wire anl; sigma_delta_dac #(15) dac_l ( @@ -596,6 +643,7 @@ sigma_delta_dac #(15) dac_l .DACout(anl) ); +wire anr; sigma_delta_dac #(15) dac_r ( .CLK(clk_audio), @@ -604,6 +652,7 @@ sigma_delta_dac #(15) dac_r .DACout(anr) ); +wire aspdif; spdif toslink ( .clk_i(clk_audio), @@ -617,50 +666,37 @@ spdif toslink .spdif_o(aspdif) ); -assign AUDIO_SPDIF = SW[0] ? HDMI_LRCLK : aspdif; -assign AUDIO_R = SW[0] ? HDMI_I2S : anr; -assign AUDIO_L = SW[0] ? HDMI_SCLK : anl; +wire [15:0] audio_l, audio_l_pre; +aud_mix_top audmix_l +( + .clk(clk_audio), + .att(vol_att), + .mix(audio_mix), + .is_signed(audio_s), -reg signed [15:0] audio_l; -reg signed [15:0] audio_r; + .core_audio(audio_ls), + .pre_in(audio_r_pre), + .linux_audio(alsa_l), -always @(posedge clk_audio) begin - reg signed [16:0] als, al, acl, apl; - reg signed [16:0] ars, ar, acr, apr; + .pre_out(audio_l_pre), + .out(audio_l) +); - {acl,acr} <= audio_s ? {audio_ls[15],audio_ls,audio_rs[15],audio_rs}: - {2'b00,audio_ls[15:1], 2'b00,audio_rs[15:1]}; +wire [15:0] audio_r, audio_r_pre; +aud_mix_top audmix_r +( + .clk(clk_audio), + .att(vol_att), + .mix(audio_mix), + .is_signed(audio_s), - als <= acl + {alsa_l[15],alsa_l}; - ars <= acr + {alsa_r[15],alsa_r}; + .core_audio(audio_rs), + .pre_in(audio_l_pre), + .linux_audio(alsa_r), - case(audio_mix) - 0: al <= als; - 1: al <= als - (als >>> 3) + (ars >>> 3); - 2: al <= als - (als >>> 2) + (ars >>> 2); - 3: al <= (als >>> 1) + (ars >>> 1); - endcase - - case(audio_mix) - 0: ar <= ars; - 1: ar <= ars - (ars >>> 3) + (als >>> 3); - 2: ar <= ars - (ars >>> 2) + (als >>> 2); - 3: ar <= (ars >>> 1) + (als >>> 1); - endcase - - if(vol_att[4]) begin - apl <= 0; - apr <= 0; - end - else - begin - apl <= al >>> vol_att[3:0]; - apr <= ar >>> vol_att[3:0]; - end - - audio_l <= ($signed(apl) > $signed(17'd32767)) ? 16'd32767 : ($signed(apl) < $signed(-17'd32768)) ? -16'd32768 : apl[15:0]; - audio_r <= ($signed(apr) > $signed(17'd32767)) ? 16'd32767 : ($signed(apr) < $signed(-17'd32768)) ? -16'd32768 : apr[15:0]; -end + .pre_out(audio_r_pre), + .out(audio_r) +); wire [28:0] aram_address; wire [7:0] aram_burstcount; @@ -669,7 +705,7 @@ wire [63:0] aram_readdata; wire aram_readdatavalid; wire aram_read; -wire signed [15:0] alsa_l, alsa_r; +wire [15:0] alsa_l, alsa_r; alsa alsa ( @@ -691,6 +727,17 @@ alsa alsa .pcm_r(alsa_r) ); + +//////////////// User I/O (USB 3.0 connector) ///////////////////////// + +assign USER_IO[0] = 1'bZ; +assign USER_IO[1] = 1'bZ; +assign USER_IO[2] = (SW[1] & ~HDMI_I2S) ? 1'b0 : 1'bZ; +assign USER_IO[3] = 1'bZ; +assign USER_IO[4] = (SW[1] & ~HDMI_SCLK) ? 1'b0 : 1'bZ; +assign USER_IO[5] = (SW[1] & ~HDMI_LRCLK) ? 1'b0 : 1'bZ; + + /////////////////// User module connection //////////////////////////// wire [15:0] audio_ls, audio_rs; @@ -700,6 +747,7 @@ wire [7:0] r_out, g_out, b_out; wire vs, hs, de; wire clk_sys, clk_vid, ce_pix; wire [2:0] patt; +wire dim; wire reset_hdmi; wire ram_clk; @@ -728,6 +776,7 @@ wire uart_rts; wire uart_rxd; wire uart_txd; + emu emu ( .CLK_50M(FPGA_CLK3_50), @@ -751,6 +800,7 @@ emu emu .LED_DISK(led_disk), .PATTERN(patt), + .DIM(dim), .AUDIO_L(audio_ls), .AUDIO_R(audio_rs), @@ -796,6 +846,8 @@ emu emu ); endmodule + +///////////////////////////////////////////////////////////////////// module sync_fix ( @@ -822,6 +874,101 @@ always @(posedge clk) begin if(s2 != s1) cnt <= 0; pol <= pos > neg; +end + +endmodule + +///////////////////////////////////////////////////////////////////// + +module aud_mix_top +( + input clk, + + input [4:0] att, + input [1:0] mix, + input is_signed, + + input [15:0] core_audio, + input [15:0] linux_audio, + input [15:0] pre_in, + + output reg [15:0] pre_out, + output reg [15:0] out +); + +reg [15:0] ca; +always @(posedge clk) begin + reg [15:0] d1,d2,d3; + + d1 <= core_audio; d2<=d1; d3<=d2; + if(d2 == d3) ca <= d2; +end + +always @(posedge clk) begin + reg signed [16:0] a1, a2, a3, a4; + + a1 <= is_signed ? {ca[15],ca} : {2'b00,ca[15:1]}; + a2 <= a1 + {linux_audio[15],linux_audio}; + + pre_out <= a2[16:1]; + + case(mix) + 0: a3 <= a2; + 1: a3 <= $signed(a2) - $signed(a2[16:3]) + $signed(pre_in[15:2]); + 2: a3 <= $signed(a2) - $signed(a2[16:2]) + $signed(pre_in[15:1]); + 3: a3 <= {a2[16],a2[16:1]} + {pre_in[15],pre_in}; + endcase + + if(att[4]) a4 <= 0; + else a4 <= a3 >>> att[3:0]; + + //clamping + out <= ^a4[16:15] ? {a4[16],{15{a4[15]}}} : a4[15:0]; +end + +endmodule + +///////////////////////////////////////////////////////////////////// + +module vid_dim +( + input clk, + + input [7:0] r_in,g_in,b_in, + input de_in, + input hs_in, + input vs_in, + + output reg [7:0] r_out,g_out,b_out, + output reg de_out, + output reg hs_out, + output reg vs_out, + + input dim +); + +always @(posedge clk) begin + reg hs_in1,vs_in1; + + //compensate osd + hs_in1 <= hs_in; + vs_in1 <= vs_in; + + hs_out <= hs_in1; + vs_out <= vs_in1; + + de_out <= de_in; + + if(dim) begin + r_out <= r_in[7:2]; + g_out <= g_in[7:2]; + b_out <= b_in[7:2]; + end + else begin + r_out <= r_in; + g_out <= g_in; + b_out <= b_in; + end end endmodule diff --git a/sys/sysmem.sv b/sys/sysmem.sv index fe844cf..c90395e 100644 --- a/sys/sysmem.sv +++ b/sys/sysmem.sv @@ -1,105 +1,102 @@ `timescale 1 ps / 1 ps module sysmem_lite ( - input ramclk1_clk, // ramclk1.clk - input [28:0] ram1_address, // ram1.address - input [7:0] ram1_burstcount, // .burstcount - output ram1_waitrequest, // .waitrequest - output [63:0] ram1_readdata, // .readdata - output ram1_readdatavalid, // .readdatavalid - input ram1_read, // .read - input [63:0] ram1_writedata, // .writedata - input [7:0] ram1_byteenable, // .byteenable - input ram1_write, // .write + output clock, + output reset_out, - input ramclk2_clk, // ramclk2.clk - input [28:0] ram2_address, // ram2.address - input [7:0] ram2_burstcount, // .burstcount - output ram2_waitrequest, // .waitrequest - output [63:0] ram2_readdata, // .readdata - output ram2_readdatavalid, // .readdatavalid - input ram2_read, // .read - input [63:0] ram2_writedata, // .writedata - input [7:0] ram2_byteenable, // .byteenable - input ram2_write, // .write + input reset_hps_cold_req, + input reset_hps_warm_req, + input reset_core_req, - output ctl_clock, - input reset_cold_req, // reset.cold_req - output reset_reset, // .reset - input reset_reset_req, // .reset_req - input reset_warm_req, // .warm_req + input ram1_clk, + input [28:0] ram1_address, + input [7:0] ram1_burstcount, + output ram1_waitrequest, + output [63:0] ram1_readdata, + output ram1_readdatavalid, + input ram1_read, + input [63:0] ram1_writedata, + input [7:0] ram1_byteenable, + input ram1_write, - input vbuf_clk, // vbuf.clk - input [27:0] vbuf_address, // vbuf.address - input [7:0] vbuf_burstcount, // .burstcount - output vbuf_waitrequest, // .waitrequest - output [127:0] vbuf_readdata, // .readdata - output vbuf_readdatavalid, // .readdatavalid - input vbuf_read, // .read - input [127:0] vbuf_writedata, // .writedata - input [15:0] vbuf_byteenable, // .byteenable - input vbuf_write // .write + input ram2_clk, + input [28:0] ram2_address, + input [7:0] ram2_burstcount, + output ram2_waitrequest, + output [63:0] ram2_readdata, + output ram2_readdatavalid, + input ram2_read, + input [63:0] ram2_writedata, + input [7:0] ram2_byteenable, + input ram2_write, + + input vbuf_clk, + input [27:0] vbuf_address, + input [7:0] vbuf_burstcount, + output vbuf_waitrequest, + output [127:0] vbuf_readdata, + output vbuf_readdatavalid, + input vbuf_read, + input [127:0] vbuf_writedata, + input [15:0] vbuf_byteenable, + input vbuf_write ); -assign ctl_clock = clk_vip_clk; - -wire hps_h2f_reset_reset; // HPS:h2f_rst_n -> Reset_Source:reset_hps -wire reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n -wire reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n -wire clk_vip_clk; +assign reset_out = ~init_reset_n | ~hps_h2f_reset_n | reset_core_req; sysmem_HPS_fpga_interfaces fpga_interfaces ( - .f2h_cold_rst_req_n (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n - .f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n - .h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk - .h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n - .f2h_sdram0_clk (vbuf_clk), // f2h_sdram0_clock.clk - .f2h_sdram0_ADDRESS (vbuf_address), // f2h_sdram0_data.address - .f2h_sdram0_BURSTCOUNT (vbuf_burstcount), // .burstcount - .f2h_sdram0_WAITREQUEST (vbuf_waitrequest), // .waitrequest - .f2h_sdram0_READDATA (vbuf_readdata), // .readdata - .f2h_sdram0_READDATAVALID (vbuf_readdatavalid), // .readdatavalid - .f2h_sdram0_READ (vbuf_read), // .read - .f2h_sdram0_WRITEDATA (vbuf_writedata), // .writedata - .f2h_sdram0_BYTEENABLE (vbuf_byteenable), // .byteenable - .f2h_sdram0_WRITE (vbuf_write), // .write - .f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk - .f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address - .f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount - .f2h_sdram1_WAITREQUEST (ram1_waitrequest), // .waitrequest - .f2h_sdram1_READDATA (ram1_readdata), // .readdata - .f2h_sdram1_READDATAVALID (ram1_readdatavalid), // .readdatavalid - .f2h_sdram1_READ (ram1_read), // .read - .f2h_sdram1_WRITEDATA (ram1_writedata), // .writedata - .f2h_sdram1_BYTEENABLE (ram1_byteenable), // .byteenable - .f2h_sdram1_WRITE (ram1_write), // .write - .f2h_sdram2_clk (ramclk2_clk), // f2h_sdram2_clock.clk - .f2h_sdram2_ADDRESS (ram2_address), // f2h_sdram2_data.address - .f2h_sdram2_BURSTCOUNT (ram2_burstcount), // .burstcount - .f2h_sdram2_WAITREQUEST (ram2_waitrequest), // .waitrequest - .f2h_sdram2_READDATA (ram2_readdata), // .readdata - .f2h_sdram2_READDATAVALID (ram2_readdatavalid), // .readdatavalid - .f2h_sdram2_READ (ram2_read), // .read - .f2h_sdram2_WRITEDATA (ram2_writedata), // .writedata - .f2h_sdram2_BYTEENABLE (ram2_byteenable), // .byteenable - .f2h_sdram2_WRITE (ram2_write) // .write + .f2h_cold_rst_req_n (~reset_hps_cold_req), + .f2h_warm_rst_req_n (~reset_hps_warm_req), + .h2f_user0_clk (clock), + .h2f_rst_n (hps_h2f_reset_n), + .f2h_sdram0_clk (vbuf_clk), + .f2h_sdram0_ADDRESS (vbuf_address), + .f2h_sdram0_BURSTCOUNT (vbuf_burstcount), + .f2h_sdram0_WAITREQUEST (vbuf_waitrequest), + .f2h_sdram0_READDATA (vbuf_readdata), + .f2h_sdram0_READDATAVALID (vbuf_readdatavalid), + .f2h_sdram0_READ (vbuf_read), + .f2h_sdram0_WRITEDATA (vbuf_writedata), + .f2h_sdram0_BYTEENABLE (vbuf_byteenable), + .f2h_sdram0_WRITE (vbuf_write), + .f2h_sdram1_clk (ram1_clk), + .f2h_sdram1_ADDRESS (ram1_address), + .f2h_sdram1_BURSTCOUNT (ram1_burstcount), + .f2h_sdram1_WAITREQUEST (ram1_waitrequest), + .f2h_sdram1_READDATA (ram1_readdata), + .f2h_sdram1_READDATAVALID (ram1_readdatavalid), + .f2h_sdram1_READ (ram1_read), + .f2h_sdram1_WRITEDATA (ram1_writedata), + .f2h_sdram1_BYTEENABLE (ram1_byteenable), + .f2h_sdram1_WRITE (ram1_write), + .f2h_sdram2_clk (ram2_clk), + .f2h_sdram2_ADDRESS (ram2_address), + .f2h_sdram2_BURSTCOUNT (ram2_burstcount), + .f2h_sdram2_WAITREQUEST (ram2_waitrequest), + .f2h_sdram2_READDATA (ram2_readdata), + .f2h_sdram2_READDATAVALID (ram2_readdatavalid), + .f2h_sdram2_READ (ram2_read), + .f2h_sdram2_WRITEDATA (ram2_writedata), + .f2h_sdram2_BYTEENABLE (ram2_byteenable), + .f2h_sdram2_WRITE (ram2_write) ); -reset_source reset_source ( - .clk (clk_vip_clk), // clock.clk - .reset_hps (~hps_h2f_reset_reset), // reset_hps.reset - .reset_sys (), // reset_sys.reset - .cold_req (reset_cold_req), // reset_ctl.cold_req - .reset (reset_reset), // .reset - .reset_req (reset_reset_req), // .reset_req - .reset_vip (0), // .reset_vip - .warm_req (reset_warm_req), // .warm_req - .reset_warm (reset_source_reset_warm_reset), // reset_warm.reset - .reset_cold (reset_source_reset_cold_reset) // reset_cold.reset -); +wire hps_h2f_reset_n; + +reg init_reset_n = 0; +always @(posedge clock) begin + integer timeout = 0; + + if(timeout < 2000000) begin + init_reset_n <= 0; + timeout <= timeout + 1; + end + else init_reset_n <= 1; +end endmodule + module sysmem_HPS_fpga_interfaces ( // h2f_reset