Fix metastability.

2026-05-24 03:04:13 +00:00 · 2018-03-03 23:38:31 +08:00
parent 314e8fd2b3
commit 76ce03c578
4 changed files with 104 additions and 90 deletions
--- a/menu.qsf
+++ b/menu.qsf
@@ -51,7 +51,7 @@ set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
 set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
 set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
 set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
+set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
 set_global_assignment -name SEED 1

 #============================================================
--- a/sys/pattern_vg.v
+++ b/sys/pattern_vg.v
@@ -10,12 +10,11 @@ module pattern_vg
 	input [X_BITS-1:0] x,
 	input [Y_BITS-1:0] y,
 	input              vn_in, hn_in, dn_in,
-	input      [B-1:0] r_in, g_in, b_in,
 	output reg         vn_out, hn_out, den_out,
 	output reg [B-1:0] r_out, g_out, b_out,
 	input [X_BITS-1:0] total_active_pix,
 	input [Y_BITS-1:0] total_active_lines,
-	input        [7:0] pattern
+	input        [2:0] pattern
 );
 	
 reg [Y_BITS+2:0] bar;
@@ -35,19 +34,29 @@ wire [7:0] noise = (cos_g >= rnd_reg) ? {cos_g - rnd_reg, 2'b00} : 8'd0;

 reg [9:0] vvc = 0;
 always @(negedge clk_in) begin
-	if(pattern == 4) begin
-		bar  <= ~den_out ? 1'b0 : {y,3'b000}/total_active_lines;
-		ramp <= {x,8'h00}/total_active_pix;
-	end else begin
-		bar  <= ~den_out ? 1'b0 : {x,3'b000}/total_active_pix;
-		ramp <= ~({y,8'h00}/total_active_lines);
+	reg div;
+	reg [Y_BITS-1:0] x1;
+	reg [X_BITS-1:0] y1;
+
+	div <= ~div;
+	
+	if(!div) begin
+		x1 <= x;
+		y1 <= y;
+		if(pattern[0]) begin
+			bar <= ~den_out ? 1'b0 : {y1,3'b000}/total_active_lines;
+			ramp <= {x1,8'h00}/total_active_pix;
+		end else begin
+			bar <= ~den_out ? 1'b0 : {x1,3'b000}/total_active_pix;
+			ramp <= ~({y1,8'h00}/total_active_lines);
+		end
 	end

 	cosx <= vvc + ({y,10'd0}/total_active_lines);
 end

 always @(posedge clk_in) begin
-	if(!x && !y) vvc <= vvc + 9'd6;
+	if(!x && !y && dn_in) vvc <= vvc + 9'd6;
 	if(!x) cos_g <= {1'b1, cos_out[7:3]};

 	if(x[1:0] == 0) rnd_reg <= rnd_c;
@@ -55,64 +64,65 @@ always @(posedge clk_in) begin
 	vn_out <= vn_in;
 	hn_out <= hn_in;
 	den_out <= dn_in;
+	
+	case(pattern)
+		// TV noise
+		0: if(&x[1:0]) begin
+				r_out <= noise;
+				g_out <= noise;
+				b_out <= noise;
+			end

-	if (pattern == 0) // TV noise
-	begin
-		if(&x[1:0]) begin
-			r_out <= noise;
-			g_out <= noise;
-			b_out <= noise;
-		end
-	end
-	else if (pattern == 1) // border
-	begin
-		if (dn_in && ((y == 12'b0) || (x == 12'b0) || (x == total_active_pix - 1) || (y == total_active_lines - 1)))
-		begin
-			r_out <= 8'hFF;
-			g_out <= 8'hFF;
-			b_out <= 8'hFF;
-		end
-		else	// Double-border (OzOnE)...
-		if (dn_in && ((y == 12'b0+20) || (x == 12'b0+20) || (x == total_active_pix - 1 - 20) || (y == total_active_lines - 1 - 20)))
-		begin
-			r_out <= 8'h80;
-			g_out <= 8'h80;
-			b_out <= 8'h80;
-		end
-		else
-		begin
-			r_out <= r_in;
-			g_out <= g_in;
-			b_out <= b_in;
-		end
-	end
-	else if (pattern == 2) // stripes
-	begin
-		if ((dn_in) && y[2])
-		begin
-			r_out <= 8'h80;
-			g_out <= 8'h80;
-			b_out <= 8'h80;
-		end
-		else
-		begin
-			r_out <= 8'hC0;
-			g_out <= 8'hC0;
-			b_out <= 8'hC0;
-		end
-	end
-	else if (pattern <= 4) // Simple RAMPs
-	begin
-		r_out <= (bar[0]) ? ramp[7:0] : 8'h00;
-		g_out <= (bar[1]) ? ramp[7:0] : 8'h00;
-		b_out <= (bar[2]) ? ramp[7:0] : 8'h00;
-	end
-	else if(pattern == 5)
-	begin
-		r_out <= r_in;
-		g_out <= g_in;
-		b_out <= b_in;
-	end
+		// black
+		1:	begin
+				r_out <= 0;
+				g_out <= 0;
+				b_out <= 0;
+			end
+
+		// border
+		2: if (dn_in && ((y == 12'b0) || (x == 12'b0) || (x == total_active_pix - 1) || (y == total_active_lines - 1)))
+			begin
+				r_out <= 8'hFF;
+				g_out <= 8'hFF;
+				b_out <= 8'hFF;
+			end
+			else
+			if (dn_in && ((y == 12'b0+20) || (x == 12'b0+20) || (x == total_active_pix - 1 - 20) || (y == total_active_lines - 1 - 20)))
+			begin
+				r_out <= 8'h80;
+				g_out <= 8'h80;
+				b_out <= 8'h80;
+			end
+			else
+			begin
+				r_out <= 0;
+				g_out <= 0;
+				b_out <= 0;
+			end
+
+		// stripes
+		3:	if ((dn_in) && y[2])
+			begin
+				r_out <= 8'h80;
+				g_out <= 8'h80;
+				b_out <= 8'h80;
+			end
+			else
+			begin
+				r_out <= 8'hC0;
+				g_out <= 8'hC0;
+				b_out <= 8'hC0;
+			end
+
+		// Simple RAMPs
+		4,5: begin
+				r_out <= (bar[0]) ? ramp[7:0] : 8'h00;
+				g_out <= (bar[1]) ? ramp[7:0] : 8'h00;
+				b_out <= (bar[2]) ? ramp[7:0] : 8'h00;
+			end
+
+	endcase
 end

 endmodule
--- a/sys/sync_vg.v
+++ b/sys/sync_vg.v
@@ -20,8 +20,6 @@ module sync_vg
 	output reg hs_out,
 	output reg hde_out,
 	output reg vde_out,
-	output reg [Y_BITS-1:0] v_count_out,
-	output reg [X_BITS-1:0] h_count_out,
 	output reg [X_BITS-1:0] x_out,
 	output reg [Y_BITS-1:0] y_out
 );
@@ -52,27 +50,38 @@ always @(posedge clk)
 			v_count <= v_count + 1'd1;
 	end

+reg [X_BITS-1:0] x;
+reg [Y_BITS-1:0] y;
+reg vs;
+reg hs;
+reg hde;
+reg vde;
+
 always @(posedge clk)
-	if (reset)
-		{ vs_out, hs_out, hde_out, vde_out } <= 0;
+	if (reset) { vs, hs, hde, vde } <= 0;
 	else begin
-		hs_out <= ((h_count < h_sync));
+		hs <= ((h_count < h_sync));

-		hde_out <= (h_count >= h_sync + h_bp) && (h_count <= h_total - h_fp - 1);
-		vde_out <= (v_count >= v_sync + v_bp) && (v_count <= v_total - v_fp - 1);
+		if((h_count >= h_sync + h_bp) && (h_count <= h_total - h_fp - 1)) begin
+			x <= h_count - (h_sync + h_bp);
+			hde <= 1;
+		end else begin
+			x <= 0;
+			hde <= 0;
+		end

-		if ((v_count == 0) && (h_count == hv_offset))
-			vs_out <= 1'b1;
-		else if ((v_count == v_sync) && (h_count == hv_offset))
-			vs_out <= 1'b0;
+		if((v_count >= v_sync + v_bp) && (v_count <= v_total - v_fp - 1)) begin
+			y <= v_count - (v_sync + v_bp);
+			vde <= 1;
+		end else begin
+			y <=0;
+			vde <= 0;
+		end

-		/* H_COUNT_OUT and V_COUNT_OUT */
-		h_count_out <= h_count;
-		v_count_out <= v_count;
-
-		/* X and Y coords for a backend pattern generator */
-		x_out <= h_count - (h_sync + h_bp);
-		y_out <= v_count - (v_sync + v_bp);
+		if ((v_count == 0) && (h_count == hv_offset))      vs <= 1'b1;
+		if ((v_count == v_sync) && (h_count == hv_offset)) vs <= 1'b0;
 	end

+always @(posedge clk) {vs_out,hs_out,hde_out,vde_out,x_out,y_out} <= {vs,hs,hde,vde,x,y};
+
 endmodule
--- a/sys/sys_top.v
+++ b/sys/sys_top.v
@@ -402,8 +402,6 @@ sync_vg #(.X_BITS(12), .Y_BITS(12)) sync_vg
 	.vde_out(vde),
 	.hde_out(hde),
 	.vs_out(vs_hdmi),
-	.v_count_out(),
-	.h_count_out(),
 	.x_out(x),
 	.y_out(y),
 	.hs_out(hs_hdmi)
@@ -428,9 +426,6 @@ pattern_vg
 	.vn_in(vs_hdmi),
 	.hn_in(hs_hdmi),
 	.dn_in(vde & hde),
-	.r_in(0),
-	.g_in(0),
-	.b_in(0),
 	.vn_out(HDMI_TX_VS),
 	.hn_out(HDMI_TX_HS),
 	.den_out(hdmi_de),