mirror of
https://github.com/MiSTer-devel/MemTest_MiSTer.git
synced 2026-05-17 03:04:03 +00:00
2ef29982db
* Including more low frequencies - hopefully to help debug issues with N64 on Mister Pi boards * Including even more frequencies (625 is 62.5MHz, the SDRAM clock for N64). Included Excel spreadsheet with frequency calculations * Changing the parameters for 62.5MHz to more closely follow the PLL MegaWizard's recommendation for this frequency * Updating all clock frequencies to match the output of the PLL MegaWizard
561 lines
13 KiB
Systemverilog
561 lines
13 KiB
Systemverilog
//============================================================================
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//
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// Memory testes for MiSTer.
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// Copyright (C) 2017-2019 Sorgelig
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//
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [45:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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output [11:0] VIDEO_ARX,
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output [11:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output VGA_F1,
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output [1:0] VGA_SL,
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output VGA_SCALER, // Force VGA scaler
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`ifdef USE_FB
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// Use framebuffer in DDRAM (USE_FB=1 in qsf)
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// FB_FORMAT:
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// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
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// [3] : 0=16bits 565 1=16bits 1555
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// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
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//
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// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
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output FB_EN,
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output [4:0] FB_FORMAT,
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output [11:0] FB_WIDTH,
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output [11:0] FB_HEIGHT,
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output [31:0] FB_BASE,
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output [13:0] FB_STRIDE,
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input FB_VBL,
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input FB_LL,
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output FB_FORCE_BLANK,
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// Palette control for 8bit modes.
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// Ignored for other video modes.
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output FB_PAL_CLK,
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output [7:0] FB_PAL_ADDR,
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output [23:0] FB_PAL_DOUT,
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input [23:0] FB_PAL_DIN,
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output FB_PAL_WR,
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`endif
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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// I/O board button press simulation (active high)
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// b[1]: user button
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// b[0]: osd button
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output [1:0] BUTTONS,
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input CLK_AUDIO, // 24.576 MHz
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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//ADC
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inout [3:0] ADC_BUS,
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//SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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`ifdef USE_DDRAM
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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`endif
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`ifdef USE_SDRAM
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE,
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`endif
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`ifdef DUAL_SDRAM
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//Secondary SDRAM
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input SDRAM2_EN,
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output SDRAM2_CLK,
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output [12:0] SDRAM2_A,
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output [1:0] SDRAM2_BA,
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inout [15:0] SDRAM2_DQ,
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output SDRAM2_nCS,
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output SDRAM2_nCAS,
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output SDRAM2_nRAS,
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output SDRAM2_nWE,
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`endif
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input UART_CTS,
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output UART_RTS,
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input UART_RXD,
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output UART_TXD,
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output UART_DTR,
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input UART_DSR,
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// Open-drain User port.
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// 0 - D+/RX
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// 1 - D-/TX
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// 2..6 - USR2..USR6
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// Set USER_OUT to 1 to read from USER_IN.
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input [6:0] USER_IN,
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output [6:0] USER_OUT,
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input OSD_STATUS
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);
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assign ADC_BUS = 'Z;
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assign USER_OUT = '1;
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assign {UART_RTS, UART_TXD, UART_DTR} = 0;
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
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assign VGA_SL = 0;
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assign VGA_F1 = 0;
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assign VGA_SCALER = 0;
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assign VIDEO_ARX = 0;
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assign VIDEO_ARY = 0;
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assign AUDIO_S = 0;
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assign AUDIO_L = 0;
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assign AUDIO_R = 0;
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assign AUDIO_MIX = 0;
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign LED_USER = 0;
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assign BUTTONS = 0;
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wire [31:0] status;
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wire [1:0] buttons;
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`include "build_id.v"
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localparam CONF_STR =
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{
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"MEMTEST;;",
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"J1, Reset Freq, Reset Test, Switch IC;",
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"jn, A, Start, B;",
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"jp, B, Start, A;",
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"V,v",`BUILD_DATE
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};
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reg [10:0] ps2_key;
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wire [15:0] joystick_0;
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wire [1:0] sdram_sz;
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reg [1:0] sdram_chip = 2'h0;
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hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
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(
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.clk_sys(CLK_50M),
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.HPS_BUS(HPS_BUS),
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.conf_str(CONF_STR),
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.status(status),
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.buttons(buttons),
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.sdram_sz(sdram_sz),
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.joystick_0(joystick_0),
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.ps2_key(ps2_key),
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.ps2_kbd_led_use(0),
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.ps2_kbd_led_status(0)
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);
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///////////////////////////////////////////////////////////////////
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wire clk_ram, locked;
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pll pll
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(
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.*,
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.refclk(CLK_50M),
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.rst(pll_reset | RESET),
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.outclk_0(clk_ram)
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);
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wire mgmt_waitrequest;
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reg mgmt_write;
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reg [5:0] mgmt_address;
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reg [31:0] mgmt_writedata;
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wire [63:0] reconfig_to_pll;
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wire [63:0] reconfig_from_pll;
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pll_cfg pll_cfg
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(
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.*,
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.mgmt_clk(CLK_50M),
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.mgmt_reset(RESET),
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.mgmt_read(0),
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.mgmt_readdata()
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);
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reg recfg = 0;
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reg pll_reset = 0;
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wire [31:0] cfg_param[256] =
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'{ // M K C
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'h167, 'h00808, 'hB33332DD, 'h20302,
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'h160, 'h00808, 'h00000001, 'h20302,
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'h150, 'h20807, 'h00000001, 'h20302,
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'h149, 'h00404, 'hF0A3D6B4, 'h20201,
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'h148, 'h00404, 'hE147ADBF, 'h20201,
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'h147, 'h00404, 'hD1EB851F, 'h20201,
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'h146, 'h00404, 'hC28F5C29, 'h20201,
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'h145, 'h00404, 'hB33332DD, 'h20201,
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'h144, 'h00404, 'hA3D709E8, 'h20201,
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'h143, 'h00404, 'h947AE148, 'h20201,
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'h142, 'h00404, 'h851EB852, 'h20201,
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'h141, 'h00404, 'h75C28F06, 'h20201,
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'h140, 'h00707, 'h00000001, 'h20302,
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'h139, 'h00404, 'h570A3D71, 'h20201,
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'h138, 'h00404, 'h47AE147B, 'h20201,
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'h137, 'h00404, 'h3851EA2E, 'h20201,
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'h136, 'h00404, 'h28F5C239, 'h20201,
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'h135, 'h00404, 'h1999999A, 'h20201,
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'h134, 'h00505, 'hB851EB2F, 'h00202,
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'h133, 'h00505, 'hA3D709E8, 'h00202,
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'h132, 'h00505, 'h8F5C28F6, 'h00202,
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'h131, 'h00505, 'h7AE14758, 'h00202,
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'h130, 'h00505, 'h66666611, 'h00202,
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'h129, 'h00505, 'h51EB851F, 'h00202,
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'h128, 'h00505, 'h3D70A381, 'h00202,
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'h127, 'h00505, 'h28F5C239, 'h00202,
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'h126, 'h00505, 'h147AE148, 'h00202,
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'h125, 'h00505, 'h00000001, 'h00202,
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'h124, 'h20504, 'hEB851E62, 'h00202,
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'h123, 'h20504, 'hD70A3D71, 'h00202,
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'h122, 'h20504, 'hC28F5C29, 'h00202,
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'h121, 'h20504, 'hAE147A8B, 'h00202,
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'h120, 'h00707, 'h66666611, 'h00303,
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'h110, 'h20706, 'h333332DD, 'h00303,
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'h100, 'h00404, 'h00000001, 'h00202,
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'h90, 'h00707, 'h66666666, 'h00404,
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'h80, 'h00707, 'h66666666, 'h20504,
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'h70, 'h00707, 'h00000001, 'h00505,
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'h69, 'h00404, 'h47AE147B, 'h00303,
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'h68, 'h00404, 'h28F5C28F, 'h00303,
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'h67, 'h00505, 'hB851EB85, 'h00404,
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'h66, 'h00505, 'h8F5C28F6, 'h00404,
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'h65, 'h20706, 'h00000001, 'h00505,
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'h64, 'h00606, 'hCCCCCCCD, 'h00505,
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'h63, 'h00606, 'h9999999A, 'h00505,
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'h625, 'h00404, 'hC0000000, 'h20403,
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'h62, 'h00606, 'h66666666, 'h00505,
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'h61, 'h00606, 'h33333333, 'h00505,
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'h60, 'h00404, 'h66666611, 'h20403,
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'h59, 'h00404, 'h428F5C29, 'h20403,
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'h58, 'h00404, 'h1EB851EC, 'h20403,
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'h57, 'h20504, 'h1EB851EC, 'h00404,
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'h56, 'h00505, 'h147AE148, 'h20504,
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'h55, 'h00404, 'hCCCCCCCD, 'h00404,
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'h54, 'h00404, 'hA3D709E8, 'h00404,
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'h53, 'h00404, 'h7AE14758, 'h00404,
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'h52, 'h00404, 'h51EB851F, 'h00404,
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'h51, 'h00404, 'h28F5C239, 'h00404,
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'h50, 'h00404, 'h00000001, 'h00404,
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'h49, 'h00404, 'hD1EB851F, 'h20504,
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'h48, 'h00404, 'hA3D709E8, 'h20504,
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'h47, 'h00404, 'h75C28F06, 'h20504,
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'h46, 'h00404, 'h47AE147B, 'h20504,
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'h45, 'h00404, 'h1999999A, 'h20504
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};
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reg [5:0] pos = 0;
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reg [15:0] mins = 0;
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reg [15:0] secs = 0;
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reg auto = 0;
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always @(posedge CLK_50M) begin
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reg [7:0] state = 0;
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integer min = 0, sec = 0;
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reg old_stb = 0;
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reg [15:0] old_joy = 0;
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mgmt_write <= 0;
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if(((locked && !mgmt_waitrequest) || pll_reset) && recfg) begin
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state <= state + 1'd1;
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if(!state[2:0]) begin
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case(state[7:3])
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// Start
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0: begin
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mgmt_address <= 0;
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mgmt_writedata <= 0;
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mgmt_write <= 1;
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end
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// M
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1: begin
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mgmt_address <= 4;
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mgmt_writedata <= cfg_param[{pos, 2'd1}];
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mgmt_write <= 1;
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end
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// K
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2: begin
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mgmt_address <= 7;
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mgmt_writedata <= cfg_param[{pos, 2'd2}];
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mgmt_write <= 1;
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end
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// N
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3: begin
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mgmt_address <= 3;
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mgmt_writedata <= 'h10000; //N-counter is bypassed
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mgmt_write <= 1;
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end
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// C0
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4: begin
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mgmt_address <= 5;
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mgmt_writedata <= cfg_param[{pos, 2'd3}];
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mgmt_write <= 1;
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end
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// Charge pump
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5: begin
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mgmt_address <= 9;
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mgmt_writedata <= 1;
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mgmt_write <= 1;
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end
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// Bandwidth
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6: begin
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mgmt_address <= 8;
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mgmt_writedata <= 7;
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mgmt_write <= 1;
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end
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// Apply
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7: begin
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mgmt_address <= 2;
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mgmt_writedata <= 0;
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mgmt_write <= 1;
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end
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8: pll_reset <= 1;
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9: pll_reset <= 0;
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10: recfg <= 0;
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endcase
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end
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end
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if(recfg) begin
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{min, mins} <= 0;
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{sec, secs} <= 0;
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end else begin
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min <= min + 1;
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if(min == 2999999999) begin
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min <= 0;
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if(mins[3:0]<9) mins[3:0] <= mins[3:0] + 1'd1;
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else begin
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mins[3:0] <= 0;
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if(mins[7:4]<9) mins[7:4] <= mins[7:4] + 1'd1;
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else begin
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mins[7:4] <= 0;
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if(mins[11:8]<9) mins[11:8] <= mins[11:8] + 1'd1;
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else begin
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mins[11:8] <= 0;
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if(mins[15:12]<9) mins[15:12] <= mins[15:12] + 1'd1;
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else mins[15:12] <= 0;
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end
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end
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end
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end
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sec <= sec + 1;
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if(sec == 4999999) begin
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sec <= 0;
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secs <= secs + 1'd1;
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end
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end
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old_stb <= ps2_key[10];
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old_joy <= joystick_0;
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if(old_stb != ps2_key[10] || old_joy != joystick_0) begin
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state <= 0;
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if(ps2_key[9] || joystick_0) begin
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if((ps2_key[7:0] == 'h75 || (~old_joy[3] && joystick_0[3])) && pos > 0) begin
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recfg <= 1;
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pos <= pos - 1'd1;
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auto <= 0;
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end
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if((ps2_key[7:0] == 'h72 || (~old_joy[2] && joystick_0[2])) && pos < 63) begin
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recfg <= 1;
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pos <= pos + 1'd1;
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auto <= 0;
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end
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if(ps2_key[7:0] == 'h5a || (~old_joy[4] && joystick_0[4])) begin
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recfg <= 1;
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auto <= 0;
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end
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if(ps2_key[7:0] == 'h1c || (~old_joy[5] && joystick_0[5])) begin
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recfg <= 1;
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pos <= 0;
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auto <= 1;
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end
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if(ps2_key[7:0] == 'h21 || (~old_joy[6] && joystick_0[6])) begin
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recfg <= 1;
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if (sdram_chip == 2) sdram_chip <= 0; else sdram_chip <= sdram_chip + 1'd1;
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|
end
|
|
end
|
|
end
|
|
|
|
if(auto && (failcount && passcount) && !recfg && pos < 63) begin
|
|
recfg <= 1;
|
|
pos <= pos + 1'd1;
|
|
end
|
|
|
|
if(status[0] | buttons[1]) begin
|
|
recfg <= 1;
|
|
pos <= 0;
|
|
auto <= 1;
|
|
sdram_chip <= 0;
|
|
end
|
|
end
|
|
|
|
|
|
///////////////////////////////////////////////////////////////////
|
|
assign SDRAM_CKE = 1;
|
|
|
|
reg reset = 0;
|
|
always @(posedge clk_ram) begin
|
|
integer timeout;
|
|
|
|
if(timeout) timeout <= timeout - 1;
|
|
reset <= |timeout;
|
|
|
|
if((recfg || ~locked) && (timeout < 1000000)) timeout <= 1000000;
|
|
|
|
if(RESET) timeout <= 100000000;
|
|
end
|
|
|
|
wire [31:0] passcount, failcount;
|
|
tester my_memtst
|
|
(
|
|
.clk(clk_ram),
|
|
.rst_n(~reset),
|
|
.sz(sdram_sz),
|
|
.chip(sdram_chip),
|
|
.passcount(passcount),
|
|
.failcount(failcount),
|
|
.DRAM_CLK(SDRAM_CLK),
|
|
.DRAM_DQ(SDRAM_DQ),
|
|
.DRAM_ADDR(SDRAM_A),
|
|
.DRAM_LDQM(SDRAM_DQML),
|
|
.DRAM_UDQM(SDRAM_DQMH),
|
|
.DRAM_WE_N(SDRAM_nWE),
|
|
.DRAM_CS_N(SDRAM_nCS),
|
|
.DRAM_RAS_N(SDRAM_nRAS),
|
|
.DRAM_CAS_N(SDRAM_nCAS),
|
|
.DRAM_BA_0(SDRAM_BA[0]),
|
|
.DRAM_BA_1(SDRAM_BA[1])
|
|
);
|
|
|
|
|
|
///////////////////////////////////////////////////////////////////
|
|
wire videoclk;
|
|
|
|
vpll vpll
|
|
(
|
|
.refclk(CLK_50M),
|
|
.rst(0),
|
|
.outclk_0(videoclk)
|
|
);
|
|
|
|
assign CLK_VIDEO = videoclk;
|
|
assign CE_PIXEL = 1;
|
|
|
|
wire hs, vs;
|
|
wire [1:0] b, r, g;
|
|
vgaout showrez
|
|
(
|
|
.clk(videoclk),
|
|
.rez1({sdram_sz, passcount[27:0]}),
|
|
.rez2(failcount),
|
|
.rez3((sdram_sz == 3) ? ~sdram_chip : 2'b00),
|
|
.bg(6'b000001),
|
|
.freq(16'hF000 | cfg_param[{pos, 2'd0}][11:0]),
|
|
.elapsed(mins),
|
|
.mark(8'h80 >> {~auto, secs[2:0]}),
|
|
.hs(hs),
|
|
.vs(vs),
|
|
.de(VGA_DE),
|
|
.b(b),
|
|
.r(r),
|
|
.g(g)
|
|
);
|
|
|
|
assign VGA_HS = ~hs;
|
|
assign VGA_VS = ~vs;
|
|
|
|
assign VGA_B = {4{b}};
|
|
assign VGA_R = {4{r}};
|
|
assign VGA_G = {4{g}};
|
|
|
|
endmodule
|