* hdmi_cec
* Improve HDMI CEC startup
* hdmi_cec
* Improve HDMI CEC startup
* Use ADV7513 interrupt registers for CEC
Set ADV7513 main 0xE1 to the CEC I2C map address, 0xE2 to 0x00 to power the CEC block, and 0xE3 |= 0x0E for CEC control setup.
Keep HPD forced high through main 0xD6 = 0xC0 after the startup pulse, but clear main 0x94[7] so HPD does not drive the shared HDMI interrupt line.
Clear main 0xA1[6] so the monitor-sense/video-active block stays powered; ADV7513 interrupt status registers 0x94-0x97 are only valid while that block is alive.
Set main 0x95 = 0x07 to enable only CEC RX-ready interrupts, use main 0x97 to clear RX/TX interrupt latches, and clear 0x96/0x97 at init.
Read CEC RX-ready from CEC map 0x49, keep CEC RX enabled with 0x4A = 0x08, release consumed RX slots through 0x4A, and remove fallback polling of RX length registers 0x25/0x37/0x48.
Use main 0x97 bits for CEC TX done/retry/arbitration status, keep CEC TX disabled through 0x11 except while sending, and set the CEC clock divider 0x4E = 0x3D.
Gate RX handling on fpga_get_hdmi_int() so normal CEC polling no longer performs DDC/CEC I2C reads unless the FPGA HDMI interrupt bit is asserted.
Reply to CEC vendor/name discovery so displays can identify MiSTer after registration.
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Co-authored-by: misteraddons <51079966+misteraddons@users.noreply.github.com>
