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119 lines
4.0 KiB
VHDL
119 lines
4.0 KiB
VHDL
--
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-- mapper.vhd
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-- Memory mapper
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-- Revision 1.00
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--
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-- Copyright (c) 2006 Kazuhiro Tsujikawa (ESE Artists' factory)
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-- All rights reserved.
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--
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-- Redistribution and use of this source code or any derivative works, are
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-- permitted provided that the following conditions are met:
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--
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-- 1. Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- 3. Redistributions may not be sold, nor may they be used in a commercial
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-- product or activity without specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity mapper is
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port(
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clk21m : in std_logic;
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reset : in std_logic;
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clkena : in std_logic;
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req : in std_logic;
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ack : out std_logic;
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mem : in std_logic;
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wrt : in std_logic;
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adr : in std_logic_vector(15 downto 0);
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dbi : out std_logic_vector(7 downto 0);
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dbo : in std_logic_vector(7 downto 0);
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ramreq : out std_logic;
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ramwrt : out std_logic;
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ramadr : out std_logic_vector(21 downto 0);
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ramdbi : in std_logic_vector(7 downto 0);
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ramdbo : out std_logic_vector(7 downto 0)
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);
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end mapper;
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architecture rtl of mapper is
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signal MapBank0 : std_logic_vector(7 downto 0);
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signal MapBank1 : std_logic_vector(7 downto 0);
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signal MapBank2 : std_logic_vector(7 downto 0);
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signal MapBank3 : std_logic_vector(7 downto 0);
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begin
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----------------------------------------------------------------
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-- Mapper bank register access
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----------------------------------------------------------------
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process(clk21m, reset)
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begin
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if (rising_edge(clk21m)) then
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if (reset = '1') then
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MapBank0 <= X"03";
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MapBank1 <= X"02";
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MapBank2 <= X"01";
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MapBank3 <= X"00";
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else
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-- I/O port access on FC-FFh ... Mapper bank register write
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if (req = '1' and mem = '0' and wrt = '1') then
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case adr(1 downto 0) is
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when "00" => MapBank0 <= dbo;
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when "01" => MapBank1 <= dbo;
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when "10" => MapBank2 <= dbo;
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when others => MapBank3 <= dbo;
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end case;
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end if;
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end if;
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end if;
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end process;
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ack <= req when mem = '0' else '0';
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RamReq <= req when mem = '1' else '0';
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RamWrt <= wrt;
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RamAdr <= MapBank0(7 downto 0) & adr(13 downto 0) when adr(15 downto 14) = "00" else
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MapBank1(7 downto 0) & adr(13 downto 0) when adr(15 downto 14) = "01" else
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MapBank2(7 downto 0) & adr(13 downto 0) when adr(15 downto 14) = "10" else
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MapBank3(7 downto 0) & adr(13 downto 0);
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RamDbo <= dbo;
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dbi <= RamDbi when mem = '1' else
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MapBank0 when adr(1 downto 0) = "00" else
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MapBank1 when adr(1 downto 0) = "01" else
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MapBank2 when adr(1 downto 0) = "10" else
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MapBank3;
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end rtl;
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