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20 lines
414 B
Verilog
20 lines
414 B
Verilog
module io_decoder
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(
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input [7:0] addr,
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input iorq_n,
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input m1_n,
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output vdp_n,
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output psg_n,
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output ppi_n,
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output cen_n
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);
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wire io_en = ~iorq_n & m1_n;
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assign cen_n = ~((addr[7:3] == 5'b10010) & io_en);
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assign vdp_n = ~((addr[7:3] == 5'b10011) & io_en);
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assign psg_n = ~((addr[7:3] == 5'b10100) & io_en);
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assign ppi_n = ~((addr[7:3] == 5'b10101) & io_en);
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endmodule
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