mirror of
https://github.com/MiSTer-devel/Life_MiSTer.git
synced 2026-04-19 03:04:22 +00:00
250 lines
20 KiB
Tcl
250 lines
20 KiB
Tcl
## Generated SDC file "/media/hrvoje/fpga/EDSAC_MiSTer/sys/sys_top.sdc"
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## Copyright (C) 2018 Intel Corporation. All rights reserved.
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## Your use of Intel Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Intel Program License
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## Subscription Agreement, the Intel Quartus Prime License Agreement,
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## the Intel FPGA IP License Agreement, or other applicable license
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## agreement, including, without limitation, that your use is for
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## the sole purpose of programming logic devices manufactured by
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## Intel and sold by Intel or its authorized distributors. Please
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## refer to the applicable agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus Prime"
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## VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition"
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## DATE "Fri Apr 17 02:33:48 2020"
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##
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## DEVICE "5CSEBA6U23I7"
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##
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name {FPGA_CLK1_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK1_50}]
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create_clock -name {FPGA_CLK2_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK2_50}]
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create_clock -name {FPGA_CLK3_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {FPGA_CLK3_50}]
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create_clock -name {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk} -period 10.000 -waveform { 0.000 5.000 } [get_pins -compatibility_mode {*|h2f_user0_clk}]
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create_clock -name {spi_sck} -period 10.000 -waveform { 0.000 5.000 } [get_pins -compatibility_mode {spi|sclk_out}]
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create_clock -name {emu:emu|snd_wait[0]} -period 20.000 -waveform { 0.000 10.000 } [get_registers { emu:emu|snd_wait[0] }]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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create_generated_clock -name {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk} -source [get_pins {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 3 -master_clock {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]} [get_pins {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}]
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create_generated_clock -name {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]} -source [get_pins {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin}] -duty_cycle 50/1 -multiply_by 4563 -divide_by 512 -master_clock {FPGA_CLK1_50} [get_pins {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]}]
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create_generated_clock -name {HDMI_CLK} -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] -master_clock {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk} [get_ports {HDMI_TX_CLK}]
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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set_clock_uncertainty -rise_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -rise_to [get_clocks {HDMI_CLK}] -setup 0.300
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set_clock_uncertainty -rise_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -rise_to [get_clocks {HDMI_CLK}] -hold 0.210
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set_clock_uncertainty -rise_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -fall_to [get_clocks {HDMI_CLK}] -setup 0.300
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set_clock_uncertainty -rise_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -fall_to [get_clocks {HDMI_CLK}] -hold 0.210
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set_clock_uncertainty -rise_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -rise_to [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -setup 0.200
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set_clock_uncertainty -rise_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -rise_to [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -hold 0.060
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set_clock_uncertainty -rise_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -fall_to [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -setup 0.200
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set_clock_uncertainty -rise_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -fall_to [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -hold 0.060
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set_clock_uncertainty -fall_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -rise_to [get_clocks {HDMI_CLK}] -setup 0.300
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set_clock_uncertainty -fall_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -rise_to [get_clocks {HDMI_CLK}] -hold 0.210
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set_clock_uncertainty -fall_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -fall_to [get_clocks {HDMI_CLK}] -setup 0.300
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set_clock_uncertainty -fall_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -fall_to [get_clocks {HDMI_CLK}] -hold 0.210
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set_clock_uncertainty -fall_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -rise_to [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -setup 0.200
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set_clock_uncertainty -fall_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -rise_to [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -hold 0.060
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set_clock_uncertainty -fall_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -fall_to [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -setup 0.200
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set_clock_uncertainty -fall_from [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -fall_to [get_clocks {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -hold 0.060
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set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -rise_to [get_clocks {spi_sck}] 0.060
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set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -fall_to [get_clocks {spi_sck}] 0.060
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set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.110
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set_clock_uncertainty -rise_from [get_clocks {spi_sck}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.110
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set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -rise_to [get_clocks {spi_sck}] 0.060
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set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -fall_to [get_clocks {spi_sck}] 0.060
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set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -rise_to [get_clocks {FPGA_CLK3_50}] 0.110
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set_clock_uncertainty -fall_from [get_clocks {spi_sck}] -fall_to [get_clocks {FPGA_CLK3_50}] 0.110
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set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.060
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set_clock_uncertainty -rise_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.060
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set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -rise_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.060
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set_clock_uncertainty -fall_from [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] -fall_to [get_clocks {sysmem|fpga_interfaces|clocks_resets|h2f_user0_clk}] 0.060
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set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -setup 0.170
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set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -hold 0.060
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set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -setup 0.170
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set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -hold 0.060
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set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -setup 0.170
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set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -rise_to [get_clocks {FPGA_CLK3_50}] -hold 0.060
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set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -setup 0.170
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set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK3_50}] -fall_to [get_clocks {FPGA_CLK3_50}] -hold 0.060
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set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {HDMI_CLK}] 0.380
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set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {HDMI_CLK}] 0.380
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set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -setup 0.310
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set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -hold 0.270
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set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -setup 0.310
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set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -hold 0.270
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set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {HDMI_CLK}] 0.380
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set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {HDMI_CLK}] 0.380
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set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -setup 0.310
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set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {FPGA_CLK2_50}] -hold 0.270
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set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -setup 0.310
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set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {FPGA_CLK2_50}] -hold 0.270
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set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK1_50}] -rise_to [get_clocks {FPGA_CLK1_50}] -setup 0.170
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set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK1_50}] -rise_to [get_clocks {FPGA_CLK1_50}] -hold 0.060
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set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK1_50}] -fall_to [get_clocks {FPGA_CLK1_50}] -setup 0.170
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set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK1_50}] -fall_to [get_clocks {FPGA_CLK1_50}] -hold 0.060
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set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK1_50}] -rise_to [get_clocks {FPGA_CLK1_50}] -setup 0.170
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set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK1_50}] -rise_to [get_clocks {FPGA_CLK1_50}] -hold 0.060
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set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK1_50}] -fall_to [get_clocks {FPGA_CLK1_50}] -setup 0.170
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set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK1_50}] -fall_to [get_clocks {FPGA_CLK1_50}] -hold 0.060
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set_clock_uncertainty -rise_from [get_clocks {emu:emu|snd_wait[0]}] -rise_to [get_clocks {emu:emu|snd_wait[0]}] 0.270
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set_clock_uncertainty -rise_from [get_clocks {emu:emu|snd_wait[0]}] -fall_to [get_clocks {emu:emu|snd_wait[0]}] 0.270
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set_clock_uncertainty -rise_from [get_clocks {emu:emu|snd_wait[0]}] -rise_to [get_clocks {FPGA_CLK2_50}] 0.290
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set_clock_uncertainty -rise_from [get_clocks {emu:emu|snd_wait[0]}] -fall_to [get_clocks {FPGA_CLK2_50}] 0.290
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set_clock_uncertainty -fall_from [get_clocks {emu:emu|snd_wait[0]}] -rise_to [get_clocks {emu:emu|snd_wait[0]}] 0.270
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set_clock_uncertainty -fall_from [get_clocks {emu:emu|snd_wait[0]}] -fall_to [get_clocks {emu:emu|snd_wait[0]}] 0.270
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set_clock_uncertainty -fall_from [get_clocks {emu:emu|snd_wait[0]}] -rise_to [get_clocks {FPGA_CLK2_50}] 0.290
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set_clock_uncertainty -fall_from [get_clocks {emu:emu|snd_wait[0]}] -fall_to [get_clocks {FPGA_CLK2_50}] 0.290
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set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu:emu|snd_wait[0]}] 0.290
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set_clock_uncertainty -rise_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu:emu|snd_wait[0]}] 0.290
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set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -rise_to [get_clocks {emu:emu|snd_wait[0]}] 0.290
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set_clock_uncertainty -fall_from [get_clocks {FPGA_CLK2_50}] -fall_to [get_clocks {emu:emu|snd_wait[0]}] 0.290
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_DE}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_DE}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[0]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[0]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[1]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[1]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[2]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[2]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[3]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[3]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[4]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[4]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[5]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[5]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[6]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[6]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[7]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[7]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[8]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[8]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[9]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[9]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[10]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[10]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[11]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[11]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[12]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[12]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[13]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[13]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[14]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[14]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[15]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[15]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[16]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[16]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[17]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[17]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[18]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[18]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[19]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[19]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[20]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[20]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[21]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[21]}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[22]}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[22]}]
|
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_D[23]}]
|
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_D[23]}]
|
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_HS}]
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_HS}]
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set_output_delay -add_delay -max -clock [get_clocks {HDMI_CLK}] 4.000 [get_ports {HDMI_TX_VS}]
|
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set_output_delay -add_delay -min -clock [get_clocks {HDMI_CLK}] 3.000 [get_ports {HDMI_TX_VS}]
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#**************************************************************
|
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# Set Clock Groups
|
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#**************************************************************
|
|
|
|
set_clock_groups -exclusive -group [get_clocks { *|pll|pll_inst|altera_pll_i|*[*].*|divclk}] -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] -group [get_clocks { *|h2f_user0_clk}] -group [get_clocks { FPGA_CLK1_50 }] -group [get_clocks { FPGA_CLK2_50 }] -group [get_clocks { FPGA_CLK3_50 }]
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|
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#**************************************************************
|
|
# Set False Path
|
|
#**************************************************************
|
|
|
|
set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
|
|
set_false_path -from [get_ports {KEY*}]
|
|
set_false_path -from [get_ports {BTN_*}]
|
|
set_false_path -to [get_ports {LED_*}]
|
|
set_false_path -to [get_ports {VGA_*}]
|
|
set_false_path -to [get_ports {AUDIO_SPDIF}]
|
|
set_false_path -to [get_ports {AUDIO_L}]
|
|
set_false_path -to [get_ports {AUDIO_R}]
|
|
set_false_path -to [get_keepers {cfg[*]}]
|
|
set_false_path -from [get_keepers {cfg[*]}]
|
|
set_false_path -to [get_keepers {wcalc[*] hcalc[*]}]
|
|
|
|
|
|
#**************************************************************
|
|
# Set Multicycle Path
|
|
#**************************************************************
|
|
|
|
|
|
|
|
#**************************************************************
|
|
# Set Maximum Delay
|
|
#**************************************************************
|
|
|
|
|
|
|
|
#**************************************************************
|
|
# Set Minimum Delay
|
|
#**************************************************************
|
|
|
|
|
|
|
|
#**************************************************************
|
|
# Set Input Transition
|
|
#**************************************************************
|
|
|