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https://github.com/MiSTer-devel/Life_MiSTer.git
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88 lines
2.5 KiB
Verilog
88 lines
2.5 KiB
Verilog
module row (
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input clock,
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input [0:0] shiftin,
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output [0:0] shiftout
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);
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altshift_taps ALTSHIFT_TAPS_component (
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.clock (clock),
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.shiftin (shiftin),
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.shiftout (shiftout)
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);
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defparam
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ALTSHIFT_TAPS_component.intended_device_family = "Cyclone V",
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ALTSHIFT_TAPS_component.lpm_hint = "RAM_BLOCK_TYPE=M10K",
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ALTSHIFT_TAPS_component.lpm_type = "altshift_taps",
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ALTSHIFT_TAPS_component.number_of_taps = 1,
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ALTSHIFT_TAPS_component.tap_distance = 2198,
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ALTSHIFT_TAPS_component.width = 1;
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endmodule
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module ring (
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input clock,
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input enable,
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input shiftin,
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output shiftout,
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input [31:0] status
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);
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reg [21:0] counter = 0;
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always @(posedge clock) begin
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if (enable)
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counter <= ~|counter ? 2472795 : counter - 1'b1;
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end
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altsyncram altsyncram_component (
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.address_a (counter),
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.address_b (counter),
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.clock0 (clock),
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.data_a (shiftin),
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.wren_a (enable),
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.q_b (shiftout),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b (1'b1),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_b = "NONE",
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altsyncram_component.address_reg_b = "CLOCK0",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.init_file = "./roms/initial.hex",
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altsyncram_component.intended_device_family = "Cyclone V",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 2472800,
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altsyncram_component.numwords_b = 2472800,
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altsyncram_component.operation_mode = "DUAL_PORT",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_b = "CLOCK0",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.ram_block_type = "M10K",
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altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA",
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altsyncram_component.widthad_a = 22,
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altsyncram_component.widthad_b = 22,
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altsyncram_component.width_a = 1,
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altsyncram_component.width_b = 1,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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