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56 lines
1.5 KiB
Verilog
56 lines
1.5 KiB
Verilog
`timescale 1ps / 1ps
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/*============================================================================
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Aznable (custom 8-bit computer system) - Generic timer
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Author: Jim Gregory - https://github.com/JimmyStones/
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Version: 1.0
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Date: 2021-10-20
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>.
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===========================================================================*/
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module generic_timer #(
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parameter COUNTER_WIDTH = 16,
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parameter DIVIDER_WIDTH = 15,
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parameter INTERVAL = 15'd24000
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)(
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input clk,
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input reset,
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output reg [COUNTER_WIDTH-1:0] counter
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);
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reg [DIVIDER_WIDTH-1:0] divider = {DIVIDER_WIDTH{1'b0}};
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always @(posedge clk or posedge reset)
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begin
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if(reset)
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begin
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counter <= {COUNTER_WIDTH{1'b0}};
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divider <= {DIVIDER_WIDTH{1'b0}};
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end
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else
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begin
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if(divider==INTERVAL)
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begin
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counter <= counter + 1'b1;
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divider <= {DIVIDER_WIDTH{1'b0}};
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end
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else
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begin
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divider <= divider + 1'b1;
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end
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end
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end
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endmodule |