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68 lines
1.8 KiB
Verilog
68 lines
1.8 KiB
Verilog
/*============================================================================
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Generic dual-port RAM module
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Author: Jim Gregory - https://github.com/JimmyStones/
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Version: 1.0
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Date: 2021-07-03
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>.
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===========================================================================*/
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module dpram #(
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parameter address_width = 10,
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parameter data_width = 8,
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parameter init_file= ""
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) (
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input wire clock_a,
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input wire wren_a,
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input wire [address_width-1:0] address_a,
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input wire [data_width-1:0] data_a,
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output reg [data_width-1:0] q_a,
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input wire clock_b,
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input wire wren_b,
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input wire [address_width-1:0] address_b,
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input wire [data_width-1:0] data_b,
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output reg [data_width-1:0] q_b
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);
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initial begin
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if (init_file>0)
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begin
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// $display("Loading dpram from file:");
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// $display(init_file);
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$readmemh(init_file, mem);
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end
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end
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localparam ramLength = (2**address_width);
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reg [data_width-1:0] mem [ramLength-1:0];
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always @(posedge clock_a) begin
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q_a <= mem[address_a];
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if(wren_a) begin
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q_a <= data_a;
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mem[address_a] <= data_a;
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end
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end
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always @(posedge clock_b) begin
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q_b <= mem[address_b];
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if(wren_b) begin
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q_b <= data_b;
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mem[address_b] <= data_b;
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end
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end
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endmodule |