mirror of
https://github.com/MiSTer-devel/InputTest_MiSTer.git
synced 2026-04-19 03:04:18 +00:00
22 lines
1.2 KiB
Plaintext
22 lines
1.2 KiB
Plaintext
set_global_assignment -name SYSTEMVERILOG_FILE InputTest.sv
|
|
set_global_assignment -name QIP_FILE rtl/tv80/TV80.qip
|
|
set_global_assignment -name CDF_FILE jtag.cdf
|
|
set_global_assignment -name QIP_FILE sys/sys.qip
|
|
set_global_assignment -name VERILOG_FILE rtl/JTFRAME/jtframe_vtimer.v
|
|
set_global_assignment -name VERILOG_FILE rtl/JTFRAME/jtframe_resync.v
|
|
set_global_assignment -name VERILOG_FILE rtl/JTFRAME/jtframe_cen24.v
|
|
set_global_assignment -name QIP_FILE rtl/jt49/jt49.qip
|
|
set_global_assignment -name QIP_FILE rtl/jt5205/jt5205.qip
|
|
set_global_assignment -name VERILOG_FILE rtl/charmap.v
|
|
set_global_assignment -name VERILOG_FILE rtl/sprite_engine.v
|
|
set_global_assignment -name VERILOG_FILE rtl/tilemap.v
|
|
set_global_assignment -name VERILOG_FILE rtl/lfsr.v
|
|
set_global_assignment -name VERILOG_FILE rtl/starfield.v
|
|
set_global_assignment -name VERILOG_FILE rtl/music.v
|
|
set_global_assignment -name VERILOG_FILE rtl/sound.v
|
|
set_global_assignment -name VERILOG_FILE rtl/generic_timer.v
|
|
set_global_assignment -name VERILOG_FILE rtl/system.v
|
|
set_global_assignment -name VERILOG_FILE rtl/dpram.v
|
|
set_global_assignment -name VERILOG_FILE rtl/dpram_w1r2.v
|
|
set_global_assignment -name VERILOG_FILE rtl/spram.v
|
|
set_global_assignment -name VERILOG_FILE rtl/pause.v |