mirror of
https://github.com/MiSTer-devel/InputTest_MiSTer.git
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354 lines
9.3 KiB
Verilog
354 lines
9.3 KiB
Verilog
`timescale 1ns / 1ps
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/*============================================================================
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Aznable (custom 8-bit computer system) - System module
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Author: Jim Gregory - https://github.com/JimmyStones/
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Version: 1.0
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Date: 2021-07-03
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>.
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===========================================================================*/
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module system (
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input clk_sys,
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input ce_pix,
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input reset,
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input [13:0] dn_addr,
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input dn_wr,
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input [7:0] dn_data,
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input [7:0] dn_index,
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// 6 devices, 32 buttons each
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input [191:0] joystick,
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// 6 devices, 16 bits each - -127..+127, Y: [15:8], X: [7:0]
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input [95:0] analog_l,
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// 6 devices, 16 bits each - -127..+127, Y: [15:8], X: [7:0]
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input [95:0] analog_r,
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// 6 devices, 8 bits each - paddle 0..255
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input [47:0] paddle,
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// 6 devices, 16 bits eachspinner [7:0] -128..+127, [8] - toggle with every update, [9-15] padding
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input [95:0] spinner,
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// ps2 alternative interface.
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// [8] - extended, [9] - pressed, [10] - toggles with every press/release
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input [10:0] ps2_key,
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// [0-23] mouse data, [24] - toggles with every event, [25-31] - padding,
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// [32-39] - wheel movements, [40-47] - reserved(additional buttons)
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input [47:0] ps2_mouse,
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// [31:0] - seconds since 1970-01-01 00:00:00, [32] - toggle with every change
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input [32:0] timestamp,
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output VGA_HS,
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output VGA_VS,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HB,
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output VGA_VB
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);
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localparam [8:0] VGA_WIDTH = 9'd320;
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localparam [8:0] VGA_HEIGHT = 9'd240;
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wire _hb;
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wire _vb;
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assign VGA_HB = ~_hb;
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assign VGA_VB = ~_vb;
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wire [8:0] hcnt;
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wire [8:0] vcnt;
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// Display timing module from JTFRAME
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jtframe_vtimer #(
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.HB_START(VGA_WIDTH - 1'b1),
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.VB_START(VGA_HEIGHT- 1'b1)
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) vtimer
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(
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.clk(clk_sys),
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.pxl_cen(ce_pix),
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.V(vcnt),
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.H(hcnt),
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.Hinit(),
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.Vinit(),
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.LHBL(_hb),
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.LVBL(_vb),
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.HS(VGA_HS),
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.VS(VGA_VS)
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);
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// Millisecond timer
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reg [15:0] timer;
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reg [14:0] timer_divider = 15'd0;
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always @(posedge clk_sys)
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begin
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if(timer_cs == 1'b1 && cpu_wr_n == 1'b0)
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begin
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timer <= 16'd0;
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timer_divider <= 15'd0;
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end
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else
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begin
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if(timer_divider==15'd24000)
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begin
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timer <= timer + 16'd1;
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timer_divider <= 15'd0;
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end
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else
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begin
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timer_divider <= timer_divider + 15'd1;
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end
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end
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end
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// Character map
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wire [3:0] chpos_x = 4'd7 - hcnt[2:0];
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wire [2:0] chpos_y = vcnt[2:0];
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wire [5:0] chram_x = hcnt[8:3];
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wire [5:0] chram_y = vcnt[8:3];
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wire [11:0] chram_addr = {chram_y, chram_x};
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wire [11:0] chrom_addr = {1'b0, chmap_data_out[7:0], chpos_y};
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wire chpixel = chrom_data_out[chpos_x[2:0]];
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// RGB mixer
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wire [2:0] r_temp = chpixel ? fgcolram_data_out[2:0] : bgcolram_data_out[2:0];
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wire [2:0] g_temp = chpixel ? fgcolram_data_out[5:3] : bgcolram_data_out[5:3];
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wire [1:0] b_temp = chpixel ? fgcolram_data_out[7:6] : bgcolram_data_out[7:6];
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// Convert RGb to 24bpp
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assign VGA_R = {{2{r_temp}},2'b0};
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assign VGA_G = {{2{g_temp}},2'b0};
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assign VGA_B = {{3{b_temp}},2'b0};
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// CPU control signals
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wire [15:0] cpu_addr;
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wire [7:0] cpu_din;
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wire [7:0] cpu_dout;
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wire cpu_rd_n;
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wire cpu_wr_n;
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wire cpu_mreq_n;
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// include Z80 CPU
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tv80s T80x (
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.reset_n ( !reset ),
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.clk ( clk_sys ),
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.wait_n ( 1'b1 ),
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.int_n ( 1'b1 ),
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.nmi_n ( 1'b1 ),
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.busrq_n ( 1'b1 ),
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.mreq_n ( cpu_mreq_n ),
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.rd_n ( cpu_rd_n ),
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.wr_n ( cpu_wr_n ),
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.A ( cpu_addr ),
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.di ( cpu_din ),
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.dout ( cpu_dout ),
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.m1_n (),
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.iorq_n (),
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.rfsh_n (),
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.halt_n (),
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.busak_n ()
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);
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// RAM data to CPU
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wire [7:0] pgrom_data_out;
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wire [7:0] chrom_data_out;
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wire [7:0] wkram_data_out;
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wire [7:0] chram_data_out;
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wire [7:0] fgcolram_data_out;
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wire [7:0] bgcolram_data_out;
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// RAM data to GFX
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wire [7:0] chmap_data_out;
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// Hardware inputs
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wire [7:0] in0_data_out = {VGA_HS, VGA_VS,VGA_HB, VGA_VB, 4'b1000};
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wire [7:0] joystick_data_out = joystick[cpu_addr[7:0] +: 8];
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wire [7:0] analog_l_data_out = analog_l[cpu_addr[6:0] +: 8];
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wire [7:0] analog_r_data_out = analog_r[cpu_addr[6:0] +: 8];
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wire [7:0] paddle_data_out = paddle[cpu_addr[5:0] +: 8];
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wire [7:0] spinner_data_out = spinner[cpu_addr[6:0] +: 8];
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wire [7:0] ps2_key_data_out = ps2_key[cpu_addr[3:0] +: 8];
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wire [7:0] ps2_mouse_data_out = ps2_mouse[cpu_addr[5:0] +: 8];
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wire [7:0] timestamp_data_out = timestamp[cpu_addr[5:0] +: 8];
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wire [7:0] timer_data_out = timer[cpu_addr[3:0] +: 8];
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// CPU address decodes
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wire pgrom_cs = cpu_addr[15:14] == 2'b00;
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//wire chrom_cs = cpu_addr[15:12] == 4'b0100; // CPU never accesses the character ROM data directly
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wire chram_cs = cpu_addr[15:11] == 5'b10000;
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wire fgcolram_cs = cpu_addr[15:11] == 5'b10001;
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wire bgcolram_cs = cpu_addr[15:11] == 5'b10010;
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wire wkram_cs = cpu_addr[15:14] == 2'b11;
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wire in0_cs = cpu_addr == 16'h6000;
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wire joystick_cs = cpu_addr[15:8] == 8'b01110000;
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wire analog_l_cs = cpu_addr[15:8] == 8'b01110001;
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wire analog_r_cs = cpu_addr[15:8] == 8'b01110010;
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wire paddle_cs = cpu_addr[15:8] == 8'b01110011;
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wire spinner_cs = cpu_addr[15:8] == 8'b01110100;
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wire ps2_key_cs = cpu_addr[15:8] == 8'b01110101;
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wire ps2_mouse_cs = cpu_addr[15:8] == 8'b01110110;
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wire timestamp_cs = cpu_addr[15:8] == 8'b01110111;
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wire timer_cs = cpu_addr[15:8] == 8'b01111000;
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//always @(posedge timestamp[32]) begin
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// $display("%b", timestamp);
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// end
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//always @(posedge clk_sys) begin
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// if(pgrom_cs) $display("%x pgrom o %x", cpu_addr, pgrom_data_out);
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// if(wkram_cs) $display("%x wkram i %x o %x w %b", cpu_addr, cpu_dout, wkram_data_out, wkram_wr);
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// if(chram_cs) $display("%x chram i %x o %x w %b", cpu_addr, cpu_dout, chram_data_out, chram_wr);
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// if(fgcolram_cs) $display("%x fgcolram i %x o %x w %b", cpu_addr, cpu_dout, fgcolram_data_out, fgcolram_wr);
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// if(in0_cs) $display("%x in0 i %x o %x", cpu_addr, cpu_dout, in0_data_out);
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// if(joystick_cs) $display("joystick %b %b", joystick_bit, joystick_data_out);
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// if(analog_l_cs) $display("analog_l %b %b", analog_l_bit, analog_l_data_out);
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// if(analog_r_cs) $display("analog_r %b %b", analog_r_bit, analog_r_data_out);
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// if(paddle_cs) $display("paddle %b", paddle_data_out);
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// if(ps2_key_cs) $display("ps2_key %b %x", ps2_key_data_out, cpu_addr[3:0]);
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// $display("%x", cpu_addr);
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//end
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always @(posedge ps2_mouse[24]) begin
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$display("%b", ps2_mouse);
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end
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// CPU data mux
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assign cpu_din = pgrom_cs ? pgrom_data_out :
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wkram_cs ? wkram_data_out :
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chram_cs ? chram_data_out :
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fgcolram_cs ? fgcolram_data_out :
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bgcolram_cs ? bgcolram_data_out :
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in0_cs ? in0_data_out :
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joystick_cs ? joystick_data_out :
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analog_l_cs ? analog_l_data_out :
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analog_r_cs ? analog_r_data_out :
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paddle_cs ? paddle_data_out :
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spinner_cs ? spinner_data_out :
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ps2_key_cs ? ps2_key_data_out :
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ps2_mouse_cs ? ps2_mouse_data_out :
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timestamp_cs ? timestamp_data_out :
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timer_cs ? timer_data_out :
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8'b00000000;
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// Rom upload write enables
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wire pgrom_wr = dn_wr && dn_index == 8'b0;
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wire chrom_wr = dn_wr && dn_index == 8'b1;
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// Ram write enables
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wire wkram_wr = !cpu_wr_n && wkram_cs;
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wire chram_wr = !cpu_wr_n && chram_cs;
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wire fgcolram_wr = !cpu_wr_n && fgcolram_cs;
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wire bgcolram_wr = !cpu_wr_n && bgcolram_cs;
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// MEMORY
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// ------
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// Program ROM - 0x0000 - 0x3FFF (0x4000 / 16384 bytes)
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dpram #(14,8, "rom.hex") pgrom
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(
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.clock_a(clk_sys),
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.address_a(cpu_addr[13:0]),
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.wren_a(1'b0),
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.data_a(),
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.q_a(pgrom_data_out),
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.clock_b(clk_sys),
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.address_b(dn_addr[13:0]),
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.wren_b(pgrom_wr),
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.data_b(dn_data),
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.q_b()
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);
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// Char ROM - 0x4000 - 0x47FF (0x0400 / 2048 bytes)
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dpram #(11,8, "font.hex") chrom
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(
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.clock_a(clk_sys),
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.address_a(chrom_addr[10:0]),
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.wren_a(1'b0),
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.data_a(),
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.q_a(chrom_data_out),
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.clock_b(clk_sys),
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.address_b(dn_addr[10:0]),
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.wren_b(chrom_wr),
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.data_b(dn_data),
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.q_b()
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);
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// Char RAM - 0x8000 - 0x87FF (0x0800 / 2048 bytes)
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dpram #(11,8) chram
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(
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.clock_a(clk_sys),
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.address_a(cpu_addr[10:0]),
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.wren_a(chram_wr),
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.data_a(cpu_dout),
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.q_a(chram_data_out),
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.clock_b(clk_sys),
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.address_b(chram_addr[10:0]),
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.wren_b(1'b0),
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.data_b(),
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.q_b(chmap_data_out)
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);
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// Char foreground color RAM - 0x8800 - 0x8FFF (0x0800 / 2048 bytes)
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dpram #(11,8) fgcolram
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(
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.clock_a(clk_sys),
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.address_a(cpu_addr[10:0]),
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.wren_a(fgcolram_wr),
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.data_a(cpu_dout),
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.q_a(),
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.clock_b(clk_sys),
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.address_b(chram_addr[10:0]),
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.wren_b(1'b0),
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.data_b(),
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.q_b(fgcolram_data_out)
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);
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// Char background color RAM - 0x9000 - 0x97FF (0x0800 / 2048 bytes)
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dpram #(11,8) bgcolram
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(
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.clock_a(clk_sys),
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.address_a(cpu_addr[10:0]),
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.wren_a(bgcolram_wr),
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.data_a(cpu_dout),
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.q_a(),
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.clock_b(clk_sys),
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.address_b(chram_addr[10:0]),
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.wren_b(1'b0),
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.data_b(),
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.q_b(bgcolram_data_out)
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);
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// Work RAM - 0xC000 - 0xFFFF (0x4000 / 16384 bytes)
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spram #(14,8) wkram
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(
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.clock(clk_sys),
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.address(cpu_addr[13:0]),
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.wren(wkram_wr),
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.data(cpu_dout),
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.q(wkram_data_out)
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);
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endmodule
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