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58 lines
1.1 KiB
Verilog
58 lines
1.1 KiB
Verilog
module dpram #(
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parameter address_width = 10,
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parameter data_width = 8,
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parameter init_file= ""
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) (
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input wire clock_a,
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input wire wren_a,
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input wire [address_width-1:0] address_a,
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input wire [data_width-1:0] data_a,
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output reg [data_width-1:0] q_a,
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input wire clock_b,
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input wire wren_b,
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input wire [address_width-1:0] address_b,
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input wire [data_width-1:0] data_b,
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output reg [data_width-1:0] q_b
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);
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initial begin
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if (init_file>0)
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begin
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$display("Loading rom:");
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$display(init_file);
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$readmemh(init_file, mem);
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end
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end
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localparam ramLength = (2**address_width);
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reg [data_width-1:0] mem [ramLength-1:0];
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// `ifdef SIMULATION
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// integer j;
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// initial
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// begin
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// for (j = 0; j < ramLength; j = j + 1)
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// begin
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// mem[j] = 0;
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// end
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// end
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// `endif
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always @(posedge clock_a) begin
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q_a <= mem[address_a];
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if(wren_a) begin
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q_a <= data_a;
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mem[address_a] <= data_a;
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end
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end
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always @(posedge clock_b) begin
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q_b <= mem[address_b];
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if(wren_b) begin
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q_b <= data_b;
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mem[address_b] <= data_b;
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end
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end
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endmodule |