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43 lines
1.6 KiB
Verilog
43 lines
1.6 KiB
Verilog
/*============================================================================
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Aznable (custom 8-bit computer system) - Linear-feedback shift register
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Author: Jim Gregory - https://github.com/JimmyStones/
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Version: 1.0
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Date: 2021-11-06
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Based on Project F: Ad Astra - Starfield
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(C)2021 Will Green, open source hardware released under the MIT License
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Learn more at https://projectf.io
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>.
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===========================================================================*/
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`timescale 1ps / 1ps
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module lfsr #(
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parameter LEN=8, // shift register length
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parameter TAPS=8'b10111000 // XOR taps
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) (
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input wire clk, // clock
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input wire rst, // reset
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input wire en, // enable
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input wire [LEN-1:0] seed,
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output reg [LEN-1:0] sreg // lfsr output
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);
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always @(posedge clk) begin
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if (en) sreg <= {1'b0, sreg[LEN-1:1]} ^ (sreg[0] ? TAPS : {LEN{1'b0}});
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if (rst) sreg <= seed;
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end
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endmodule |