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41 lines
1.0 KiB
Verilog
41 lines
1.0 KiB
Verilog
`default_nettype none
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module basic6(
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input wire osc,
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input wire [15:0] A,
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output wire [7:0] D,
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input wire memr_n,
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input wire memw_n,
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input wire INIT,
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output wire NDRY_n,
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output wire RAM_n
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);
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wire [7:0] data_EPROM_out;
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wire cs0 = (A[15:11] == 5'b1100_1); // C800
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wire cs1 = (A[15:11] == 5'b1101_0); // D000
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wire cs2 = (A[15:11] == 5'b1101_1); // D800
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wire cs3 = (A[15:11] == 5'b1110_0); // E000
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wire cs_C800 = cs0 | cs1 | cs2 | cs3;
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wire cs = cs_C800 & memw_n & ~memr_n;
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assign NDRY_n = 1'b1;
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assign RAM_n = ~cs; // 0 = request served by basic6 module, 1 = should be served by computer RAM
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assign D = data_EPROM_out;
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wire [1:0] addrePrefix = cs0 ? 2'b00 :
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cs1 ? 2'b01 :
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cs2 ? 2'b10 :
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cs3 ? 2'b11 : 2'b00 ;
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dpram #(.ADDRWIDTH(13), .MEM_INIT_FILE("./rom/Basic6.mif")) myEPPROM
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(
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.clock(osc),
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.address_a({addrePrefix, A[10:0]}),
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.wren_a(0),
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.q_a(data_EPROM_out)
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);
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endmodule //basic6
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