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148 lines
3.5 KiB
Systemverilog
148 lines
3.5 KiB
Systemverilog
//
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// Copyright (c) 2019 Sorgelig
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//
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// All rights reserved
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//
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// Redistribution and use in source and synthezised forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// Redistributions in synthesized form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// Neither the name of the author nor the names of other contributors may
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// be used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Please report bugs to the author, but before you do so, please
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// make sure that this is not a derivative work and that
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// you have the latest version of this file.
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module multitap
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(
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input RESET,
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input CLK,
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input CE,
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input J3BUT,
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input P1_UP, P1_DOWN, P1_LEFT, P1_RIGHT, P1_A, P1_B, P1_C, P1_START, P1_MODE, P1_X, P1_Y, P1_Z,
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input P2_UP, P2_DOWN, P2_LEFT, P2_RIGHT, P2_A, P2_B, P2_C, P2_START, P2_MODE, P2_X, P2_Y, P2_Z,
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input P3_UP, P3_DOWN, P3_LEFT, P3_RIGHT, P3_A, P3_B, P3_C, P3_START, P3_MODE, P3_X, P3_Y, P3_Z,
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input P4_UP, P4_DOWN, P4_LEFT, P4_RIGHT, P4_A, P4_B, P4_C, P4_START, P4_MODE, P4_X, P4_Y, P4_Z,
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input TEAMPLAYER_EN,
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input FOURWAY_EN,
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input [24:0] MOUSE,
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input [2:0] MOUSE_OPT,
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input PAL,
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input EXPORT,
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input SEL,
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input [4:1] A,
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input RNW,
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input [7:0] DI,
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output [7:0] DO,
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output DTACK_N,
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input JCART_SEL,
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output[15:0] JCART_DO,
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output JCART_DTACK_N
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);
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wire [7:0] GEN_DO;
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gen_io io
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(
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.*,
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.DO(GEN_DO)
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);
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wire [7:0] FW_DO;
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fourway fourway
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(
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.*,
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.DO(FW_DO),
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.DTACK_N()
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);
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wire [7:0] TP_DO;
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teamplayer teamplayer
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(
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.*,
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.DO(TP_DO),
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.DTACK_N()
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);
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pad_io jcart_u
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(
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.*,
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.P_UP(P4_UP),
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.P_DOWN(P4_DOWN),
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.P_LEFT(P4_LEFT),
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.P_RIGHT(P4_RIGHT),
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.P_A(P4_A),
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.P_B(P4_B),
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.P_C(P4_C),
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.P_START(P4_START),
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.P_MODE(P4_MODE),
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.P_X(P4_X),
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.P_Y(P4_Y),
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.P_Z(P4_Z),
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.SEL(JCART_SEL),
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.DIR(0),
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.DI(DI[0]),
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.DO(JCART_DO[15:8]),
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.DTACK_N(JCART_DTACK_N)
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);
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pad_io jcart_l
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(
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.*,
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.P_UP(P3_UP),
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.P_DOWN(P3_DOWN),
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.P_LEFT(P3_LEFT),
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.P_RIGHT(P3_RIGHT),
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.P_A(P3_A),
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.P_B(P3_B),
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.P_C(P3_C),
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.P_START(P3_START),
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.P_MODE(P3_MODE),
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.P_X(P3_X),
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.P_Y(P3_Y),
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.P_Z(P3_Z),
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.SEL(JCART_SEL),
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.DIR(0),
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.DI(DI[0]),
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.DO(JCART_DO[7:0]),
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.DTACK_N()
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);
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wire MT_SEL = (A==1 || A==2);
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assign DO = (FOURWAY_EN & MT_SEL) ? FW_DO : (TEAMPLAYER_EN & MT_SEL) ? TP_DO : GEN_DO;
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endmodule
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