diff --git a/Genesis.qsf b/Genesis.qsf index d34753e..0b4fb69 100644 --- a/Genesis.qsf +++ b/Genesis.qsf @@ -49,7 +49,7 @@ set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0 -set_global_assignment -name SEED 1337 +set_global_assignment -name SEED 1 source sys/sys.tcl source sys/sys_analog.tcl diff --git a/Genesis.sv b/Genesis.sv index 628036f..458aeba 100644 --- a/Genesis.sv +++ b/Genesis.sv @@ -433,7 +433,6 @@ system system .ROM_ADDR(rom_addr), .ROM_DATA(use_sdr ? sdrom_data : ddrom_data), .ROM_WDATA(rom_wdata), - .ROM_RD(rom_rd), .ROM_WE(rom_we), .ROM_BE(rom_be), .ROM_REQ(rom_req), @@ -562,7 +561,6 @@ sdram sdram .addr0(ioctl_addr[24:1]), .din0({ioctl_data[7:0],ioctl_data[15:8]}), .dout0(), - .rd0(0), .wrl0(1), .wrh0(1), .req0(rom_wr), @@ -571,7 +569,6 @@ sdram sdram .addr1(rom_addr), .din1(rom_wdata), .dout1(sdrom_data), - .rd1(rom_rd), .wrl1(rom_we & rom_be[0]), .wrh1(rom_we & rom_be[1]), .req1(rom_req), @@ -580,7 +577,6 @@ sdram sdram .addr2(0), .din2(0), .dout2(), - .rd2(0), .wrl2(0), .wrh2(0), .req2(0), @@ -590,13 +586,13 @@ sdram sdram wire [24:1] rom_addr, rom_addr2; wire [15:0] sdrom_data, ddrom_data, rom_data2, rom_wdata; wire [1:0] rom_be; -wire rom_req, rom_rd, sdrom_rdack, ddrom_rdack, rom_rd2, rom_rdack2, rom_we; +wire rom_req, sdrom_rdack, ddrom_rdack, rom_rd2, rom_rdack2, rom_we; assign DDRAM_CLK = clk_ram; ddram ddram ( .*, - .wraddr(ioctl_addr), + .wraddr(ioctl_addr[24:1]), .din({ioctl_data[7:0],ioctl_data[15:8]}), .we_req(rom_wr), .we_ack(ddrom_wrack), @@ -618,7 +614,7 @@ ddram ddram reg use_sdr; always @(posedge clk_sys) use_sdr <= (!status[36:35]) ? |sdram_sz[2:0] : status[35]; -reg rom_wr; +reg rom_wr = 0; wire sdrom_wrack, ddrom_wrack; reg [24:0] rom_sz; always @(posedge clk_sys) begin @@ -627,20 +623,13 @@ always @(posedge clk_sys) begin old_reset <= reset; if(~old_reset && reset) ioctl_wait <= 0; - if (old_download & ~cart_download) begin - rom_sz <= ioctl_addr[24:0]; - ioctl_wait <= 0; - end + if (old_download & ~cart_download) rom_sz <= ioctl_addr[24:0]; - if(~old_download && cart_download) - rom_wr <= 0; - else if (cart_download) begin - if(ioctl_wr) begin - ioctl_wait <= 1; - rom_wr <= ~rom_wr; - end else if(ioctl_wait && (rom_wr == sdrom_wrack) && (rom_wr == ddrom_wrack)) begin - ioctl_wait <= 0; - end + if (cart_download & ioctl_wr) begin + ioctl_wait <= 1; + rom_wr <= ~rom_wr; + end else if(ioctl_wait && (rom_wr == sdrom_wrack) && (rom_wr == ddrom_wrack)) begin + ioctl_wait <= 0; end end diff --git a/ddram.sv b/ddram.sv index bce1ae4..6fc0a19 100644 --- a/ddram.sv +++ b/ddram.sv @@ -1,6 +1,6 @@ // // ddram.v -// Copyright (c) 2017 Sorgelig +// Copyright (c) 2017,2019 Sorgelig // // // This source file is free software: you can redistribute it and/or modify @@ -19,7 +19,7 @@ // ------------------------------------------ // -// 8-bit version +// 16-bit version module ddram ( @@ -35,7 +35,7 @@ module ddram output [7:0] DDRAM_BE, output DDRAM_WE, - input [27:0] wraddr, + input [27:1] wraddr, input [15:0] din, input we_req, output reg we_ack, @@ -55,22 +55,22 @@ module ddram ); assign DDRAM_BURSTCNT = ram_burst; -assign DDRAM_BE = ({6'd0,ram_be}<<{ram_address[2:1],1'b0}) | {8{ram_read}}; -assign DDRAM_ADDR = {4'b0011, ram_address[27:3]}; // RAM at 0x30000000 +assign DDRAM_BE = ram_be | {8{ram_read}}; +assign DDRAM_ADDR = {4'b0011, ram_address}; // RAM at 0x30000000 assign DDRAM_RD = ram_read; assign DDRAM_DIN = ram_data; assign DDRAM_WE = ram_write; -assign dout = (rdaddr[27:1] < wraddr[27:1]) ? ram_q[{rdaddr[2:1], 4'b0000} +:16] : 16'd0; -assign dout2 = (rdaddr2[27:1] < wraddr[27:1]) ? ram_q2[{rdaddr2[2:1], 4'b0000} +:16] : 16'd0; +assign dout = (rdaddr < wraddr) ? ram_q[{rdaddr[2:1], 4'b0000} +:16] : 16'd0; +assign dout2 = (rdaddr2 < wraddr) ? ram_q2[{rdaddr2[2:1], 4'b0000} +:16] : 16'd0; reg [7:0] ram_burst; reg [63:0] ram_q, next_q, ram_q2, next_q2; reg [63:0] ram_data; -reg [27:0] ram_address, cache_addr, cache_addr2; +reg [27:3] ram_address, cache_addr, cache_addr2; reg ram_read = 0; reg ram_write = 0; -reg [1:0] ram_be = 0; +reg [7:0] ram_be = 0; reg [1:0] state = 0; reg ch = 0; @@ -83,9 +83,9 @@ always @(posedge DDRAM_CLK) begin case(state) 0: if(we_ack != we_req) begin - ram_be <= 3; + ram_be <= 8'd3<<{wraddr[2:1],1'b0}; ram_data <= {4{din}}; - ram_address <= wraddr; + ram_address <= wraddr[27:3]; ram_write <= 1; ram_burst <= 1; ch <= 1; @@ -93,28 +93,28 @@ always @(posedge DDRAM_CLK) begin end else if(rom_req != rom_ack) begin if(rom_we) begin - ram_be <= rom_be; + ram_be <= {6'd0,rom_be}<<{rdaddr[2:1],1'b0}; ram_data <= {4{rom_din}}; - ram_address <= {rdaddr[27:1],1'b0}; + ram_address <= rdaddr[27:3]; ram_write <= 1; ram_burst <= 1; ch <= 0; state <= 1; end - else if(cache_addr[27:3] == rdaddr[27:3]) rom_ack <= rom_req; - else if((cache_addr[27:3]+1'd1) == rdaddr[27:3]) begin + else if(cache_addr == rdaddr[27:3]) rom_ack <= rom_req; + else if((cache_addr+1'd1) == rdaddr[27:3]) begin rom_ack <= rom_req; ram_q <= next_q; - cache_addr <= {rdaddr[27:3],3'b000}; - ram_address <= {rdaddr[27:3]+1'd1,3'b000}; + cache_addr <= rdaddr[27:3]; + ram_address <= rdaddr[27:3]+1'd1; ram_read <= 1; ram_burst <= 1; ch <= 0; state <= 3; end else begin - ram_address <= {rdaddr[27:3],3'b000}; - cache_addr <= {rdaddr[27:3],3'b000}; + ram_address <= rdaddr[27:3]; + cache_addr <= rdaddr[27:3]; ram_read <= 1; ram_burst <= 2; ch <= 0; @@ -122,20 +122,20 @@ always @(posedge DDRAM_CLK) begin end end else if(rd_req2 != rd_ack2) begin - if(cache_addr2[27:3] == rdaddr2[27:3]) rd_ack2 <= rd_req2; - else if((cache_addr2[27:3]+1'd1) == rdaddr2[27:3]) begin + if(cache_addr2 == rdaddr2[27:3]) rd_ack2 <= rd_req2; + else if((cache_addr2+1'd1) == rdaddr2[27:3]) begin rd_ack2 <= rd_req2; ram_q2 <= next_q2; - cache_addr2 <= {rdaddr2[27:3],3'b000}; - ram_address <= {rdaddr2[27:3]+1'd1,3'b000}; + cache_addr2 <= rdaddr2[27:3]; + ram_address <= rdaddr2[27:3]+1'd1; ram_read <= 1; ram_burst <= 1; ch <= 1; state <= 3; end else begin - ram_address <= {rdaddr2[27:3],3'b000}; - cache_addr2 <= {rdaddr2[27:3],3'b000}; + ram_address <= rdaddr2[27:3]; + cache_addr2 <= rdaddr2[27:3]; ram_read <= 1; ram_burst <= 2; ch <= 1; @@ -144,10 +144,10 @@ always @(posedge DDRAM_CLK) begin end 1: begin - cache_addr <= '1; - cache_addr2 <= '1; - cache_addr[3:0] <= 0; - cache_addr2[3:0] <= 0; + cache_addr <= '1; + cache_addr2 <= '1; + cache_addr[3] <= 0; + cache_addr2[3] <= 0; if(ch) we_ack <= we_req; else rom_ack <= rom_req; state <= 0; diff --git a/jt12/jt12_kon.v b/jt12/jt12_kon.v index 6b0d608..d867cf6 100644 --- a/jt12/jt12_kon.v +++ b/jt12/jt12_kon.v @@ -61,14 +61,29 @@ if(num_ch==6) begin always @(posedge clk) if( clk_en ) keyon_I <= (csm&&next_ch==3'd2&&overflow2) || csr_out; - wire key_upnow = up_keyon && (keyon_ch==next_ch) && (next_op == 2'd3); + reg up_keyon_reg; + reg [3:0] tkeyon_op; + reg [2:0] tkeyon_ch; + always @(posedge clk) if( clk_en ) begin + if (rst) + up_keyon_reg <= 1'b0; + if (up_keyon) begin + up_keyon_reg <= 1'b1; + tkeyon_op <= keyon_op; + tkeyon_ch <= keyon_ch; end + else if (key_upnow) + up_keyon_reg <= 1'b0; + end + + wire key_upnow = up_keyon_reg && (tkeyon_ch==next_ch) && (next_op == 2'd3); + wire middle1; wire middle2; wire middle3; - wire din = key_upnow ? keyon_op[3] : csr_out; - wire mid_din2 = key_upnow ? keyon_op[1] : middle1; - wire mid_din3 = key_upnow ? keyon_op[2] : middle2; - wire mid_din4 = key_upnow ? keyon_op[0] : middle3; + wire din = key_upnow ? tkeyon_op[3] : csr_out; + wire mid_din2 = key_upnow ? tkeyon_op[1] : middle1; + wire mid_din3 = key_upnow ? tkeyon_op[2] : middle2; + wire mid_din4 = key_upnow ? tkeyon_op[0] : middle3; jt12_sh_rst #(.width(1),.stages(6),.rstval(1'b0)) u_konch0( .clk ( clk ), diff --git a/releases/Genesis_20200105.rbf b/releases/Genesis_20200105.rbf new file mode 100644 index 0000000..ba816f3 Binary files /dev/null and b/releases/Genesis_20200105.rbf differ diff --git a/sdram.sv b/sdram.sv index 0faee3f..e9b3a97 100644 --- a/sdram.sv +++ b/sdram.sv @@ -39,7 +39,6 @@ module sdram input clk, // sdram is accessed at up to 128MHz input [24:1] addr0, - input rd0, input wrl0, input wrh0, input [15:0] din0, @@ -48,7 +47,6 @@ module sdram output reg ack0, input [24:1] addr1, - input rd1, input wrl1, input wrh1, input [15:0] din1, @@ -57,7 +55,6 @@ module sdram output reg ack1, input [24:1] addr2, - input rd2, input wrl2, input wrh2, input [15:0] din2, @@ -94,7 +91,6 @@ reg [1:0] dqm; reg active = 0; reg [2:0] ram_req = 0; wire [2:0] wr = {wrl2|wrh2,wrl1|wrh1,wrl0|wrh0}; -wire [2:0] rd = {rd2,rd1,rd0}; reg [15:0] dout; @@ -106,22 +102,21 @@ assign dout2 = dout; // access manager always @(posedge clk) begin - reg [2:0] old_rd, old_wr; reg [9:0] rfs_cnt; - reg rfs; + reg rfs, rfs2; rfs_cnt <= rfs_cnt + 1'd1; if (rfs_cnt == 850) begin rfs <= 1; rfs_cnt <= 0; end - - old_rd <= old_rd & rd; - old_wr <= old_wr & wr; + + if (rfs_cnt == 425) rfs2 <= 1; if(state == STATE_IDLE && mode == MODE_NORMAL) begin if (rfs) begin rfs <= 0; + rfs2 <= 0; rfs_cnt <= 0; we <= 0; dqm <= 2'b00; @@ -129,40 +124,34 @@ always @(posedge clk) begin state <= STATE_START; end else if (ack0 != req0) begin - old_rd[0] <= rd[0]; - old_wr[0] <= wr[0]; {ba,a} <= addr0; data <= din0; we <= wr[0]; dqm <= wr[0] ? ~{wrh0,wrl0} : 2'b00; active <= 1; - state <= STATE_START; ram_req[0] <= 1; - rfs <= rd[0]; + rfs <= rfs2; + state <= STATE_START; end else if (ack1 != req1) begin - old_rd[1] <= rd[1]; - old_wr[1] <= wr[1]; {ba,a} <= addr1; data <= din1; we <= wr[1]; dqm <= wr[1] ? ~{wrh1,wrl1} : 2'b00; active <= 1; - state <= STATE_START; ram_req[1] <= 1; - rfs <= rd[1]; + rfs <= rfs2; + state <= STATE_START; end else if (ack2 != req2) begin - old_rd[2] <= rd[2]; - old_wr[2] <= wr[2]; {ba,a} <= addr2; data <= din2; we <= wr[2]; dqm <= wr[2] ? ~{wrh2,wrl2} : 2'b00; active <= 1; - state <= STATE_START; ram_req[2] <= 1; - rfs <= rd[2]; + rfs <= rfs2; + state <= STATE_START; end end diff --git a/sys/hps_io.v b/sys/hps_io.v index acef6b4..f70929f 100644 --- a/sys/hps_io.v +++ b/sys/hps_io.v @@ -58,6 +58,9 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0) input status_set, input [15:0] status_menumask, + input info_req, + input [7:0] info, + //toggle to force notify of video mode change input new_vmode, @@ -220,6 +223,8 @@ always@(posedge clk_sys) begin reg old_status_set = 0; reg [7:0] cd_req = 0; reg old_cd = 0; + reg old_info = 0; + reg [7:0] info_n = 0; old_status_set <= status_set; if(~old_status_set & status_set) begin @@ -227,6 +232,9 @@ always@(posedge clk_sys) begin status_req <= status_in; end + old_info <= info_req; + if(~old_info & info_req) info_n <= info; + old_cd <= cd_in[48]; if(old_cd ^ cd_in[48]) cd_req <= cd_req + 1'd1; @@ -273,6 +281,7 @@ always@(posedge clk_sys) begin 'h2F: io_dout <= 1; 'h32: io_dout <= gamma_bus[21]; 'h34: io_dout <= cd_req; + 'h36: begin io_dout <= info_n; info_n <= 0; end endcase sd_buff_addr <= 0; diff --git a/sys/sys_top.v b/sys/sys_top.v index 6997370..b13e287 100644 --- a/sys/sys_top.v +++ b/sys/sys_top.v @@ -266,6 +266,7 @@ reg [15:0] cfg; reg cfg_got = 0; reg cfg_set = 0; +wire vga_fb = cfg[12]; wire [1:0] hdmi_limited = {cfg[11],cfg[8]}; wire direct_video = cfg[10]; wire dvi_mode = cfg[7]; @@ -835,6 +836,9 @@ osd hdmi_osd .osd_status(osd_status) ); +wire hdmi_cs_osd; +csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd); + reg [23:0] dv_data; reg dv_hs, dv_vs, dv_de; always @(posedge clk_vid) begin @@ -879,7 +883,7 @@ end wire hdmi_tx_clk; cyclonev_clkselect hdmi_clk_sw ( - .clkselect({1'b1, direct_video}), + .clkselect({1'b1, ~vga_fb & direct_video}), .inclk({clk_vid, hdmi_clk_out, 2'b00}), .outclk(hdmi_tx_clk) ); @@ -918,10 +922,10 @@ always @(posedge hdmi_tx_clk) begin reg hs,vs,de; reg [23:0] d; - hs <= direct_video ? dv_hs : hdmi_hs_osd; - vs <= direct_video ? dv_vs : hdmi_vs_osd; - de <= direct_video ? dv_de : hdmi_de_osd; - d <= direct_video ? dv_data : hdmi_data_osd; + hs <= (~vga_fb & direct_video) ? dv_hs : (direct_video & csync_en) ? hdmi_cs_osd : hdmi_hs_osd; + vs <= (~vga_fb & direct_video) ? dv_vs : hdmi_vs_osd; + de <= (~vga_fb & direct_video) ? dv_de : hdmi_de_osd; + d <= (~vga_fb & direct_video) ? dv_data : hdmi_data_osd; hdmi_out_hs <= hs; hdmi_out_vs <= vs; @@ -985,15 +989,12 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd); .ypbpr_full(0), .ypbpr_en(ypbpr_en), .dout(vga_o), - .din(vga_scaler ? {24{hdmi_de_osd}} & hdmi_data_osd : vga_data_osd) + .din((vga_fb | vga_scaler) ? {24{hdmi_de_osd}} & hdmi_data_osd : vga_data_osd) ); - wire hdmi_cs_osd; - csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd); - - wire vs1 = vga_scaler ? hdmi_vs_osd : vga_vs_osd; - wire hs1 = vga_scaler ? hdmi_hs_osd : vga_hs_osd; - wire cs1 = vga_scaler ? hdmi_cs_osd : vga_cs_osd; + wire vs1 = (vga_fb | vga_scaler) ? hdmi_vs_osd : vga_vs_osd; + wire hs1 = (vga_fb | vga_scaler) ? hdmi_hs_osd : vga_hs_osd; + wire cs1 = (vga_fb | vga_scaler) ? hdmi_cs_osd : vga_cs_osd; assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ : csync_en ? 1'b1 : ~vs1; assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ : csync_en ? ~cs1 : ~hs1; diff --git a/system.sv b/system.sv index 71abeee..2952aab 100644 --- a/system.sv +++ b/system.sv @@ -97,7 +97,6 @@ module system output [24:1] ROM_ADDR, input [15:0] ROM_DATA, output [15:0] ROM_WDATA, - output reg ROM_RD, output reg ROM_WE, output [1:0] ROM_BE, output reg ROM_REQ, @@ -110,10 +109,7 @@ module system input EN_HIFI_PCM, input LADDER, - input OBJ_LIMIT_HIGH, - - output [23:0] DBG_M68K_A, - output [23:0] DBG_MBUS_A + input OBJ_LIMIT_HIGH ); reg reset; @@ -561,10 +557,6 @@ end assign ROM_BE = ~{MBUS_UDS_N, MBUS_LDS_N}; assign ROM_WDATA = MBUS_DO; -assign DBG_MBUS_A = {MBUS_A,1'b0}; -assign DBG_M68K_A = {M68K_A,1'b0}; - - //----------------------------------------------------------------------- // 64KB SRAM / 128KB SVP DRAM //----------------------------------------------------------------------- @@ -825,7 +817,7 @@ always @(posedge MCLK) begin MBUS_DO <= {Z80_DO,Z80_DO}; MBUS_RNW <= Z80_WR_N; mstate <= MBUS_Z80_PREREAD; - cycle_cnt = 2'd1; + cycle_cnt <= 2'd1; end end @@ -833,7 +825,7 @@ always @(posedge MCLK) begin begin if (!cycle_cnt) begin mstate <= MBUS_SELECT; - cycle_cnt = 2'd1; + cycle_cnt <= 2'd1; end end @@ -878,7 +870,6 @@ always @(posedge MCLK) begin else if (MBUS_A < ROMSZ) begin if (PIER_QUIRK) BANK_MODE <= (MBUS_A >= 23'h140000) ? 3'h3 : 3'h0; if (SVP_QUIRK && msrc == MSRC_VDP) MBUS_A <= MBUS_A - 1'd1; - ROM_RD <= 1; ROM_WE <= 0; ROM_REQ <= ~ROM_ACK; mstate <= MBUS_ROM_READ; @@ -1031,7 +1022,6 @@ always @(posedge MCLK) begin if (ROM_REQ == ROM_ACK) begin data <= ROM_DATA; if(msrc == MSRC_M68K) NO_DATA <= ROM_DATA; - ROM_RD <= 0; if (msrc != MSRC_Z80 || !cycle_cnt) mstate <= MBUS_FINISH; end