diff --git a/Genesis.srf b/Genesis.srf
index 5325561..65660ca 100644
--- a/Genesis.srf
+++ b/Genesis.srf
@@ -15,6 +15,10 @@
 { "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "Inferred RAM node \"emu:emu\|Genesis:Genesis\|vdp:vdp\|FIFO_ADDR_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "Inferred RAM node \"emu:emu\|Genesis:Genesis\|vdp:vdp\|FIFO_DATA_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Net \"vip:vip\|vip_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Net \"vip:vip\|vip_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Inferred RAM node \"emu:emu\|Genesis:Genesis\|TG68KdotC_Kernel:tg68\|regfile_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Inferred RAM node \"emu:emu\|Genesis:Genesis\|TG68KdotC_Kernel:tg68\|regfile_rtl_1\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "Vip.vip: Module dependency loop involving: \"HPS\"" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "alt_vip_cvo_mode_banks.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
@@ -29,3 +33,4 @@
 { "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}