diff --git a/sys/build_id.tcl b/sys/build_id.tcl index 3705e4c..b43b9d9 100644 --- a/sys/build_id.tcl +++ b/sys/build_id.tcl @@ -1,25 +1,29 @@ # Build TimeStamp Verilog Module # Jeff Wiencrot - 8/1/2011 +# Sorgelig - 02/11/2019 proc generateBuildID_Verilog {} { # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) - set buildDate [ clock format [ clock seconds ] -format %y%m%d ] - set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + set buildDate "`define BUILD_DATE \"[clock format [ clock seconds ] -format %y%m%d]\"" # Create a Verilog file for output set outputFileName "build_id.v" - set outputFile [open $outputFileName "w"] + + set fileData "" + if { [file exists $outputFileName]} { + set outputFile [open $outputFileName "r"] + set fileData [read $outputFile] + close $outputFile + } - # Output the Verilog source - puts $outputFile "`define BUILD_DATE \"$buildDate\"" - puts $outputFile "`define BUILD_TIME \"$buildTime\"" - close $outputFile - - # Send confirmation message to the Messages window - post_message "Generated build identification Verilog module: [pwd]/$outputFileName" - post_message "Date: $buildDate" - post_message "Time: $buildTime" + if {$buildDate ne $fileData} { + set outputFile [open $outputFileName "w"] + puts -nonewline $outputFile $buildDate + close $outputFile + # Send confirmation message to the Messages window + post_message "Generated: [pwd]/$outputFileName: $buildDate" + } } # Build CDF file diff --git a/sys/hq2x.sv b/sys/hq2x.sv index 9f539f9..f5fcc71 100644 --- a/sys/hq2x.sv +++ b/sys/hq2x.sv @@ -8,9 +8,7 @@ // //////////////////////////////////////////////////////////////////////////////////////////////////////// -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on +// altera message_off 10030 module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) ( @@ -34,24 +32,29 @@ localparam AWIDTH = $clog2(LENGTH)-1; localparam DWIDTH = HALF_DEPTH ? 11 : 23; localparam DWIDTH1 = DWIDTH+1; -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; +(* romstyle = "MLAB" *) reg [5:0] hqTable[256]; +initial begin + hqTable = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 + }; +end + +wire [5:0] hqrule = hqTable[nextpatt]; reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2; reg [23:0] A, B, D, F, G, H; @@ -70,7 +73,7 @@ wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; wire [23:0] X = (cyc == 0) ? A : (cyc == 1) ? Prev1 : (cyc == 2) ? Next1 : G; wire [23:0] blend_result_pre; -Blend blender(clk, ce_in, hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result_pre); +Blend blender(clk, ce_in, disable_hq2x ? 6'd0 : hqrule, Curr0, X, B, D, F, H, blend_result_pre); wire [DWIDTH:0] Curr20tmp; wire [23:0] Curr20 = HALF_DEPTH ? h2rgb(Curr20tmp) : Curr20tmp; @@ -146,13 +149,28 @@ reg [AWIDTH:0] offs; always @(posedge clk) begin reg old_reset_line; reg old_reset_frame; - reg wrdata_finished; + reg [3:0] wrdata_finished; + reg [AWIDTH+1:0] waddr; wrout_en <= 0; wrin_en <= 0; if(ce_in) begin + // blend_result has been delayed by 4 cycles + case(cyc) + 0: wrdata[DWIDTH:0] <= blend_result; + 1: wrdata[DWIDTH1+DWIDTH:DWIDTH1] <= blend_result; + 2: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result; + 3: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result; + endcase + + wrdata_finished <= wrdata_finished << 1; + if(wrdata_finished[3]) begin + wrout_en <= 1; + wrout_addr <= waddr; + end + if(~&offs) begin if (cyc == 1) begin Prev2 <= Curr20; @@ -163,32 +181,10 @@ always @(posedge clk) begin wrin_en <= 1; end - /* - case(cyc) - 0: wrdata[DWIDTH:0] <= blend_result; - 1: wrdata[DWIDTH1+DWIDTH:DWIDTH1] <= blend_result; - 2: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result; - 3: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result; - endcase - */ - - // blend_result has been delayed by 1 cycle - case(cyc) - 1: wrdata[DWIDTH:0] <= blend_result; - 2: wrdata[DWIDTH1+DWIDTH:DWIDTH1] <= blend_result; - 3: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result; - 0: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result; - endcase - if(cyc==3) begin offs <= offs + 1'd1; - wrout_addr <= {offs, curbuf}; - wrdata_finished <= 1; - end - - if(wrdata_finished) begin - wrout_en <= 1; - wrdata_finished <= 0; + waddr <= {offs, curbuf}; + wrdata_finished[0] <= 1; end end @@ -241,26 +237,27 @@ module hq2x_in #(parameter LENGTH, parameter DWIDTH) input wren ); - localparam AWIDTH = $clog2(LENGTH)-1; - wire [DWIDTH:0] out[2]; - assign q0 = out[rdbuf0]; - assign q1 = out[rdbuf1]; +localparam AWIDTH = $clog2(LENGTH)-1; +wire [DWIDTH:0] out[2]; +assign q0 = out[rdbuf0]; +assign q1 = out[rdbuf1]; + +hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); +hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); endmodule module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) ( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output logic [DWIDTH:0] q + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output reg [DWIDTH:0] q ); -logic [DWIDTH:0] ram[0:NUMWORDS-1]; +reg [DWIDTH:0] ram[0:NUMWORDS-1]; always_ff@(posedge clock) begin if(wren) ram[wraddress] <= data; @@ -275,15 +272,14 @@ module DiffCheck ( input [23:0] rgb1, input [23:0] rgb2, - output result + output result ); wire [7:0] r = rgb1[7:1] - rgb2[7:1]; wire [7:0] g = rgb1[15:9] - rgb2[15:9]; wire [7:0] b = rgb1[23:17] - rgb2[23:17]; wire [8:0] t = $signed(r) + $signed(b); - wire [8:0] gx = {g[7], g}; - wire [9:0] y = $signed(t) + $signed(gx); + wire [9:0] y = $signed(t) + $signed({g[7], g}); wire [8:0] u = $signed(r) - $signed(b); wire [9:0] v = $signed({g, 1'b0}) - $signed(t); @@ -291,56 +287,19 @@ module DiffCheck wire y_inside = (y < 10'h60 || y >= 10'h3a0); // if u is inside (-16, 16) - wire u_inside = (u < 9'h10 || u >= 9'h1f0); + wire u_inside = (!u[8:4] || &u[8:4]); //(u < 9'h10 || u >= 9'h1f0); // if v is inside (-24, 24) wire v_inside = (v < 10'h18 || v >= 10'h3e8); assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input clk, - input clk_en, - input [8:0] Op, - input [7:0] A, - input [7:0] B, - input [7:0] C, - output reg [7:0] O -); - - function [10:0] mul8x3; - input [7:0] op1; - input [2:0] op2; - begin - mul8x3 = 11'd0; - if(op2[0]) mul8x3 = mul8x3 + op1; - if(op2[1]) mul8x3 = mul8x3 + {op1, 1'b0}; - if(op2[2]) mul8x3 = mul8x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [10:0] Amul = mul8x3(A, Op[7:5]); - wire [10:0] Bmul = mul8x3(B, {Op[3:2], 1'b0}); - wire [10:0] Cmul = mul8x3(C, {Op[1:0], 1'b0}); - wire [10:0] At = Amul; - wire [10:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [10:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [11:0] Res = {At, 1'b0} + Bt + Ct; - - always @(posedge clk) if (clk_en) begin - O <= Op[8] ? A : Res[11:4]; - end endmodule module Blend ( - input clk, - input clk_en, + input clk, + input clk_en, input [5:0] rule, - input disable_hq2x, input [23:0] E, input [23:0] A, input [23:0] B, @@ -350,66 +309,63 @@ module Blend output [23:0] Result ); - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + localparam BLEND1 = 7'b110_10_00; // (A * 12 + B * 4 ) >> 4 + localparam BLEND2 = 7'b100_10_10; // (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 7'b101_10_01; // (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 7'b110_01_01; // (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 7'b010_11_11; // (A * 4 + B * 6 + C * 6) >> 4 + localparam BLEND6 = 7'b111_00_00; // (A * 14 + B * 1 + C * 1) >> 4 - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = {11{1'bx}}; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; + reg [23:0] a,b,d,e,h,f; + reg [3:0] bl_rule; + reg [1:0] df_rule; + always @(posedge clk) if (clk_en) begin + {bl_rule,df_rule} <= rule; + a <= A; b <= B; d <= D; e <= E; f <= F; h <= H; end - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [23:0] Input1 = E; - wire [23:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; + wire is_diff; + DiffCheck diff_checker(df_rule[1] ? b : h, df_rule[0] ? d : f, is_diff); + + reg [23:0] i10,i20,i30; + reg [6:0] op0; + always @(posedge clk) if (clk_en) begin + i10 <= e; + case({!is_diff, bl_rule}) + 1,11,12,13,17: {op0, i20, i30} <= {BLEND1, a, 24'd0}; + 2,14,18: {op0, i20, i30} <= {BLEND1, d, 24'd0}; + 3,15,19: {op0, i20, i30} <= {BLEND1, b, 24'd0}; + 4,20,24,27: {op0, i20, i30} <= {BLEND2, d, b}; + 5,21: {op0, i20, i30} <= {BLEND2, a, b}; + 6,22: {op0, i20, i30} <= {BLEND2, a, d}; + 25,29: {op0, i20, i30} <= {BLEND5, d, b}; + 26: {op0, i20, i30} <= {BLEND6, d, b}; + 28: {op0, i20, i30} <= {BLEND4, d, b}; + 30: {op0, i20, i30} <= {BLEND3, b, d}; + 31: {op0, i20, i30} <= {BLEND3, d, b}; + default: {op0, i20, i30} <= {BLEND1, e, 24'd0}; + endcase + end + + reg [23:0] i1,i2,i3; + reg [6:0] op; + always @(posedge clk) if (clk_en) begin + op <= op0; i1 <= i10; i2 <= i20; i3 <= i30; + end + + function [34:0] mul24x3; + input [23:0] op1; + input [2:0] op2; + begin + mul24x3 = 0; + if(op2[0]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0]}; + if(op2[1]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 1'b0}; + if(op2[2]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 2'b00}; + end + endfunction + + wire [35:0] res = {mul24x3(i1, op[6:4]), 1'b0} + mul24x3(i2, {op[3:2], !op[3:2]}) + mul24x3(i3, {op[1:0], !op[3:2]}); + + always @(posedge clk) if (clk_en) Result <= {res[35:28],res[23:16],res[11:4]}; - wire [23:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(clk, clk_en, op, Input1[7:0], Input2[7:0], Input3[7:0], Result[7:0]); - InnerBlend inner_blend2(clk, clk_en, op, Input1[15:8], Input2[15:8], Input3[15:8], Result[15:8]); - InnerBlend inner_blend3(clk, clk_en, op, Input1[23:16], Input2[23:16], Input3[23:16], Result[23:16]); endmodule diff --git a/sys/osd.v b/sys/osd.v index ea239cb..eee77d8 100644 --- a/sys/osd.v +++ b/sys/osd.v @@ -100,7 +100,7 @@ always@(posedge clk_sys) begin end (* direct_enable *) reg ce_pix; -always @(negedge clk_video) begin +always @(posedge clk_video) begin reg [21:0] cnt = 0; reg [21:0] pixsz, pixcnt; reg deD; diff --git a/sys/scandoubler.v b/sys/scandoubler.v index 44ed1d0..a1d5a44 100644 --- a/sys/scandoubler.v +++ b/sys/scandoubler.v @@ -59,7 +59,7 @@ wire [7:0] pc_in = pix_in_cnt + 1'b1; reg [7:0] pixsz, pixsz2, pixsz4 = 0; reg ce_x4i, ce_x1i; -always @(negedge clk_vid) begin +always @(posedge clk_vid) begin reg old_ce, valid, hs; if(~&pix_len) pix_len <= pl; @@ -124,7 +124,7 @@ reg [7:0] pix_out_cnt = 0; wire [7:0] pc_out = pix_out_cnt + 1'b1; reg ce_x4o, ce_x2o; -always @(negedge clk_vid) begin +always @(posedge clk_vid) begin reg hs; if(~&pix_out_cnt) pix_out_cnt <= pc_out; diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc index 7763fc8..1f62a9d 100644 --- a/sys/sys_top.sdc +++ b/sys/sys_top.sdc @@ -22,9 +22,6 @@ set_clock_groups -exclusive \ -group [get_clocks { FPGA_CLK2_50 }] \ -group [get_clocks { FPGA_CLK3_50 }] -set_output_delay -max -clock HDMI_CLK 4.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}] -set_output_delay -min -clock HDMI_CLK 3.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}] - set_false_path -from [get_ports {KEY*}] set_false_path -from [get_ports {BTN_*}] set_false_path -to [get_ports {LED_*}] @@ -34,6 +31,7 @@ set_false_path -to [get_ports {AUDIO_L}] set_false_path -to [get_ports {AUDIO_R}] set_false_path -to {cfg[*]} set_false_path -from {cfg[*]} +set_false_path -from {VSET[*]} set_false_path -to {wcalc[*] hcalc[*]} set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2 diff --git a/sys/sys_top.v b/sys/sys_top.v index d1572ed..a38e236 100644 --- a/sys/sys_top.v +++ b/sys/sys_top.v @@ -444,7 +444,7 @@ always @(posedge FPGA_CLK2_50) begin end wire clk_100m; -wire clk_hdmi = ~hdmi_clk_out; // Internal HDMI clock, inverted in relation to external clock +wire clk_hdmi = hdmi_clk_out; wire clk_audio = FPGA_CLK3_50; wire clk_pal = FPGA_CLK3_50; @@ -837,7 +837,7 @@ osd hdmi_osd reg [23:0] dv_data; reg dv_hs, dv_vs, dv_de; -always @(negedge clk_vid) begin +always @(posedge clk_vid) begin reg [23:0] dv_d1, dv_d2; reg dv_de1, dv_de2, dv_hs1, dv_hs2, dv_vs1, dv_vs2; reg [12:0] vsz, vcnt;