mirror of
https://github.com/MiSTer-devel/Gameboy_MiSTer.git
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432 lines
12 KiB
Systemverilog
432 lines
12 KiB
Systemverilog
//============================================================================
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// Gameboy
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// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
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//
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// Port to MiSTer
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// Copyright (C) 2017,2018 Sorgelig
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [44:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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output [7:0] VIDEO_ARX,
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output [7:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status OR'd with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
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input TAPE_IN,
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// SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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input SD_CD,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE
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);
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assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign LED_USER = ioctl_download;
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign VIDEO_ARX = status[3] ? 8'd16 : 8'd4;
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assign VIDEO_ARY = status[3] ? 8'd9 : 8'd3;
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assign AUDIO_MIX = status[8:7];
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`include "build_id.v"
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localparam CONF_STR = {
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"GAMEBOY;;",
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"-;",
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"F,GB;",
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"-;",
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"O1,LCD tint,White,Yellow;",
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"O4,Inverted,No,Yes;",
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"O3,Aspect ratio,4:3,16:9;",
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"O78,Stereo mix,none,25%,50%,100%;",
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"-;",
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"O2,Boot,Normal,Fast;",
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"-;",
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"R6,Reset;",
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"J1,A,B,Select,Start;",
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"V,v1.01.",`BUILD_DATE
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};
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//////////////////// CLOCKS ///////////////////
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wire clk_sys;
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wire pll_locked;
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pll pll
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(
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.refclk(CLK_50M),
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.rst(0),
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.outclk_0(clk_sys),
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.outclk_1(SDRAM_CLK),
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.locked(pll_locked)
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);
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///////////////////////////////////////////////////
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wire [31:0] status;
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wire [1:0] buttons;
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wire ioctl_download;
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wire ioctl_wr;
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wire [24:0] ioctl_addr;
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wire [15:0] ioctl_dout;
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reg ioctl_wait;
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wire [15:0] joystick_0, joystick_1;
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wire [15:0] joystick = joystick_0 | joystick_1;
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hps_io #(.STRLEN($size(CONF_STR)>>3), .WIDE(1)) hps_io
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(
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.clk_sys(clk_sys),
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.HPS_BUS(HPS_BUS),
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.conf_str(CONF_STR),
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.ioctl_download(ioctl_download),
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.ioctl_wr(ioctl_wr),
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.ioctl_addr(ioctl_addr),
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.ioctl_dout(ioctl_dout),
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.ioctl_wait(ioctl_wait),
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.buttons(buttons),
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.status(status),
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.joystick_0(joystick_0),
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.joystick_1(joystick_1)
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);
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///////////////////////////////////////////////////
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// TODO: ds for cart ram write
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wire [1:0] sdram_ds = ioctl_download ? 2'b11 : {cart_addr[0], ~cart_addr[0]};
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wire [15:0] sdram_do;
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wire [15:0] sdram_di = ioctl_download ? ioctl_dout : {cart_di, cart_di};
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wire [23:0] sdram_addr = ioctl_download? ioctl_addr[24:1]: {3'b000, mbc_bank, cart_addr[12:1]};
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wire sdram_oe = ~ioctl_download & cart_rd;
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wire sdram_we = ioctl_download ? dn_write : cart_ram_wr;
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assign SDRAM_CKE = 1;
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sdram sdram (
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// interface to the MT48LC16M16 chip
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.sd_data ( SDRAM_DQ ),
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.sd_addr ( SDRAM_A ),
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.sd_dqm ( {SDRAM_DQMH, SDRAM_DQML} ),
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.sd_cs ( SDRAM_nCS ),
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.sd_ba ( SDRAM_BA ),
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.sd_we ( SDRAM_nWE ),
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.sd_ras ( SDRAM_nRAS ),
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.sd_cas ( SDRAM_nCAS ),
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// system interface
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.clk ( clk_sys ),
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.sync ( ce_cpu ),
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.init ( ~pll_locked ),
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// cpu interface
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.din ( sdram_di ),
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.addr ( sdram_addr ),
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.ds ( sdram_ds ),
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.we ( sdram_we ),
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.oe ( sdram_oe ),
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.dout ( sdram_do )
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);
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reg cart_ready = 0;
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reg dn_write;
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always @(posedge clk_sys) begin
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if(ioctl_wr) ioctl_wait <= 1;
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if(ce_cpu) begin
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dn_write <= ioctl_wait;
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if(dn_write) {ioctl_wait, dn_write} <= 0;
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if(dn_write) cart_ready <= 1;
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end
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end
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///////////////////////////////////////////////////
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// TODO: RAM bank
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// http://fms.komkon.org/GameBoy/Tech/Carts.html
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// 32MB SDRAM memory map using word addresses
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// 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 D
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// 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 S
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// -------------------------------------------------
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// 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X up to 2MB used as ROM
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// 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X up to 2MB used as RAM
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// 0 0 0 0 R R B B B B B C C C C C C C C C C C C C C MBC1 ROM (R=RAM bank in mode 0)
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// 0 0 0 1 0 0 0 0 0 0 R R C C C C C C C C C C C C C MBC1 RAM (R=RAM bank in mode 1)
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// ---------------------------------------------------------------
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// ----------------------------- MBC1 ----------------------------
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// ---------------------------------------------------------------
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wire [8:0] mbc1_addr =
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(cart_addr[15:14] == 2'b00)?{8'b000000000, cart_addr[13]}: // 16k ROM Bank 0
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(cart_addr[15:14] == 2'b01)?{1'b0, mbc1_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-127
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(cart_addr[15:13] == 3'b101)?{7'b1000000, mbc1_ram_bank}: // 8k RAM Bank 0-3
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9'd0;
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// -------------------------- RAM banking ------------------------
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// in mode 0 (16/8 mode) the ram is not banked
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// in mode 1 (4/32 mode) four ram banks are used
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wire [1:0] mbc1_ram_bank = (mbc1_mode?mbc1_ram_bank_reg:2'b00) & ram_mask;
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// -------------------------- ROM banking ------------------------
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// in mode 0 (16/8 mode) the ram bank select signals are the upper rom address lines
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// in mode 1 (4/32 mode) the upper two rom address lines are 2'b00
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wire [6:0] mbc1_rom_bank_mode = { mbc1_mode?2'b00:mbc1_ram_bank_reg, mbc1_rom_bank_reg};
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// mask address lines to enable proper mirroring
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wire [6:0] mbc1_rom_bank = mbc1_rom_bank_mode & rom_mask;
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// --------------------- CPU register interface ------------------
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reg mbc1_ram_enable;
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reg mbc1_mode;
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reg [4:0] mbc1_rom_bank_reg;
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reg [1:0] mbc1_ram_bank_reg;
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always @(posedge clk_sys) begin
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if(reset) begin
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mbc1_rom_bank_reg <= 5'd1;
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mbc1_ram_bank_reg <= 2'd0;
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mbc1_ram_enable <= 1'b0;
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mbc1_mode <= 1'b0;
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end else if(ce_cpu) begin
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if(cart_wr && (cart_addr[15:13] == 3'b000))
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mbc1_ram_enable <= (cart_di[3:0] == 4'ha);
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if(cart_wr && (cart_addr[15:13] == 3'b001)) begin
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if(cart_di[4:0]==0) mbc1_rom_bank_reg <= 5'd1;
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else mbc1_rom_bank_reg <= cart_di[4:0];
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end
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if(cart_wr && (cart_addr[15:13] == 3'b010))
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mbc1_ram_bank_reg <= cart_di[1:0];
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if(cart_wr && (cart_addr[15:13] == 3'b011))
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mbc1_mode <= cart_di[0];
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end
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end
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// extract header fields extracted from cartridge
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// during download
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reg [7:0] cart_mbc_type;
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reg [7:0] cart_rom_size;
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reg [7:0] cart_ram_size;
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// only write sdram if the write attept comes from the cart ram area
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wire cart_ram_wr = cart_wr && mbc1_ram_enable && (cart_addr[15:13] == 3'b101);
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// RAM size
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wire [1:0] ram_mask = // 0 - no ram
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(cart_ram_size == 1)?2'b00: // 1 - 2k, 1 bank
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(cart_ram_size == 2)?2'b00: // 2 - 8k, 1 bank
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2'b11; // 3 - 32k, 4 banks
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// ROM size
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wire [6:0] rom_mask = // 0 - 2 banks, 32k direct mapped
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(cart_rom_size == 1)?7'b0000011: // 1 - 4 banks = 64k
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(cart_rom_size == 2)?7'b0000111: // 2 - 8 banks = 128k
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(cart_rom_size == 3)?7'b0001111: // 3 - 16 banks = 256k
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(cart_rom_size == 4)?7'b0011111: // 4 - 32 banks = 512k
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(cart_rom_size == 5)?7'b0111111: // 5 - 64 banks = 1M
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7'b1111111; // 6 - 128 banks = 2M
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// MBC types
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// 0 - none
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// 1 - mbc1
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// 2 - mbc1 + ram
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// 3 - mbc1 + ram + bat
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// MBC1, MBC1+RAM, MBC1+RAM+BAT
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wire mbc1 = (cart_mbc_type == 1) || (cart_mbc_type == 2) || (cart_mbc_type == 3);
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wire [8:0] mbc_bank =
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mbc1?mbc1_addr: // MBC1, 16k bank 0, 16k bank 1-127 + ram
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{7'b0000000, cart_addr[14:13]}; // no MBC, 32k linear address
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always @(posedge clk_sys) begin
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if(!pll_locked) begin
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cart_mbc_type <= 8'h00;
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cart_rom_size <= 8'h00;
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cart_ram_size <= 8'h00;
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end else begin
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if(ioctl_download & ioctl_wr) begin
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case(ioctl_addr)
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'h146: cart_mbc_type <= ioctl_dout[15:8];
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'h148: { cart_ram_size, cart_rom_size } <= ioctl_dout;
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endcase
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end
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end
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end
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wire [7:0] cart_di; // data from cpu to cart
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wire [7:0] cart_do = ~cart_ready ? 8'h00 : cart_addr[0] ? sdram_do[15:8] : sdram_do[7:0];
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wire [15:0] cart_addr;
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wire cart_rd;
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wire cart_wr;
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wire lcd_clkena;
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wire [1:0] lcd_data;
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wire [1:0] lcd_mode;
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wire lcd_on;
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assign AUDIO_S = 0;
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wire reset = (RESET | status[0] | status[6] | buttons[1] | ioctl_download);
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// the gameboy itself
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gb gb (
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.reset ( reset ),
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.clk ( clk_cpu ), // the whole gameboy runs on 4mhnz
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.fast_boot ( status[2] ),
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.joystick ( joystick ),
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// interface to the "external" game cartridge
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.cart_addr ( cart_addr ),
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.cart_rd ( cart_rd ),
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.cart_wr ( cart_wr ),
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.cart_do ( cart_do ),
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.cart_di ( cart_di ),
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// audio
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.audio_l ( AUDIO_L ),
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.audio_r ( AUDIO_R ),
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// interface to the lcd
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.lcd_clkena ( lcd_clkena ),
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.lcd_data ( lcd_data ),
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.lcd_mode ( lcd_mode ),
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.lcd_on ( lcd_on )
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);
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// the lcd to vga converter
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wire [5:0] video_r, video_g, video_b;
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wire video_hs, video_vs, video_bl;
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lcd lcd (
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.pclk ( clk_sys ),
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.pce ( ce_pix ),
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.clk ( clk_cpu ),
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.tint ( status[1] ),
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.inv ( status[4] ),
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// serial interface
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.clkena ( lcd_clkena ),
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.data ( lcd_data ),
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.mode ( lcd_mode ), // used to detect begin of new lines and frames
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.on ( lcd_on ),
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.hs ( VGA_HS ),
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.vs ( VGA_VS ),
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.blank ( video_bl ),
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.r ( video_r ),
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.g ( video_g ),
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.b ( video_b )
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);
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assign VGA_R = {video_r,video_r[5:4]};
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assign VGA_G = {video_g,video_g[5:4]};
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assign VGA_B = {video_b,video_b[5:4]};
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assign VGA_DE = ~video_bl;
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assign CLK_VIDEO = clk_sys;
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assign CE_PIXEL = ce_pix2;
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wire clk_cpu = clk_sys & ce_cpu;
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reg ce_pix, ce_cpu, ce_pix2;
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always @(negedge clk_sys) begin
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reg [2:0] div = 0;
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div <= div + 1'd1;
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ce_pix2 <= !div[0];
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ce_pix <= !div[1:0];
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ce_cpu <= !div[2:0];
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end
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endmodule
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