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16 lines
241 B
Systemverilog
16 lines
241 B
Systemverilog
module CODES(
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input clk,
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input reset,
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input enable,
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output available,
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input [15:0] addr_in,
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input [7:0] data_in,
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input [128:0] code,
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output genie_ovr,
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output [7:0] genie_data
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);
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assign genie_ovr = 0;
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endmodule
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