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https://github.com/MiSTer-devel/Gameboy_MiSTer.git
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136 lines
3.7 KiB
Verilog
136 lines
3.7 KiB
Verilog
module link #(
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parameter CLK_DIV = 511
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)(
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// system signals
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input clk_sys,
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input ce,
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input rst,
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input sel_sc,
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input sel_sb,
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input cpu_wr_n,
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input sc_start_in,
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input sc_int_clock_in,
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input [7:0] sb_in,
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input serial_clk_in,
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input serial_data_in,
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output serial_clk_out,
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output serial_data_out,
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output [7:0] sb,
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output serial_irq,
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output reg sc_start,
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output reg sc_int_clock,
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// savestates
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input [63:0] SaveStateBus_Din,
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input [9:0] SaveStateBus_Adr,
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input SaveStateBus_wren,
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input SaveStateBus_rst,
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output [63:0] SaveStateBus_Dout
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);
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// savestates
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wire [16:0] SS_Link;
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wire [16:0] SS_Link_BACK;
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eReg_SavestateV #(0, 8, 16, 0, 64'h0000000000000000) iREG_SAVESTATE_HDMA (clk_sys, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, SaveStateBus_Dout, SS_Link_BACK, SS_Link);
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reg [7:0] sb_r = 0;
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assign sb = sb_r;
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reg [3:0] serial_counter;
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reg serial_out_r = 0;
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assign serial_data_out = serial_out_r;
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reg serial_clk_out_r = 1;
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assign serial_clk_out = serial_clk_out_r;
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reg serial_irq_r;
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assign serial_irq = serial_irq_r;
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reg [8:0] serial_clk_div; //8192Hz
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reg [1:0] serial_clk_in_last;
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assign SS_Link_BACK[ 0] = sc_start ;
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assign SS_Link_BACK[ 1] = sc_int_clock ;
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assign SS_Link_BACK[ 5: 2] = serial_counter ;
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assign SS_Link_BACK[ 6] = serial_out_r ;
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assign SS_Link_BACK[ 7] = serial_clk_out_r;
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assign SS_Link_BACK[16: 8] = serial_clk_div ;
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// serial master
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always @(posedge clk_sys) begin
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if(rst) begin
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sc_start <= SS_Link[ 0]; //1'b0;
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sc_int_clock <= SS_Link[ 1]; //1'b0;
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serial_counter <= SS_Link[ 5: 2]; //4'd0;
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serial_out_r <= SS_Link[ 6]; //1'b0;
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serial_clk_out_r <= SS_Link[ 7]; //1'b0;
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serial_clk_div <= SS_Link[16: 8]; //9'd0;
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sb_r <= sb_in;
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serial_clk_in_last <= {1'b0,serial_clk_in};
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end else if (ce) begin
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serial_irq_r <= 1'b0;
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if (sel_sc && !cpu_wr_n) begin //cpu write
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sc_start <= sc_start_in;
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sc_int_clock <= sc_int_clock_in;
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if (sc_start_in) begin //enable transfer
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serial_clk_div <= CLK_DIV[8:0];
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serial_counter <= 4'd8;
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serial_clk_out_r <= 1'b1;
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//serial_clk_in_last <= serial_clk_in;
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serial_clk_in_last <= {1'b0,serial_clk_in};
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end
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end else if (sel_sb && !cpu_wr_n) begin
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sb_r <= sb_in;
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end else if (sc_start) begin // serial transfer
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if (sc_int_clock) begin // internal clock
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serial_clk_div <= serial_clk_div - 9'd1;
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if (serial_counter != 0) begin
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if (serial_clk_div == CLK_DIV/2+1) begin
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serial_clk_out_r <= ~serial_clk_out_r;
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serial_out_r <= sb[7];
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end else if (!serial_clk_div) begin
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sb_r <= {sb[6:0], serial_data_in};
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serial_clk_out_r <= ~serial_clk_out;
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serial_counter <= serial_counter - 1'd1;
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serial_clk_div <= CLK_DIV[8:0];
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end
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end else begin
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serial_irq_r <= 1'b1;
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sc_start <= 1'b0;
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serial_clk_div <= CLK_DIV[8:0];
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serial_counter <= 4'd8;
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end
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end else begin // external clock
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serial_clk_in_last[0] <= serial_clk_in;
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serial_clk_in_last[1] <= serial_clk_in_last[0] ;
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if (serial_clk_in_last[1] != serial_clk_in_last[0]) begin
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if (serial_clk_in_last[1] == 0) begin
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serial_out_r <= sb[7]; // send out bit to linked gb
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serial_counter <= serial_counter - 1'd1;
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end else begin // posedge external clock
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sb_r <= {sb[6:0], serial_data_in}; // capture bit into sb
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if (serial_counter == 0) begin // read in 8 bits?
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serial_irq_r <= 1'b1; // set interrupt, reset counter/sc_start for next read
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sc_start <= 1'b0;
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serial_counter <= 4'd8;
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end
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end
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end
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end
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end
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end
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end
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endmodule
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// vim:sw=3:ts=3:et:
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