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https://github.com/MiSTer-devel/Gameboy_MiSTer.git
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7b44195b09
-Writing to $FE00-FEFF would overwrite IRAM (Megaman Xtreme) -HDMA should remember last source and target (Harry potter) -Stopping a HDMA transfer with CPU at single speed would stop and then start a new transfer (Pokemon Crystal) -Give IRAM time to provide valid data at the start and end of HDMA transfer (Donkey Kong Country fishing, Pokemon Crystal)
372 lines
8.1 KiB
Verilog
372 lines
8.1 KiB
Verilog
module hdma(
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input reset,
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input clk,
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input ce, // 4 or 8 Mhz cpu clock
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input speed, // cpu speed mode use for amount of byte cycles
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// cpu register interface
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input sel_reg,
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input [3:0] addr,
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input wr,
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output [7:0] dout,
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input [7:0] din,
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input [1:0] lcd_mode,
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// dma connection
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output reg hdma_rd,
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output reg hdma_active,
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output [15:0] hdma_source_addr,
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output [15:0] hdma_target_addr
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);
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//"The preparation time (4 clocks) is the same in single and double speed mode"
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localparam START_DELAY = 3'd4;
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//ff51-ff55 HDMA1-5 (GBC)
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reg [11:0] hdma_source; // ff51, ff52 only top 4 bits used
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reg [8:0] hdma_target; // ff53 only lowest 5 bits used, ff54 only top 4 bits used
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reg hdma_mode; // ff55 bit 7 - 1=General Purpose DMA 0=H-Blank DMA
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reg hdma_enabled; // ff55 !bit 7 when read
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reg [7:0] hdma_length; // ff55 bit 6:0 - dma transfer length (hdma_length+1)*16 bytes
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reg hdma_end;
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// it takes about 8us to transfer a block of 16 bytes. -> 500ns per byte -> 2Mhz
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// 32 cycles in Normal Speed Mode, and 64 'fast' cycles in Double Speed Mode
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reg [3:0] byte_cnt; // 16bytes
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// Normal speed: 2 cycles, Double speed: 4 cycles per byte.
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wire [1:0] byte_cycles = speed ? 2'd3 : 2'd1;
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reg [1:0] hdma_cnt;
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//assign hdma_rd = hdma_active;
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assign hdma_source_addr = { hdma_source, byte_cnt };
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assign hdma_target_addr = { 3'b100,hdma_target, byte_cnt };
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reg [2:0] dma_delay;
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reg [1:0] hdma_state;
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parameter active=2'd0,blocksent=2'd1,wait_h=2'd2;
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always @(posedge clk) begin
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if(reset) begin
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hdma_active <= 1'b0;
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hdma_state <= wait_h;
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hdma_enabled <= 1'b0;
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hdma_source <= 12'hFFF;
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hdma_target <= 9'h1FF;
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dma_delay <= 3'd0;
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hdma_rd <= 0;
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hdma_end <= 0;
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end
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else if(ce) begin
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if(sel_reg && wr) begin
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case (addr)
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4'd1: hdma_source[11:4] <= din;
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4'd2: hdma_source[3:0] <= din[7:4];
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4'd3: hdma_target[8:4] <= din[4:0];
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4'd4: hdma_target[3:0] <= din[7:4];
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// writing the hdma register engages the dma engine
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4'h5: begin
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hdma_length <= {1'b0,din[6:0]};
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if (hdma_mode == 1 && hdma_enabled && !din[7]) begin //terminate an active H-Blank transfer by writing zero to Bit 7 of FF55
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hdma_state <= wait_h;
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hdma_end <= 1'b1;
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hdma_rd <= 1'b0;
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hdma_enabled <= 1'b0;
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end else begin //normal trigger
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hdma_enabled <= 1'b1;
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hdma_mode <= din[7];
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dma_delay <= START_DELAY;
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hdma_cnt <= 2'd0;
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byte_cnt <= 4'd0;
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if (din[7] == 1) hdma_state <= wait_h;
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end
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end
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endcase
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end
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// Currently IRAM takes 1 CPU cycle to get data. If hdma_active is lowered
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// at the same time as hdma_rd then the CPU will read invalid data.
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if (hdma_end) begin
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hdma_active <= 0;
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hdma_end <= 0;
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end
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if (hdma_enabled) begin
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if(hdma_mode==0) begin //mode 0 GDMA do the transfer in one go after inital delay
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hdma_active <= 1'b1;
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hdma_rd <= 1'b1; // get data from RAM ready while waiting
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if (dma_delay>0) begin
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dma_delay <= dma_delay - 1'b1;
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end else begin
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if(hdma_length != 8'hFF) begin
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hdma_cnt <= hdma_cnt + 1'd1;
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if (hdma_cnt == byte_cycles) begin
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hdma_cnt <= 2'd0;
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byte_cnt <= byte_cnt + 1'b1;
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if (&byte_cnt) begin
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hdma_source <= hdma_source + 1'b1;
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hdma_target <= hdma_target + 1'b1;
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hdma_length <= hdma_length - 1'd1;
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if (hdma_length == 0) begin
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hdma_end <= 1'b1;
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hdma_rd <= 1'b0;
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hdma_enabled <= 1'b0;
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end
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end
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end
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end
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end
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end else begin //mode 1 HDMA transfer 1 block (16bytes) in each H-Blank only
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case (hdma_state)
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wait_h: begin
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if (lcd_mode == 2'b00 ) begin // Mode 00: h-blank
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dma_delay <= START_DELAY;
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hdma_state <= active;
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end
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hdma_end <= 1'b1;
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hdma_rd <= 1'b0;
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end
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blocksent: begin
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if (hdma_length == 8'hFF) begin //check if finished
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hdma_enabled <= 1'b0;
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end
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if (lcd_mode == 2'b11) // wait for mode 3, mode before h-blank
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hdma_state <= wait_h;
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end
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active: begin
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if(hdma_length != 8'hFF) begin
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hdma_active <= 1'b1;
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hdma_rd <= 1'b1; // get data from RAM ready while waiting
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if (dma_delay>0) begin
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dma_delay <= dma_delay - 1'b1;
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end else begin
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hdma_cnt <= hdma_cnt + 1'd1;
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if (hdma_cnt == byte_cycles) begin
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hdma_cnt <= 2'd0;
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byte_cnt <= byte_cnt + 1'b1;
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if (&byte_cnt) begin
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hdma_source <= hdma_source + 1'b1;
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hdma_target <= hdma_target + 1'b1;
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hdma_length <= hdma_length - 1'd1;
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hdma_state <= blocksent;
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hdma_end <= 1'b1;
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hdma_rd <= 1'b0;
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end
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end
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end
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end else begin
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hdma_end <= 1'b1;
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hdma_rd <= 1'b0;
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hdma_enabled <= 1'b0;
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end
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end
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endcase
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end
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end
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end
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end
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assign dout = (sel_reg && addr==4'd5) ? {~hdma_enabled, hdma_length[6:0]} : 8'hFF;
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endmodule
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/*
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`timescale 1 ns/100 ps // time-unit = 1 ns, precision = 100 ps
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module hdma_tb;
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// duration for each bit = 125 * timescale = 125 * 1 ns = 125ns // 8MHz
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localparam period = 125;
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reg reset = 1'd1;
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reg clk = 1'd0;
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reg speed = 1'b0;
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// cpu register interface
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reg sel_reg = 1'd0;
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reg [3:0] addr = 4'd0;
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reg wr = 1'd0;
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wire [7:0] dout;
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reg [7:0] din = 8'd0;
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reg [1:0] lcd_mode = 2'd0;
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// dma connection
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wire hdma_rd;
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wire hdma_active;
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wire [15:0] hdma_source_addr;
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wire [15:0] hdma_target_addr;
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hdma hdma(
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.reset ( reset ),
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.clk ( clk ),
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.speed ( speed ),
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// cpu register interface
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.sel_reg ( sel_reg ),
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.addr ( addr ),
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.wr ( wr ),
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.dout ( dout ),
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.din ( din ),
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.lcd_mode ( lcd_mode ),
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// dma connection
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.hdma_rd ( hdma_rd ),
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.hdma_active ( hdma_active ),
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.hdma_source_addr ( hdma_source_addr ),
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.hdma_target_addr ( hdma_target_addr )
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);
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always #62 clk <= !clk;
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initial begin
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reset <= 1'b0;
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sel_reg <= 1'b1;
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addr <= 4'd4;
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#1000
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sel_reg <= 1'b1;
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addr <= 4'd1; // source h
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din <= 8'h20;
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wr <= 1'd1;
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#period
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wr <= 1'd0;
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#period
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sel_reg <= 1'b1;
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addr <= 4'd2; // source l
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din <= 8'h40;
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wr <= 1'd1;
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#period
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wr <= 1'd0;
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#period
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sel_reg <= 1'b1;
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addr <= 4'd3; // target h
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din <= 8'h82;
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wr <= 1'd1;
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#period
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wr <= 1'd0;
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#period
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sel_reg <= 1'b1;
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addr <= 4'd4; // target l
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din <= 8'h00;
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wr <= 1'd1;
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#period
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wr <= 1'd0;
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#period
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$display("GDMA");
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sel_reg <= 1'b1;
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addr <= 4'd5; // trigger GDMA with length
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din <= 8'h01; // 20h bytes
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wr <= 1'd1;
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#period
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wr <= 1'd0;
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#8000
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lcd_mode <= 2'd1;
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#2000
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lcd_mode <= 2'd0;
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#8000
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$display("HDMA");
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sel_reg <= 1'b1;
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addr <= 4'd5; // trigger HDMA with length
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din <= 8'h82; // 30h bytes
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wr <= 1'd1;
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#period
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wr <= 1'd0;
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#16000
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lcd_mode <= 2'd2;
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#2000
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lcd_mode <= 2'd3;
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#2000
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lcd_mode <= 2'd0;
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#16000
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lcd_mode <= 2'd2;
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#2000
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lcd_mode <= 2'd3;
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#2000
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lcd_mode <= 2'd0;
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#16000
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sel_reg <= 1'b1;
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addr <= 4'd5;
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$display("Check FF55");
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#1000
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$display("HDMA with cancel");
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sel_reg <= 1'b1;
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addr <= 4'd5; // trigger HDMA with length
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din <= 8'h82; // 30h bytes
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wr <= 1'd1;
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#period
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wr <= 1'd0;
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#16000
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lcd_mode <= 2'd2;
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#2000
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lcd_mode <= 2'd3;
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#2000
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$display("canceling");
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sel_reg <= 1'b1;
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addr <= 4'd5; // trigger HDMA with length
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din <= 8'h00; // stop
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wr <= 1'd1;
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#period
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wr <= 1'd0;
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#16000
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sel_reg <= 1'b1;
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addr <= 4'd5;
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$display("Check FF55");
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lcd_mode <= 2'd2;
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#2000
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lcd_mode <= 2'd3;
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#2000
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$display("Test Complete");
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end
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endmodule
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*/
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