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ee8bf4c29f
Maximum of 6 extra sprites per line Extra sprites are fetched during mode2 to not break mode3 timing
68 lines
1.2 KiB
Verilog
68 lines
1.2 KiB
Verilog
module sprites_extra_store (
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input clk,
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input ce,
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input reset,
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input save_x,
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input [7:0] xpos,
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input tile_save,
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input [7:0] tile0_in,
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input [7:0] tile1_in,
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input [3:0] index_in,
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input [2:0] cgb_pal_in,
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input pal_in,
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input prio_in,
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output x_match,
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output [7:0] tile0_o,
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output [7:0] tile1_o,
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output [2:0] cgb_pal_o,
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output [3:0] index_o,
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output pal_o,
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output prio_o
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);
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reg [7:0] x;
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reg [7:0] tile0;
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reg [7:0] tile1;
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reg [2:0] cgb_pal;
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reg [3:0] index;
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reg pal;
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reg prio;
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always @(posedge clk) begin
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if (ce) begin
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if (reset) begin
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x <= 8'hFF;
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tile0 <= 8'd0;
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tile1 <= 8'd0;
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end else begin
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if (save_x) begin
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x <= xpos;
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end
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if (tile_save) begin
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tile0 <= tile0_in;
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tile1 <= tile1_in;
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pal <= pal_in;
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prio <= prio_in;
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cgb_pal <= cgb_pal_in;
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index <= index_in;
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end
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end
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end
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end
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assign x_match = (xpos == x);
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assign tile0_o = x_match ? tile0 : 8'hZZ;
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assign tile1_o = x_match ? tile1 : 8'hZZ;
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assign pal_o = x_match ? pal : 1'bZ;
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assign prio_o = x_match ? prio : 1'bZ;
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assign cgb_pal_o = x_match ? cgb_pal : 3'hZ;
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assign index_o = x_match ? index : 4'hZ;
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endmodule |