mirror of
https://github.com/MiSTer-devel/Gameboy_MiSTer.git
synced 2026-04-19 03:04:09 +00:00
016f45bc7b
* Move Cart RAM to SDRAM Used the SDRAM controller from the NES core * 3D LUT for color correction. Load custom LUT * Add custom LUTs * Fix OAM saving to save state
158 lines
4.7 KiB
VHDL
158 lines
4.7 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity speedcontrol is
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port
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(
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clk_sys : in std_logic;
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pause : in std_logic;
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speedup : in std_logic;
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cart_act : in std_logic;
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save_act : in std_logic;
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DMA_on : in std_logic;
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ce : out std_logic := '0';
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ce_n : out std_logic := '0';
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ce_2x : buffer std_logic := '0';
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refresh : out std_logic := '0';
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ff_on : out std_logic := '0'
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);
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end entity;
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architecture arch of speedcontrol is
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signal clkdiv : unsigned(2 downto 0) := (others => '0');
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signal cart_act_1 : std_logic := '0';
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signal unpause_cnt : integer range 0 to 15 := 0;
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signal fastforward_cnt : integer range 0 to 15 := 0;
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signal refreshcnt : integer range 0 to 127 := 0;
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signal sdram_busy : integer range 0 to 1 := 0;
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type tstate is
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(
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NORMAL,
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PAUSED,
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FASTFORWARDSTART,
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FASTFORWARD,
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FASTFORWARDEND,
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RAMACCESS
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);
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signal state : tstate := NORMAL;
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begin
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process(clk_sys)
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begin
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if falling_edge(clk_sys) then
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ce <= '0';
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ce_n <= '0';
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ce_2x <= '0';
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refresh <= '0';
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cart_act_1 <= cart_act;
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if (refreshcnt > 0) then
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refreshcnt <= refreshcnt - 1;
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end if;
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case (state) is
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when NORMAL =>
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if (pause = '1' and clkdiv = "111" and cart_act = '0') then
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state <= PAUSED;
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unpause_cnt <= 0;
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elsif (speedup = '1' and pause = '0' and DMA_on = '0' and save_act = '0' and clkdiv = "000") then
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state <= FASTFORWARDSTART;
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fastforward_cnt <= 0;
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else
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clkdiv <= clkdiv + 1;
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if (clkdiv = "000") then
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ce <= '1';
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end if;
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if (clkdiv = "100") then
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ce_n <= '1';
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end if;
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if (clkdiv(1 downto 0) = "00") then
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ce_2x <= '1';
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end if;
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end if;
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when PAUSED =>
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if (unpause_cnt = 0) then
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if (refreshcnt > 117) then
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refresh <= '1';
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elsif (refreshcnt = 0) then
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refreshcnt <= 127;
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end if;
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end if;
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if (pause = '0') then
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if (unpause_cnt = 15) then
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state <= NORMAL;
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else
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unpause_cnt <= unpause_cnt + 1;
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end if;
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end if;
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when FASTFORWARDSTART =>
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if (fastforward_cnt = 15) then
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state <= FASTFORWARD;
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ff_on <= '1';
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else
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fastforward_cnt <= fastforward_cnt + 1;
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end if;
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when FASTFORWARD =>
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if (pause = '1' or speedup = '0' or DMA_on = '1' or save_act = '1') then
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state <= FASTFORWARDEND;
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fastforward_cnt <= 0;
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if (clkdiv(0) = '1') then
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clkdiv <= "100";
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end if;
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elsif (cart_act = '1' and cart_act_1 = '0') then
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state <= RAMACCESS;
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sdram_busy <= 1;
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-- Refresh is already done in current SDRAM controller
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--elsif (cart_act = '0' and refreshcnt = 0) then
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-- refreshcnt <= 127;
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-- refresh <= '1';
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-- state <= RAMACCESS;
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-- sdram_busy <= 1;
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else
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clkdiv(0) <= not clkdiv(0);
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if (clkdiv(0) = '0') then
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ce <= '1';
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else
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ce_n <= '1';
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end if;
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ce_2x <= '1';
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end if;
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when FASTFORWARDEND =>
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if (fastforward_cnt = 15) then
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state <= NORMAL;
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ff_on <= '0';
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else
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fastforward_cnt <= fastforward_cnt + 1;
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end if;
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when RAMACCESS =>
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if (sdram_busy > 0) then
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sdram_busy <= sdram_busy - 1;
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else
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state <= FASTFORWARD;
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end if;
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end case;
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end if;
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end process;
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end architecture;
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