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108 lines
2.5 KiB
Systemverilog
108 lines
2.5 KiB
Systemverilog
//
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// ddram.v
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// Copyright (c) 2019 Sorgelig
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ------------------------------------------
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//
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module ddram
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(
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input DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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// save state
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input [27:1] ch1_addr,
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output [63:0] ch1_dout,
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input [63:0] ch1_din,
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input ch1_req,
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input ch1_rnw,
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input [7:0] ch1_be,
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output ch1_ready
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);
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reg [7:0] ram_burst;
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reg [63:0] ram_q[1:1];
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reg [63:0] ram_data;
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reg [27:1] ram_address;
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reg ram_read = 0;
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reg ram_write = 0;
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reg [7:0] ram_be;
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reg [5:1] ready;
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assign DDRAM_BURSTCNT = ram_burst;
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assign DDRAM_BE = ram_read ? 8'hFF : ram_be;
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assign DDRAM_ADDR = {4'b0011, ram_address[27:3]}; // RAM at 0x30000000
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assign DDRAM_RD = ram_read;
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assign DDRAM_DIN = ram_data;
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assign DDRAM_WE = ram_write;
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assign ch1_dout = ram_q[1];
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assign ch1_ready = ready[1];
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reg state = 0;
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reg [0:0] ch = 0;
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reg [1:1] ch_rq;
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always @(posedge DDRAM_CLK) begin
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ch_rq <= ch_rq | {ch1_req};
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ready <= 0;
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if(!DDRAM_BUSY) begin
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ram_write <= 0;
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ram_read <= 0;
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case(state)
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0: if(ch_rq[1] || ch1_req) begin
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ch_rq[1] <= 0;
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ch <= 1;
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ram_data <= ch1_din;
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ram_be <= ch1_be;
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ram_address <= ch1_addr;
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ram_burst <= 1;
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if(~ch1_rnw) begin
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ram_write <= 1;
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ready[1] <= 1;
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end
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else begin
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ram_read <= 1;
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state <= 1;
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end
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end
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1: if(DDRAM_DOUT_READY) begin
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ram_q[ch] <= DDRAM_DOUT;
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ready[ch] <= 1;
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state <= 0;
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end
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endcase
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end
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end
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endmodule
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