mirror of
https://github.com/MiSTer-devel/Gameboy_MiSTer.git
synced 2026-04-19 03:04:09 +00:00
016f45bc7b
* Move Cart RAM to SDRAM Used the SDRAM controller from the NES core * 3D LUT for color correction. Load custom LUT * Add custom LUTs * Fix OAM saving to save state
459 lines
13 KiB
Verilog
459 lines
13 KiB
Verilog
module cart_top (
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input reset,
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input clk_sys,
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input ce_cpu,
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input ce_cpu2x,
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input speed,
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input megaduck,
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input duck_md0_mode,
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input [2:0] mapper_sel,
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input [14:0] cart_addr,
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input cart_a15,
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input cart_rd,
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input cart_wr,
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output [7:0] cart_do,
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input [7:0] cart_di, // data from cpu to cart
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output cart_oe,
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input nCS,
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output [22:0] mbc_addr,
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output reg dn_write,
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output cart_ready,
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output is_cram_addr,
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output cram_rd,
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output cram_wr,
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output cram_bram_wr,
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output [16:0] cram_addr,
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input cart_download,
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output [7:0] ram_mask_file,
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output [7:0] ram_size,
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output has_save,
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output bram_save,
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output isGBC_game,
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output isSGB_game,
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input ioctl_download,
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input ioctl_wr,
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input [24:0] ioctl_addr,
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input [15:0] ioctl_dout,
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output ioctl_wait,
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input bk_wr,
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input bk_rtc_wr,
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input [16:0] bk_addr,
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input [15:0] bk_data,
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output [15:0] bk_q,
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input [63:0] img_size,
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input [7:0] rom_di,
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input [15:0] joystick_analog_0,
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input ce_32k,
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input [32:0] RTC_time,
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output [31:0] RTC_timestampOut,
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output [47:0] RTC_savedtimeOut,
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output RTC_inuse,
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input [63:0] SaveStateExt_Din,
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input [9:0] SaveStateExt_Adr,
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input SaveStateExt_wren,
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input SaveStateExt_rst,
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output [63:0] SaveStateExt_Dout,
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input savestate_load,
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input savestate_ovr,
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input [19:0] Savestate_CRAMAddr,
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input Savestate_CRAMRWrEn,
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input [15:0] Savestate_CRAMWriteData,
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output [15:0] Savestate_CRAM_Q,
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output rumbling
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);
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///////////////////////////////////////////////////
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// http://fms.komkon.org/GameBoy/Tech/Carts.html
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// 32MB SDRAM memory map using word addresses
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// 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 D
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// 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 S
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// -------------------------------------------------
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// 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X up to 2MB used as ROM (MBC1-3), 8MB for MBC5
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// 0 0 0 0 R R B B B B B C C C C C C C C C C C C C C MBC1 ROM (R=RAM bank in mode 0)
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wire [15:0] SS_Ext;
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wire [15:0] SS_Ext_BACK;
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wire [63:0] SS_Ext2;
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wire [63:0] SS_Ext2_BACK;
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wire [63:0] SaveStateBus_Dout_or[0:1];
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eReg_SavestateV #(0, 32, 15, 0, 64'h0000000000000001) iREG_SAVESTATE_Ext (clk_sys, SaveStateExt_Din, SaveStateExt_Adr, SaveStateExt_wren, SaveStateExt_rst, SaveStateBus_Dout_or[0], SS_Ext_BACK, SS_Ext);
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eReg_SavestateV #(0, 37, 63, 0, 64'h0000000000000000) iREG_SAVESTATE_Ext2 (clk_sys, SaveStateExt_Din, SaveStateExt_Adr, SaveStateExt_wren, SaveStateExt_rst, SaveStateBus_Dout_or[1], SS_Ext2_BACK, SS_Ext2);
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assign SaveStateExt_Dout = SaveStateBus_Dout_or[0] | SaveStateBus_Dout_or[1];
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wire [7:0] rom_do;
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wire [7:0] mbc_cram_do;
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wire [16:0] mbc_cram_addr;
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wire mbc_ram_enable, mbc_battery;
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wire mbc_cram_wr;
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wire [7:0] mbc_cram_wr_do;
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mappers mappers (
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.reset ( reset ),
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.clk_sys ( clk_sys ),
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.ce_cpu ( ce_cpu ),
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.ce_cpu2x ( ce_cpu2x ),
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.speed ( speed ),
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.mbc1 ( mbc1 ),
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.mbc1m ( mbc1m ),
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.mbc2 ( mbc2 ),
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.mbc3 ( mbc3 ),
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.mbc30( mbc30 ),
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.mbc5 ( mbc5 ),
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.mbc6 ( mbc6 ),
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.mbc7 ( mbc7 ),
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.mmm01 ( mmm01 ),
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.huc1 ( HuC1 ),
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.huc3 ( HuC3 ),
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.gb_camera ( gb_camera ),
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.tama ( tama ),
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.rocket ( rocket ),
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.sachen ( sachen),
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.wisdom_tree ( wisdom_tree ),
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.mani161 ( mani161 ),
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.megaduck ( megaduck_en ),
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.duck_md0_mode ( duck_md0_mode ),
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.isGBC_game ( isGBC_game ),
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.joystick_analog_0 ( joystick_analog_0 ),
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.ce_32k ( ce_32k ),
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.RTC_time ( RTC_time ),
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.RTC_timestampOut ( RTC_timestampOut ),
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.RTC_savedtimeOut ( RTC_savedtimeOut ),
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.RTC_inuse ( RTC_inuse ),
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.bk_wr ( bk_wr ),
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.bk_rtc_wr ( bk_rtc_wr ),
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.bk_addr ( bk_addr ),
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.bk_data ( bk_data ),
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.img_size ( img_size ),
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.savestate_load ( savestate_load ),
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.savestate_data ( SS_Ext ),
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.savestate_back ( SS_Ext_BACK ),
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.savestate_data2 ( SS_Ext2 ),
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.savestate_back2 ( SS_Ext2_BACK ),
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.has_ram ( |ram_size ),
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.ram_mask ( ram_mask ),
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.rom_mask ( rom_mask ),
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.cart_addr ( cart_addr ),
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.cart_a15 ( cart_a15 ),
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.cart_mbc_type ( cart_mbc_type ),
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.cart_rd ( cart_rd ),
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.cart_wr ( cart_wr ),
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.cart_di ( cart_di ),
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.cart_oe ( cart_oe ),
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.rom_di ( rom_di ),
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.rom_do ( rom_do ),
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.nCS ( nCS ),
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.cram_rd ( cram_rd ),
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.cram_di ( bram_save ? cram_q : rom_di ),
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.cram_do ( mbc_cram_do ),
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.cram_addr ( mbc_cram_addr ),
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.cram_wr_do ( mbc_cram_wr_do ),
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.cram_wr ( mbc_cram_wr ),
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.mbc_addr ( mbc_addr ),
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.ram_enabled ( mbc_ram_enable ),
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.has_battery ( mbc_battery ),
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.rumbling ( cart_rumbling )
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);
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// extract header fields extracted from cartridge
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// during download
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reg [7:0] cart_mbc_type;
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reg [7:0] cart_rom_size;
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reg [7:0] cart_ram_size;
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reg cart_cgb_flag;
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reg [7:0] cart_sgb_flag;
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reg [7:0] cart_old_licensee;
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reg [15:0] cart_logo_data[0:7];
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// RAM size
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wire [3:0] ram_mask = // 0 - no ram
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(ram_size == 1)?4'b0000: // 1 - 2k, 1 bank
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(ram_size == 2)?4'b0000: // 2 - 8k, 1 bank
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(ram_size == 3)?4'b0011: // 3 - 32k, 4 banks
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(ram_size == 5)?4'b0111: // 5 - 64k, 8 banks
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4'b1111; // 4 - 128k 16 banks
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// ROM size
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/*
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wire [8:0] rom_mask =
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(cart_rom_size == 0)? 9'b000000001: // 0 - 2 banks, 32k direct mapped
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(cart_rom_size == 1)? 9'b000000011: // 1 - 4 banks = 64k
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(cart_rom_size == 2)? 9'b000000111: // 2 - 8 banks = 128k
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(cart_rom_size == 3)? 9'b000001111: // 3 - 16 banks = 256k
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(cart_rom_size == 4)? 9'b000011111: // 4 - 32 banks = 512k
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(cart_rom_size == 5)? 9'b000111111: // 5 - 64 banks = 1M
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(cart_rom_size == 6)? 9'b001111111: // 6 - 128 banks = 2M
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(cart_rom_size == 7)? 9'b011111111: // 7 - 256 banks = 4M
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(cart_rom_size == 8)? 9'b111111111: // 8 - 512 banks = 8M
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(cart_rom_size == 82)?9'b001111111: //$52 - 72 banks = 1.1M
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(cart_rom_size == 83)?9'b001111111: //$53 - 80 banks = 1.2M
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(cart_rom_size == 84)?9'b001111111:
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9'b001111111; //$54 - 96 banks = 1.5M
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*/
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reg [8:0] rom_mask; // get mask from file size
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wire mbc1 = (mapper_sel_r == 3'd3) || (cart_mbc_type == 1) || (cart_mbc_type == 2) || (cart_mbc_type == 3);
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wire mbc2 = (cart_mbc_type == 5) || (cart_mbc_type == 6);
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//wire mmm01 = (cart_mbc_type == 11) || (cart_mbc_type == 12) || (cart_mbc_type == 13) || (cart_mbc_type == 14);
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wire mbc3 = (mapper_sel_r == 3'd4) || (cart_mbc_type == 15) || (cart_mbc_type == 16) || (cart_mbc_type == 17) || (cart_mbc_type == 18) || (cart_mbc_type == 19);
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wire mbc30 = mbc3 && ( (cart_rom_size == 7) || (ram_size == 5) );
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//wire mbc4 = (cart_mbc_type == 21) || (cart_mbc_type == 22) || (cart_mbc_type == 23);
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wire mbc5 = (cart_mbc_type == 25) || (cart_mbc_type == 26) || (cart_mbc_type == 27) || (cart_mbc_type == 28) || (cart_mbc_type == 29) || (cart_mbc_type == 30);
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wire mbc6 = (cart_mbc_type == 32);
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wire mbc7 = (cart_mbc_type == 34);
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wire rocket = (cart_mbc_type == 151) || (cart_mbc_type == 153);
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wire megaduck_en = (cart_mbc_type == 250); // Use a wire to ensure enable is low while loading
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wire duck_md0_cart = megaduck_en && duck_md0_mode;
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// MD0 system ROM/laptop carts expose the 32KB external memory cart.
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assign ram_size = duck_md0_cart ? 8'd3 : cart_ram_size;
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wire gb_camera = (cart_mbc_type == 252);
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wire tama = (cart_mbc_type == 253);
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wire HuC3 = (cart_mbc_type == 254);
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wire HuC1 = (cart_mbc_type == 255);
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wire wisdom_tree = (mapper_sel_r == 3'd1);
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wire mani161 = (mapper_sel_r == 3'd2);
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wire has_rumble = (cart_mbc_type[7:2] == 6'b0001_11);
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wire cart_rumbling;
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assign rumbling = has_rumble & cart_rumbling;
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assign isGBC_game = (cart_cgb_flag);
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assign isSGB_game = (cart_sgb_flag == 8'h03 && cart_old_licensee == 8'h33);
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// MBC1M detect
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reg [7:0] cart_logo_check;
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reg [2:0] cart_logo_idx;
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reg mbc1m, mmm01;
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reg mbc1m_check_end, mmm01_check_end;
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reg sachen, sachen_t1, sachen_t2;
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wire mbc1m_bank = (~|ioctl_addr[24:20] && ioctl_addr[19:12] == 8'h40); // $40000
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wire mmm01_bank = (ioctl_addr[18:12] == 7'h78); // $78000+
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wire cart_logo_match = &cart_logo_check;
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reg old_cart_download;
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reg [2:0] mapper_sel_r;
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always @(posedge clk_sys) begin
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old_cart_download <= cart_download;
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if(~old_cart_download & cart_download) begin
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cart_logo_idx <= 3'd0;
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cart_logo_check <= 8'd0;
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cart_mbc_type <= 8'd0;
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mbc1m <= 0;
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mmm01 <= 0;
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{ sachen, sachen_t1, sachen_t2 } <= 0;
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mapper_sel_r <= mapper_sel;
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rom_mask <= 9'd0;
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end
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if(cart_download & ioctl_wr) begin
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rom_mask <= ioctl_addr[22:14] | rom_mask;
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if (megaduck) begin
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cart_cgb_flag <= 0;
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cart_sgb_flag <= 0;
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mapper_sel_r <= 0;
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if (ioctl_addr > 'h100) // Make sure there's time to reset the banks in the mapper
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cart_mbc_type <= 8'd250;
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end else begin
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if (~|ioctl_addr[24:12] || (mmm01_bank & mmm01) ) // MMM01 header is at the end of ROM
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case(ioctl_addr[11:0])
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12'h142: cart_cgb_flag <= ioctl_dout[15];
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12'h146: begin
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{cart_mbc_type, cart_sgb_flag} <= ioctl_dout;
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// "Mani 4 in 1" have incorrectly set MBC3 in the header
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if ( mmm01 && ioctl_dout[15:8] == 8'h11) cart_mbc_type <= 8'h0B;
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end
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12'h148: { cart_ram_size, cart_rom_size } <= ioctl_dout;
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12'h14a: { cart_old_licensee } <= ioctl_dout[15:8];
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endcase
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// Disable other mappers when a specific mapper has been selected
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if (|mapper_sel_r) begin
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cart_mbc_type <= 8'd0;
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mbc1m <= 0;
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mmm01 <= 0;
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sachen <= 0;
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end else begin
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// Sachen
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if (~|ioctl_addr[24:12]) begin
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case(ioctl_addr[11:0])
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12'h100: sachen_t1 <= (ioctl_dout[15:8] != 8'hC3);
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12'h140: sachen_t2 <= (ioctl_dout[ 7:0] == 8'hC3); // 0xC3 opcode is at $140 instead of $101
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12'h150: begin /// CGB flag
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if (sachen_t1 & sachen_t2) begin
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sachen <= 1'b1;
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cart_cgb_flag <= ioctl_dout[15];
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cart_mbc_type <= 0;
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cart_sgb_flag <= 0;
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cart_ram_size <= 0;
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cart_old_licensee <= 0;
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end
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end
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endcase
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end
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//Store cart logo data
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if (ioctl_addr >= 'h104 && ioctl_addr <= 'h112) begin
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cart_logo_data[cart_logo_idx] <= ioctl_dout;
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cart_logo_idx <= cart_logo_idx + 1'b1;
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end
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// MBC1 Multicart detect: Compare 8 words of logo data at second 256KByte bank ($40000)
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// MMM01 detect: Compare the last bank every 512KByte ($78000+)
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if ( mbc1m_bank | mmm01_bank ) begin
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if (ioctl_addr[11:0] >= 12'h104 && ioctl_addr[11:0] <= 12'h112) begin
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cart_logo_check[cart_logo_idx] <= (ioctl_dout == cart_logo_data[cart_logo_idx]);
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cart_logo_idx <= cart_logo_idx + 1'b1;
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if (&cart_logo_idx) begin
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if (mbc1m_bank) mbc1m_check_end <= 1;
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if (mmm01_bank) mmm01_check_end <= 1;
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end
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end
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end
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if (mbc1m_check_end) begin
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mbc1m_check_end <= 0;
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mbc1m <= cart_logo_match;
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end
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if (mmm01_check_end) begin
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mmm01_check_end <= 0;
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mmm01 <= cart_logo_match;
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if (cart_logo_match) mbc1m <= 0;
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end
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end
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end
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end
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end
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reg cart_ready_r = 0;
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reg ioctl_wait_r;
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always @(posedge clk_sys) begin
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if(ioctl_wr) ioctl_wait_r <= 1;
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if(speed?ce_cpu2x:ce_cpu) begin
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dn_write <= ioctl_wait_r;
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if(dn_write) {ioctl_wait_r, dn_write} <= 0;
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if(dn_write) cart_ready_r <= 1;
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end
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end
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assign cart_ready = cart_ready_r;
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assign ioctl_wait = ioctl_wait_r;
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reg [7:0] cart_do_r;
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always @* begin
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if (~cart_ready)
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cart_do_r = 8'h00;
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else if (is_cram_addr)
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cart_do_r = mbc_cram_do;
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else
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cart_do_r = rom_do;
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end
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assign cart_do = cart_do_r;
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wire [7:0] cram_q_h, cram_q_l;
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wire [7:0] cram_q = cram_addr[0] ? cram_q_h : cram_q_l;
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assign is_cram_addr = ~nCS & ~cart_addr[14];
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assign cram_rd = cart_rd & is_cram_addr;
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assign cram_wr = savestate_ovr ? Savestate_CRAMRWrEn : (cart_wr & is_cram_addr & mbc_ram_enable);
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assign cram_bram_wr = savestate_ovr ? (Savestate_CRAMRWrEn & ~|Savestate_CRAMAddr[16:8]) : mbc_cram_wr;
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assign cram_addr = savestate_ovr ? Savestate_CRAMAddr[16:0] : mbc_cram_addr;
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wire [7:0] cram_di_l = savestate_ovr ? Savestate_CRAMWriteData[ 7:0] : mbc_cram_wr_do;
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wire [7:0] cram_di_h = savestate_ovr ? Savestate_CRAMWriteData[15:8] : mbc_cram_wr_do;
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assign Savestate_CRAM_Q = { cram_q_h, cram_q_l };
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assign bram_save = mbc7 | tama;
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// RAM size
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assign ram_mask_file = // 0 - no ram
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(mbc2 || mbc7 || tama)?8'h01: // mbc2 512x4bits, mbc7 256 bytes EEPROM, TAMA 32 bytes
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(ram_size == 1)?8'h03: // 1 - 2k, 1 bank sd_lba[1:0]
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(ram_size == 2)?8'h0F: // 2 - 8k, 1 bank sd_lba[3:0]
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(ram_size == 3)?8'h3F: // 3 - 32k, 4 banks sd_lba[5:0]
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(ram_size == 5)?8'h7F: // 5 - 64k, 8 banks sd_lba[6:0]
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8'hFF; // 4 - 128k 16 banks sd_lba[7:0] 1111
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|
|
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assign has_save = mbc_battery && (|ram_size || mbc2 || mbc7 || tama);
|
|
|
|
dpram #(7) cram_bram_l (
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|
.clock_a (clk_sys),
|
|
.address_a (cram_addr[7:1]),
|
|
.wren_a (cram_bram_wr & (~cram_addr[0] | savestate_ovr)),
|
|
.data_a (cram_di_l),
|
|
.q_a (cram_q_l),
|
|
|
|
.clock_b (clk_sys),
|
|
.address_b (bk_addr[6:0]),
|
|
.wren_b (bk_wr & ~|bk_addr[16:7]),
|
|
.data_b (bk_data[7:0]),
|
|
.q_b (bk_q[7:0])
|
|
);
|
|
|
|
dpram #(7) cram_bram_h (
|
|
.clock_a (clk_sys),
|
|
.address_a (cram_addr[7:1]),
|
|
.wren_a (cram_bram_wr & (cram_addr[0] | savestate_ovr)),
|
|
.data_a (cram_di_h),
|
|
.q_a (cram_q_h),
|
|
|
|
.clock_b (clk_sys),
|
|
.address_b (bk_addr[6:0]),
|
|
.wren_b (bk_wr & ~|bk_addr[16:7]),
|
|
.data_b (bk_data[15:8]),
|
|
.q_b (bk_q[15:8])
|
|
);
|
|
|
|
endmodule |