mirror of
https://github.com/MiSTer-devel/Gameboy_MiSTer.git
synced 2026-04-19 03:04:09 +00:00
e387e70ef2
RTC fixes Implement KEY0 and OPRI registers HDMA fixes Megaduck audio fixes Bootrom updates (GBA/Fastboot)
335 lines
9.4 KiB
Verilog
335 lines
9.4 KiB
Verilog
module tama (
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input enable,
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input clk_sys,
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input ce_cpu,
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input ce_32k,
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input savestate_load,
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input [63:0] savestate_data,
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inout [63:0] savestate_back_b,
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input has_ram,
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input [3:0] ram_mask,
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input [8:0] rom_mask,
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input [14:0] cart_addr,
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input cart_a15,
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input [7:0] cart_mbc_type,
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input cart_rd,
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input cart_wr,
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input [7:0] cart_di,
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inout cart_oe_b,
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input nCS,
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input cram_rd,
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input [7:0] cram_di,
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inout [7:0] cram_do_b,
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inout [16:0] cram_addr_b,
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inout cram_wr_b,
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inout [7:0] cram_wr_do_b,
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inout [22:0] mbc_addr_b,
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inout ram_enabled_b,
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inout has_battery_b
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);
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wire [22:0] mbc_addr;
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wire ram_enabled;
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wire [7:0] cram_do;
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wire [16:0] cram_addr;
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wire has_battery;
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wire [63:0] savestate_back;
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wire [7:0] cram_wr_do;
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wire cram_wr;
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wire cart_oe;
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assign mbc_addr_b = enable ? mbc_addr : 23'hZ;
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assign cram_do_b = enable ? cram_do : 8'hZ;
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assign cram_addr_b = enable ? cram_addr : 17'hZ;
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assign ram_enabled_b = enable ? ram_enabled : 1'hZ;
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assign has_battery_b = enable ? has_battery : 1'hZ;
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assign savestate_back_b = enable ? savestate_back : 64'hZ;
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assign cram_wr_do_b = enable ? cram_wr_do : 8'hZ;
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assign cram_wr_b = enable ? cram_wr : 1'hZ;
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assign cart_oe_b = enable ? cart_oe : 1'hZ;
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// --------------------- CPU register interface ------------------
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// https://gbdev.gg8.se/forums/viewtopic.php?id=469
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reg unlocked;
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reg [3:0] reg_index;
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reg [4:0] rom_bank_reg;
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reg [7:0] reg_data_in, reg_data_out;
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reg [4:0] reg_addr;
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reg ram_read; // 0: write, 1: read
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reg [1:0] rtc_sel;
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reg reg_start;
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reg cram_wr_r;
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reg ram_io;
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reg prev_cram_rd;
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reg [6:0] rtc_seconds;
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reg [14:0] rtc_subseconds;
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reg [6:0] rtc_minutes;
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reg [5:0] rtc_hours;
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reg [5:0] rtc_days;
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reg [4:0] rtc_month;
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reg [7:0] rtc_year;
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reg rtc_24hours;
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reg [3:0] rtc_index;
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reg [1:0] rtc_leap_year;
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wire sec_inc = &rtc_subseconds;
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reg [5:0] days_in_month;
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always @* begin
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case(rtc_month)
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5'h4, 5'h6, 5'h9, 5'h11: days_in_month = 6'h30;
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5'h2: days_in_month = (rtc_leap_year == 2'b00) ? 6'h29 : 6'h28;
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default: days_in_month = 6'h31;
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endcase
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end
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assign savestate_back[ 4: 0] = rom_bank_reg;
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assign savestate_back[ 5] = unlocked;
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assign savestate_back[ 9: 6] = reg_index;
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assign savestate_back[17:10] = reg_data_in;
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assign savestate_back[25:18] = reg_data_out;
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assign savestate_back[30:26] = reg_addr;
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assign savestate_back[ 31] = ram_read;
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assign savestate_back[33:32] = rtc_sel;
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assign savestate_back[ 34] = reg_start;
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assign savestate_back[ 35] = cram_wr_r;
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assign savestate_back[ 36] = ram_io;
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assign savestate_back[ 37] = prev_cram_rd;
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assign savestate_back[63:38] = 0;
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always @(posedge clk_sys) begin
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if(savestate_load & enable) begin
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rom_bank_reg <= savestate_data[ 4: 0]; //5'd0;
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unlocked <= savestate_data[ 5]; //1'd0;
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reg_index <= savestate_data[ 9: 6]; //4'd0;
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reg_data_in <= savestate_data[17:10]; //8'd0;
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reg_data_out <= savestate_data[25:18]; //8'd0;
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reg_addr <= savestate_data[30:26]; //5'd0;
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ram_read <= savestate_data[ 31]; //1'd0;
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rtc_sel <= savestate_data[33:32]; //2'd0;
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reg_start <= savestate_data[ 34]; //1'd0;
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cram_wr_r <= savestate_data[ 35]; //1'd0;
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ram_io <= savestate_data[ 36]; //1'd0;
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prev_cram_rd <= savestate_data[ 37]; //1'd0;
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end else if(~enable) begin
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rom_bank_reg <= 5'd0;
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unlocked <= 1'd0;
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reg_index <= 4'd0;
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reg_data_in <= 8'd0;
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reg_data_out <= 8'd0;
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reg_addr <= 5'd0;
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ram_read <= 1'd0;
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rtc_sel <= 2'd0;
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reg_start <= 1'd0;
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cram_wr_r <= 1'd0;
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ram_io <= 1'd0;
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prev_cram_rd <= 1'd0;
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end else begin
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if (ce_cpu & cart_wr & ~nCS & ~cart_addr[14]) begin // $A000-BFFF
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if (cart_addr[0]) begin
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reg_index <= cart_di[3:0]; // Register index
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if (cart_di[3:0] == 4'hA) begin
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unlocked <= 1'b1;
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end
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end else if (unlocked) begin
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case (reg_index)
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4'd0: rom_bank_reg[3:0] <= cart_di[3:0];
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4'd1: rom_bank_reg[4] <= cart_di[0];
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4'd4: reg_data_in[3:0] <= cart_di[3:0];
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4'd5: reg_data_in[7:4] <= cart_di[3:0];
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4'd6: { rtc_sel, ram_read, reg_addr[4] } <= cart_di[3:0];
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4'd7: begin
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reg_addr[3:0] <= cart_di[3:0];
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reg_start <= 1'b1;
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end
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default ;
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endcase
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end
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end
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// TODO: Get RTC working. How does the game use the RTC?
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// The in game timer runs at ~16x speed so 1 minute passes every 3.75 seconds.
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// Does the RTC also run 16x speed or only when the Game Boy is on?
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if (ce_32k) begin
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rtc_subseconds <= rtc_subseconds + 1'b1;
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if (sec_inc) begin
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rtc_seconds[3:0] <= rtc_seconds[3:0] + 1'b1;
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if (rtc_seconds[3:0] == 4'h9) begin
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rtc_seconds[3:0] <= 0;
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rtc_seconds[6:4] <= rtc_seconds[6:4] + 1'b1;
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if (rtc_seconds[6:4] == 3'h5) begin
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rtc_seconds[6:4] <= 0;
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rtc_minutes[3:0] <= rtc_minutes[3:0] + 1'b1;
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if (rtc_minutes[3:0] == 4'h9) begin
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rtc_minutes[3:0] <= 0;
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rtc_minutes[6:4] <= rtc_minutes[6:4] + 1'b1;
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if (rtc_minutes[6:4] == 3'h5) begin
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rtc_minutes[6:4] <= 0;
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rtc_hours[3:0] <= rtc_hours[3:0] + 1'b1;
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if (rtc_24hours & rtc_hours[5:0] == 6'h23) begin // 23:59
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rtc_hours[5:0] <= 0;
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end else if (~rtc_24hours & rtc_hours[4:0] == 5'h12) begin // 12:59
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rtc_hours[4:0] <= 5'h1;
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end else if (rtc_hours[3:0] == 4'h9) begin // 9:59
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rtc_hours[3:0] <= 0;
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rtc_hours[5:4] <= rtc_hours[5:4] + 1'b1;
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end
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if (~rtc_24hours & rtc_hours[4:0] == 5'h11) begin // 11:59
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rtc_hours[5] <= ~rtc_hours[5]; // AM/PM
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end
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if ( (rtc_24hours & rtc_hours[5:0] == 6'h23)
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|| (~rtc_24hours & rtc_hours[5] & rtc_hours[4:0] == 5'h11) )
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begin
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rtc_days[3:0] <= rtc_days[3:0] + 1'b1;
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if (rtc_days[3:0] == 4'h9) begin
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rtc_days[3:0] <= 0;
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rtc_days[5:4] <= rtc_days[5:4] + 1'b1;
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end
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if (rtc_days[5:0] == days_in_month) begin
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rtc_days <= 6'h1;
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rtc_month[3:0] <= rtc_month[3:0] + 1'b1;
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if (rtc_month[3:0] == 4'h9) begin
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rtc_month[3:0] <= 0;
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rtc_month[4] <= rtc_month[4] + 1'b1;
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end
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if (rtc_month == 5'h12) begin
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rtc_month <= 5'h1;
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rtc_year[3:0] <= rtc_year[3:0] + 1'b1;
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rtc_leap_year <= rtc_leap_year + 1'b1;
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if (rtc_year[3:0] == 4'h9) begin
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rtc_year[3:0] <= 0;
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rtc_year[7:4] <= rtc_year[7:4] + 1'b1;
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if (rtc_year[7:4] == 4'h9) begin
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rtc_year[7:4] <= 0;
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end
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end
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end
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end
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end
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end
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end
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end
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end
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end
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end
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if (ce_cpu) begin
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cram_wr_r <= 0;
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ram_io <= 0;
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if (reg_start) begin
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reg_start <= 0;
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if (|rtc_sel) begin // RTC
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if (rtc_sel == 2'd1) begin
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case (reg_addr)
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5'h04: begin
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rtc_minutes <= reg_data_in[6:0];
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rtc_seconds <= 0;
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rtc_subseconds <= 0;
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end
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5'h05: rtc_hours <= reg_data_in[5:0];
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5'h06: rtc_index <= 0;
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default: ;
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endcase
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end
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if (rtc_sel == 2'd2) begin
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case ({reg_addr,reg_data_in[3:0]})
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{2'd0, 4'h7}: rtc_days[3:0] <= reg_data_in[7:4];
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{2'd0, 4'h8}: rtc_days[5:4] <= reg_data_in[5:4];
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{2'd0, 4'h9}: rtc_month[3:0] <= reg_data_in[7:4];
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{2'd0, 4'hA}: rtc_month[4] <= reg_data_in[4];
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{2'd0, 4'hB}: rtc_year[3:0] <= reg_data_in[7:4];
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{2'd0, 4'hC}: rtc_year[7:4] <= reg_data_in[7:4];
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{2'd2, 4'hA}: rtc_24hours <= reg_data_in[4];
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{2'd2, 4'hB}: rtc_leap_year <= reg_data_in[5:4];
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default: ;
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endcase
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end
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end else begin // RAM
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cram_wr_r <= ~ram_read;
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ram_io <= 1;
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end
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end
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if (ram_io & ram_read) begin
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reg_data_out <= cram_di;
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end
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prev_cram_rd <= cram_rd;
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if (prev_cram_rd & ~cram_rd & ~cart_addr[0] & |rtc_sel & reg_index[3:1] == 3'b110) begin
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rtc_index <= rtc_index + 1'b1;
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end
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end
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end
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end
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// 0x0000-0x3FFF = Bank 0
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wire [4:0] rom_bank = (~cart_addr[14]) ? 5'd0 : rom_bank_reg;
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// mask address lines to enable proper mirroring
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wire [4:0] rom_bank_m = rom_bank & rom_mask[4:0]; //32
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assign mbc_addr = { 4'b0000, rom_bank_m, cart_addr[13:0] }; // 16k ROM Bank 0-31
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reg [3:0] rtc_do_r;
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always @* begin
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rtc_do_r = 4'h0;
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case(rtc_index)
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4'h0: rtc_do_r[3:0] = rtc_minutes[3:0];
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4'h1: rtc_do_r[2:0] = rtc_minutes[6:4];
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4'h2: rtc_do_r[3:0] = rtc_hours[3:0];
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4'h3: rtc_do_r[1:0] = rtc_hours[5:4];
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4'h4: rtc_do_r[3:0] = rtc_days[3:0];
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4'h5: rtc_do_r[1:0] = rtc_days[5:4];
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4'h6: rtc_do_r[3:0] = rtc_month[3:0];
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4'h7: rtc_do_r[0] = rtc_month[4];
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//4'h8: rtc_do_r[3:0] = rtc_year[3:0]; Year?
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//4'h9: rtc_do_r[3:0] = rtc_year[7:4];
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default: ;
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endcase
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end
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reg [3:0] cram_do_r;
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always @* begin
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cram_do_r = 4'hF;
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if (~cart_addr[0]) begin
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if (~unlocked) begin
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cram_do_r = 4'd0;
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end else
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case(reg_index)
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4'hA: cram_do_r = 4'd1;
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4'hC: cram_do_r = (|rtc_sel) ? rtc_do_r : reg_data_out[3:0]; // Data out low
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4'hD: cram_do_r = (|rtc_sel) ? rtc_do_r : reg_data_out[7:4]; // Data out high
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default: ;
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endcase
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end
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end
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assign cram_wr = cram_wr_r;
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assign cram_wr_do = reg_data_in;
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assign cram_do = { 4'hF, cram_do_r };
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assign cram_addr = { 12'd0, reg_addr };
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assign cart_oe = (cart_rd & ~cart_a15) | (cram_rd & ~cart_addr[0]);
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assign has_battery = 1;
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assign ram_enabled = 0;
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endmodule |