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86 lines
2.1 KiB
Verilog
86 lines
2.1 KiB
Verilog
module misc_mapper (
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input enable,
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input clk_sys,
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input ce_cpu,
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input mapper_sel, // 0: Wisdom Tree, 1: Mani DMG-601
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input savestate_load,
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input [15:0] savestate_data,
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inout [15:0] savestate_back_b,
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input [8:0] rom_mask,
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input [14:0] cart_addr,
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input cart_a15,
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input cart_wr,
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input [7:0] cart_di,
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input [7:0] cram_di,
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inout [7:0] cram_do_b,
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inout [16:0] cram_addr_b,
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inout [22:0] mbc_addr_b,
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inout ram_enabled_b,
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inout has_battery_b
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);
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wire [22:0] mbc_addr;
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wire ram_enabled;
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wire [7:0] cram_do;
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wire [16:0] cram_addr;
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wire has_battery;
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wire [15:0] savestate_back;
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assign mbc_addr_b = enable ? mbc_addr : 23'hZ;
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assign cram_do_b = enable ? cram_do : 8'hZ;
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assign cram_addr_b = enable ? cram_addr : 17'hZ;
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assign ram_enabled_b = enable ? ram_enabled : 1'hZ;
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assign has_battery_b = enable ? has_battery : 1'hZ;
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assign savestate_back_b = enable ? savestate_back : 16'hZ;
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// --------------------- CPU register interface ------------------
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reg [7:0] rom_bank_reg;
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reg map_disable;
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assign savestate_back[ 7: 0] = rom_bank_reg;
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assign savestate_back[ 8] = map_disable;
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assign savestate_back[15: 9] = 0;
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always @(posedge clk_sys) begin
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if(savestate_load & enable) begin
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rom_bank_reg <= savestate_data[ 7: 0]; //8'd0;
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map_disable <= savestate_data[ 8]; //1'b0;
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end else if(~enable) begin
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rom_bank_reg <= 8'd0;
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map_disable <= 1'b0;
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end else if(ce_cpu) begin
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if (cart_wr & ~cart_a15) begin
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if (mapper_sel) begin
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// Mani DMG-601
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if (~map_disable) begin
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rom_bank_reg <= { 5'd0, cart_di[2:0] };
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map_disable <= 1'b1;
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end
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end else begin
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// Wisdom Tree
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rom_bank_reg <= cart_addr[7:0];
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end
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end
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end
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end
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// mask address lines to enable proper mirroring
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wire [7:0] rom_bank = rom_bank_reg & rom_mask[8:1];
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assign mbc_addr = { rom_bank, cart_addr[14:0] };
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assign cram_do = 8'hFF;
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assign cram_addr = { 4'b0000, cart_addr[12:0] };
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assign ram_enabled = 0;
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assign has_battery = 0;
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endmodule |