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e140e715d5
* GBA mode * Megaduck * Rumble * Window start fixes (Ant Soldiers, Mealybug tests) * Custom boot roms
89 lines
2.5 KiB
Verilog
89 lines
2.5 KiB
Verilog
module megaduck (
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input enable,
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input clk_sys,
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input ce_cpu,
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input savestate_load,
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input [15:0] savestate_data,
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inout [15:0] savestate_back_b,
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input has_ram,
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input [1:0] ram_mask,
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input [6:0] rom_mask,
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input [14:0] cart_addr,
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input cart_a15,
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input [7:0] cart_mbc_type,
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input cart_wr,
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input [7:0] cart_di,
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input [7:0] cram_di,
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inout [7:0] cram_do_b,
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inout [16:0] cram_addr_b,
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inout [22:0] mbc_addr_b,
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inout ram_enabled_b,
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inout has_battery_b
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);
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wire [22:0] mbc_addr;
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wire ram_enabled;
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wire [7:0] cram_do;
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wire [16:0] cram_addr;
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wire has_battery;
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wire [15:0] savestate_back;
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assign mbc_addr_b = enable ? mbc_addr : 23'hZ;
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assign cram_do_b = enable ? cram_do : 8'hZ;
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assign cram_addr_b = enable ? cram_addr : 17'hZ;
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assign ram_enabled_b = enable ? ram_enabled : 1'hZ;
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assign has_battery_b = enable ? has_battery : 1'hZ;
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assign savestate_back_b = enable ? savestate_back : 16'hZ;
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// Megaduck banks are pretty simple. They are broken up into chunks of 0x4000. So bank 0
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// is 0-0x3fff, bank 1 is 0x4000-0x7fff and so on. On most carts, only the top 0x4000 of the rom
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// can be bank switched and the bottom is fixed at bank 0. In this case, the bank number is
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// written to address 0x0001. Note that the bank can never be less than 1 for the upper bank.
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// On some roms, a ram address is written instead which changes the entire visible rom space
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// instead of just the upper slot.
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reg [7:0] bank_top, bank_bottom;
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// --------------------- CPU register interface ------------------
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assign savestate_back[ 7: 0] = bank_bottom;
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assign savestate_back[15: 8] = bank_top; // The top bank can never be less than 1
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always @(posedge clk_sys) begin
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if(savestate_load & enable) begin
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bank_bottom <= savestate_data[7:0];
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bank_top <= savestate_data[15:8];
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end else if(~enable) begin
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bank_bottom <= 8'd0;
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bank_top <= 8'd1;
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end else if(ce_cpu) begin
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if (cart_wr) begin
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if (~cart_a15 && cart_addr == 1) begin
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bank_top <= (cart_di[7:0] == 0) ? 8'd1 : cart_di;
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end
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else if (cart_a15 && ~cart_addr[14]) begin
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bank_top <= {cart_di[6:0], 1'b1};
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bank_bottom <= {cart_di[6:0], 1'b0};
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end
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end
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end
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end
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assign mbc_addr = { 1'b0, (cart_addr[14] ? bank_top : bank_bottom), cart_addr[13:0] };
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assign ram_enabled = 0;
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assign cram_do = ram_enabled ? cram_di : 8'hFF;
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assign cram_addr = 17'd0;
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assign has_battery = 0;
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endmodule |