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https://github.com/MiSTer-devel/Gameboy_MiSTer.git
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4ce2e405a1
Fix freezes in Tokyo Disneyland - Fantasy Tour (Minnie's house) & Daiku no Gen-san - Kachikachi no Tonkachi ga Kachi (Stage 1-4)
385 lines
9.8 KiB
Verilog
385 lines
9.8 KiB
Verilog
module mbc7 (
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input enable,
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input reset,
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input clk_sys,
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input ce_cpu,
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input ce_1x, // 4Mhz
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input savestate_load,
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input [15:0] savestate_data,
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inout [15:0] savestate_back_b,
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input [63:0] savestate_data2,
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inout [63:0] savestate_back2_b,
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input [7:0] joystick_analog_x,
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input [7:0] joystick_analog_y,
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input has_ram,
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input [3:0] ram_mask,
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input [8:0] rom_mask,
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input [14:0] cart_addr,
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input cart_a15,
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input [7:0] cart_mbc_type,
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input cart_rd,
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input cart_wr,
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input [7:0] cart_di,
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inout cart_oe_b,
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input nCS,
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input [7:0] cram_di,
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inout [7:0] cram_do_b,
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inout [16:0] cram_addr_b,
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inout cram_wr_b,
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inout [7:0] cram_wr_do_b,
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inout [22:0] mbc_addr_b,
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inout ram_enabled_b,
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inout has_battery_b
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);
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wire [22:0] mbc_addr;
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wire [7:0] cram_do;
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wire [16:0] cram_addr;
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wire cart_oe;
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wire ram_enabled;
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wire has_battery;
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wire [15:0] savestate_back;
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wire [63:0] savestate_back2;
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wire [7:0] cram_wr_do;
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wire cram_wr;
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wire is_cram_addr = ~nCS & ~cart_addr[14];
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assign mbc_addr_b = enable ? mbc_addr : 23'hZ;
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assign cram_do_b = enable ? cram_do : 8'hZ;
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assign cram_addr_b = enable ? cram_addr : 17'hZ;
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assign cart_oe_b = enable ? cart_oe : 1'hZ;
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assign ram_enabled_b = enable ? ram_enabled : 1'hZ;
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assign has_battery_b = enable ? has_battery : 1'hZ;
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assign savestate_back_b = enable ? savestate_back : 16'hZ;
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assign savestate_back2_b = enable ? savestate_back2 : 64'hZ;
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assign cram_wr_do_b = enable ? cram_wr_do : 8'hZ;
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assign cram_wr_b = enable ? cram_wr : 1'hZ;
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// --------------------- CPU register interface ------------------
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reg [6:0] rom_bank_reg;
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reg ram_enable1, ram_enable2;
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reg [15:0] accelerometer_x, accelerometer_y;
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reg accel_latched;
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reg eeprom_di, eeprom_clk, eeprom_cs;
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wire ram_reg_en = ram_enable1 & ram_enable2;
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wire ram_reg_sel = is_cram_addr & ~cart_addr[12]; // $A000-AFFF
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assign savestate_back[ 6: 0] = rom_bank_reg;
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assign savestate_back[ 7] = ram_enable1;
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assign savestate_back[ 8] = ram_enable2;
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assign savestate_back[ 9] = eeprom_di;
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assign savestate_back[ 10] = eeprom_clk;
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assign savestate_back[ 11] = eeprom_cs;
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assign savestate_back[15:12] = 0;
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always @(posedge clk_sys) begin
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if(savestate_load & enable) begin
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rom_bank_reg <= savestate_data[ 6: 0]; //7'd1;
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ram_enable1 <= savestate_data[ 7]; //1'b0;
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ram_enable2 <= savestate_data[ 8]; //1'b0;
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eeprom_di <= savestate_data[ 9]; //1'b0;
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eeprom_clk <= savestate_data[ 10]; //1'b0;
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eeprom_cs <= savestate_data[ 11]; //1'b0;
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end else if(~enable) begin
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rom_bank_reg <= 7'd1;
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ram_enable1 <= 1'b0;
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ram_enable2 <= 1'b0;
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accel_latched <= 1'b0;
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accelerometer_x <= 16'h8000;
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accelerometer_y <= 16'h8000;
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eeprom_di <= 1'b0;
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eeprom_clk <= 1'b0;
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eeprom_cs <= 1'b0;
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end else if(ce_cpu) begin
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if (cart_wr) begin
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if (~cart_a15) begin
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case(cart_addr[14:13])
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2'b00: ram_enable1 <= (cart_di[3:0] == 4'ha); //RAM enable/disable
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2'b01: rom_bank_reg <= cart_di[6:0]; // ROM bank register
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2'b10: ram_enable2 <= (cart_di == 8'h40); //RAM enable/disable
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endcase
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end
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if (ram_reg_en & ram_reg_sel) begin
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case(cart_addr[7:4])
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0: if (cart_di == 8'h55) begin
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accel_latched <= 1'b0;
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accelerometer_x <= 16'h8000;
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accelerometer_y <= 16'h8000;
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end
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1: if (cart_di == 8'hAA && ~accel_latched) begin
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accel_latched <= 1'b1;
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accelerometer_x <= 16'h81D0 - $signed(joystick_analog_x);
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accelerometer_y <= 16'h81D0 - $signed(joystick_analog_y);
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end
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8: { eeprom_cs, eeprom_clk, eeprom_di } <= { cart_di[7:6], cart_di[1] };
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endcase
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end
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end
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end
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end
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wire [7:0] cram_addr_e;
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wire eeprom_do;
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eeprom93LC56 eeprom(
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.enable ( enable ),
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.clk_sys ( clk_sys ),
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.ce ( ce_1x ),
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.data_clk ( eeprom_clk ),
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.data_in ( eeprom_di ),
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.cs ( eeprom_cs ),
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.ram_di ( cram_di ),
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.ram_addr ( cram_addr_e ),
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.ram_wr ( cram_wr ),
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.ram_do ( cram_wr_do ),
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.data_out ( eeprom_do ),
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.savestate_load ( savestate_load ),
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.savestate_data ( savestate_data2 ),
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.savestate_back ( savestate_back2 )
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);
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reg [7:0] cram_do_r;
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always @* begin
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cram_do_r = 8'hFF;
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if (ram_reg_en & ram_reg_sel) begin
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case(cart_addr[7:4])
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2: cram_do_r = accelerometer_x[ 7:0];
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3: cram_do_r = accelerometer_x[15:8];
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4: cram_do_r = accelerometer_y[ 7:0];
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5: cram_do_r = accelerometer_y[15:8];
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6: cram_do_r = 8'h00; // Unknown
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7: cram_do_r = 8'hFF; // Unknown
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8: { cram_do_r[7:6], cram_do_r[1:0] } = { eeprom_cs, eeprom_clk, eeprom_di, eeprom_do };
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default: ;
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endcase
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end
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end
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// 0x0000-0x3FFF = Bank 0
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wire [6:0] rom_bank = (~cart_addr[14]) ? 7'd0 : rom_bank_reg;
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// mask address lines to enable proper mirroring
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wire [6:0] rom_bank_m = rom_bank & rom_mask[6:0]; //512
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assign mbc_addr = { 2'b00, rom_bank_m, cart_addr[13:0] }; // 16k ROM Bank 0-511
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assign cram_do = cram_do_r;
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assign cram_addr = { 9'd0, cram_addr_e };
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assign cart_oe = cart_rd & (~cart_a15 | (ram_reg_en & ram_reg_sel));
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assign has_battery = 1;
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assign ram_enabled = 0; // EEPROM
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endmodule
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// EEPROM
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module eeprom93LC56 (
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input enable,
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input clk_sys,
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input ce,
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input data_clk,
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input data_in,
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input cs,
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input [7:0] ram_di,
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output [7:0] ram_addr,
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output [7:0] ram_do,
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output ram_wr,
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output data_out,
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input savestate_load,
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input [63:0] savestate_data,
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output [63:0] savestate_back
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);
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reg old_data_clk, old_cs;
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reg [9:0] command;
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reg command_start, command_run, command_init;
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reg [4:0] data_clk_cnt;
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reg [16:0] data; // [15:8] = Low byte, [7:0] = High byte
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reg write_en, writing;
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reg [7:0] rw_cnt;
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reg [7:0] ram_addr_r, ram_do_r;
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reg ram_wr_r;
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wire command_write = (command[9:8] == 2'b01);
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wire command_read = (command[9:8] == 2'b10);
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wire command_erase = (command[9:8] == 2'b11);
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wire command_ewds = (command[9:6] == 4'b0000); // Write disable
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wire command_wral = (command[9:6] == 4'b0001); // Fill with value
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wire command_eral = (command[9:6] == 4'b0010); // Fill 0xFF
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wire command_ewen = (command[9:6] == 4'b0011); // Write enable
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assign savestate_back[ 0] = old_data_clk;
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assign savestate_back[ 1] = old_cs;
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assign savestate_back[11: 2] = command;
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assign savestate_back[ 12] = command_start;
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assign savestate_back[ 13] = command_run;
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assign savestate_back[ 14] = command_init;
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assign savestate_back[19:15] = data_clk_cnt;
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assign savestate_back[36:20] = data;
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assign savestate_back[ 37] = write_en;
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assign savestate_back[ 38] = writing;
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assign savestate_back[46:39] = rw_cnt;
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assign savestate_back[54:47] = ram_addr_r;
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assign savestate_back[62:55] = ram_do_r;
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assign savestate_back[ 63] = ram_wr_r;
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always @(posedge clk_sys) begin
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if (savestate_load & enable) begin
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old_data_clk <= savestate_data[ 0];
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old_cs <= savestate_data[ 1];
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command <= savestate_data[11: 2];
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command_start <= savestate_data[ 12];
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command_run <= savestate_data[ 13];
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command_init <= savestate_data[ 14];
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data_clk_cnt <= savestate_data[19:15];
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data <= savestate_data[36:20];
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write_en <= savestate_data[ 37];
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writing <= savestate_data[ 38];
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rw_cnt <= savestate_data[46:39];
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ram_addr_r <= savestate_data[54:47];
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ram_do_r <= savestate_data[62:55];
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ram_wr_r <= savestate_data[ 63];
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end else if (~enable) begin
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old_data_clk <= 0;
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old_cs <= 0;
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command <= 0;
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command_start <= 0;
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command_run <= 0;
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command_init <= 0;
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data_clk_cnt <= 0;
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write_en <= 0;
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writing <= 0;
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ram_wr_r <= 0;
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end else if(ce) begin
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old_data_clk <= data_clk;
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old_cs <= cs;
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if (~cs) begin // Reset
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command_start <= 0;
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command_run <= 0;
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command_init <= 0;
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end else begin
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if (~old_data_clk & data_clk) begin
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data_clk_cnt <= data_clk_cnt + 1'b1;
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if (~command_start & data_in & ~writing) begin
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command_start <= 1;
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data_clk_cnt <= 0;
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end
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if (command_start & ~command_run) begin
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command <= { command[8:0], data_in };
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if (data_clk_cnt == 9) begin
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data_clk_cnt <= 0;
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command_run <= 1;
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command_init <= 1;
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end
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end
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if(command_run) begin
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if (command_read) begin
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data <= { data[15:0], 1'b0 };
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if (data_clk_cnt == 15) begin // Sequential read. Fetch next data
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data_clk_cnt <= 0;
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rw_cnt <= 0;
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command[6:0] <= command[6:0] + 1'b1;
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end
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end
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if (command_write | command_wral) begin
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data <= { data[15:0], data_in };
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end
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end
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end
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if (command_init) begin
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command_init <= 0;
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if (command_ewds)
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write_en <= 0;
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if (command_ewen)
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write_en <= 1;
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if (command_read) begin
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rw_cnt <= 0;
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data[16] <= 1'b0; // Dummy zero bit
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end
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end
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if (command_run) begin
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if(command_read && rw_cnt <= 2) begin // Fetch data
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ram_addr_r <= { command[6:0], rw_cnt[0] };
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case (rw_cnt)
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1: data[15:8] <= ram_di;
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2: data[7:0] <= ram_di;
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default: ;
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endcase
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rw_cnt <= rw_cnt + 1'b1;
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end
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end
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end
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if (old_cs & ~cs & write_en) begin
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if ( (command_erase | command_eral)
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|| ((command_write | command_wral) && data_clk_cnt == 16) ) begin
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writing <= 1;
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rw_cnt <= 0;
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end
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end
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ram_wr_r <= 0;
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if (writing) begin
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ram_wr_r <= 1;
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ram_addr_r <= (command_wral | command_eral) ? rw_cnt : { command[6:0], rw_cnt[0] };
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ram_do_r <= (command_erase | command_eral) ? 8'hFF : (rw_cnt[0] ? data[7:0] : data[15:8]);
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rw_cnt <= rw_cnt + 1'b1;
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if (rw_cnt == ((command_wral | command_eral) ? 255 : 1) ) begin
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writing <= 0;
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end
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end
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end
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end
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assign ram_addr = ram_addr_r;
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assign ram_do = ram_do_r;
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assign ram_wr = ram_wr_r;
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assign data_out = command_run & command_read ? data[16] : ~writing;
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endmodule |